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User’s Manual 16 H8/36079 Group, H8/36077 Group Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series H8/36079 H8/36077 H8/36079GF, H8/36079LF, H8/36078GF, H8/36078LF, H8/36077GF, H8/36077LF, H8/36074GF, H8/36074LF, HD64F36079G HD64F36079L HD64F36078G HD64F36078L HD64F36077G HD64F36077L HD64F36074G HD64F36074L Rev.3.00 2007.
Rev. 3.00 Sep.
Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2.
General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins.
Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module.
Preface The H8/36079 Group and H8/36077 Group are single-chip microcomputers made up of the highspeed H8/300H CPU employing Renesas Technology original architecture as their cores, and the peripheral functions required to configure a system. The H8/300H CPU has an instruction set that is compatible with the H8/300 CPU. Target Users: This manual was written for users who will be using the H8/36079 Group and H8/36077 Group in the design of application systems.
Notes: When using an on-chip emulator (E7, E8) for H8/36079 and H8/36077 program development and debugging, the following restrictions must be noted. 1. The NMI pin is reserved for the E7 or E8, and cannot be used. 2. Pins P85, P86, and P87 cannot be used. In order to use these pins, additional hardware must be provided on the user board. 3. The following areas are used by the E7 or E8, and are not available to the user. H8/36079 Group: H'01F000 to H'01FFFF H8/36077 Group: H'D000 to H'DFFF 4.
H8/36079 Group and H8/36077 Group manuals: Document Title Document No. H8/36079 Group, H8/36077 Group Hardware Manual This manual H8/300H Series Software Manual REJ09B0213 User's manuals for development tools: Document Title Document No.
Contents Section 1 Overview..................................................................................................1 1.1 1.2 1.3 1.4 Features................................................................................................................................. 1 Block Diagram...................................................................................................................... 4 Pin Arrangement ..............................................................................
3.3 3.4 3.5 3.2.4 Interrupt Enable Register 2 (IENR2) .................................................................. 51 3.2.5 Interrupt Flag Register 1 (IRR1)......................................................................... 51 3.2.6 Interrupt Flag Register 2 (IRR2)......................................................................... 53 3.2.7 Wakeup Interrupt Flag Register (IWPR) ............................................................ 53 Reset Exception Handling .......................
5.7 5.8 5.6.2 Pin Connection when Not Using Subclock ......................................................... 91 Prescaler.............................................................................................................................. 91 5.7.1 Prescaler S........................................................................................................... 91 5.7.2 Prescaler W .........................................................................................................
7.5 7.6 7.7 Program/Erase Protection ................................................................................................. 126 7.5.1 Hardware Protection ......................................................................................... 126 7.5.2 Software Protection........................................................................................... 126 7.5.3 Error Protection.................................................................................................
9.8 9.9 9.7.1 Port Control Register 8 (PCR8) ........................................................................ 159 9.7.2 Port Data Register 8 (PDR8)............................................................................. 159 9.7.3 Pin Functions .................................................................................................... 160 Port B ................................................................................................................................ 161 9.8.
Section 12 Timer V .............................................................................................185 12.1 12.2 12.3 12.4 12.5 12.6 Features............................................................................................................................. 185 Input/Output Pins.............................................................................................................. 187 Register Descriptions........................................................................
13.5 13.6 13.4.6 Reset Synchronous PWM Mode ....................................................................... 240 13.4.7 Complementary PWM Mode ............................................................................ 244 13.4.8 Buffer Operation ............................................................................................... 254 13.4.9 Timer Z Output Timing .................................................................................... 262 Interrupts...........................
16.5 16.6 16.7 16.8 16.4.3 Data Transmission ............................................................................................ 305 16.4.4 Serial Data Reception ....................................................................................... 307 Operation in Clock Synchronous Mode............................................................................ 311 16.5.1 Clock.................................................................................................................
17.5 17.6 17.7 17.4.7 Noise Filter ....................................................................................................... 357 17.4.8 Example of Use................................................................................................. 357 Interrupt Request............................................................................................................... 362 Bit Synchronous Circuit.........................................................................................
Section 20 Power Supply Circuit ........................................................................393 20.1 20.2 Power Supply Connection of 5.0-V-Specification Microcontrollers ................................ 393 Power Supply Connection of 3.3-V-Specification Microcontrollers ................................ 394 Section 21 List of Registers.................................................................................395 21.1 21.2 21.3 Register Addresses (Address Order)...........................
Appendix B I/O Port Block Diagrams ...............................................................489 B.1 B.2 I/O Port Block Diagrams .................................................................................................. 489 Port States in Each Operating State .................................................................................. 513 Appendix C Product Code Lineup.....................................................................514 Appendix D Package Dimensions .................
Rev. 3.00 Sep.
Figures Section 1 Overview Figure 1.1 Block Diagram of H8/36079 Group and H8/36077 Group ........................................... 4 Figure 1.2 Pin Arrangement of H8/36079 Group and H8/36077 Group (FP-64K, FP-64A) ............................................................................ 5 Section 2 CPU Figure 2.1 Memory Map............................................................................................................... 11 Figure 2.2 CPU Registers ..........................................
Figure 5.5 Flowchart of Clock Switching with Backup Function Disabled (2) (From External Clock to On-Chip Oscillator Clock).................................................. 82 Figure 5.6 Timing Chart of Switching from On-Chip Oscillator Clock to External Clock............................................................................................................ 83 Figure 5.7 Timing Chart to Switch from External Clock to On-Chip Oscillator Clock .........................................................
Section 10 Figure 10.1 Figure 10.2 Figure 10.3 Figure 10.4 Realtime Clock (RTC) Block Diagram of RTC ........................................................................................... 167 Definition of Time Expression ................................................................................ 173 Initial Setting Procedure .......................................................................................... 176 Example: Reading of Inaccurate Time Data......................................
Figure 13.14 Figure 13.15 Figure 13.16 Figure 13.17 Figure 13.18 Figure 13.19 Figure 13.20 Figure 13.21 Figure 13.22 Figure 13.23 Figure 13.24 Figure 13.25 Figure 13.26 Figure 13.27 Example of Toggle Output Operation ................................................................... 228 Output Compare Timing ....................................................................................... 229 Example of Input Capture Operation Setting Procedure .......................................
Figure 13.45 Figure 13.46 Figure 13.47 Figure 13.48 Figure 13.49 Figure 13.50 Figure 13.51 Figure 13.52 Figure 13.53 Figure 13.54 Figure 13.55 Figure 13.56 Figure 13.57 Example of Output Disable Timing of Timer Z by External Trigger .................... 263 Example of Output Inverse Timing of Timer Z by Writing to TFCR ................... 264 Example of Output Inverse Timing of Timer Z by Writing to POCR ................... 264 IMF Flag Set Timing when Compare Match Occurs .................................
Figure 16.12 Example of SCI3 Reception in Clock Synchronous Mode.................................... 314 Figure 16.13 Sample Serial Reception Flowchart (Clock Synchronous Mode) ......................... 315 Figure 16.14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations (Clock Synchronous Mode) .................................................. 317 Figure 16.15 Example of Inter-Processor Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A)........
Figure 18.5 A/D Conversion Accuracy Definitions (2) .............................................................. 377 Figure 18.6 Analog Input Circuit Example................................................................................. 378 Section 19 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits Figure 19.1 Block Diagram around BGR ................................................................................... 380 Figure 19.
Figure B.15 Figure B.16 Figure B.17 Figure B.18 Figure B.19 Figure B.20 Figure B.21 Figure B.22 Figure B.23 Figure B.24 Figure B.25 Figure B.26 Figure D.1 Figure D.2 Port 6 Block Diagram (P67 to P60) ........................................................................ 503 Port 7 Block Diagram (P76) ................................................................................... 504 Port 7 Block Diagram (P75) ...................................................................................
Tables Section 1 Overview Table 1.1 Pin Functions ............................................................................................................ 6 Section 2 CPU Operation Notation ................................................................................................. 19 Table 2.1 Table 2.2 Data Transfer Instructions....................................................................................... 20 Table 2.3 Arithmetic Operations Instructions (1) ...............................
Table 7.3 Table 7.4 Table 7.5 Table 7.6 Table 7.7 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible ..................................................................................................... 120 Reprogram Data Computation Table .................................................................... 123 Additional-Program Data Computation Table ...................................................... 123 Programming Time ...............................................
Table 16.6 Table 16.7 SSR Status Flags and Receive Data Handling ...................................................... 308 SCI3 Interrupt Requests........................................................................................ 325 Section 17 I2C Bus Interface 2 (IIC2) I2C Bus Interface Pins ........................................................................................... 331 Table 17.1 Table 17.2 Transfer Rate..............................................................................
Appendix Table A.1 Table A.2 Table A.2 Table A.2 Table A.3 Table A.4 Table A.5 Instruction Set ....................................................................................................... 461 Operation Code Map (1) ....................................................................................... 474 Operation Code Map (2) ....................................................................................... 475 Operation Code Map (3) .......................................................
Section 1 Overview Section 1 Overview 1.
Section 1 Overview • On-chip memory Product Classification Flash memory version H8/36079 TM (F-ZTAT version) Group H8/36077 Group Product Model ROM Size 128 Kbytes 6 Kbytes 5.0-V model H8/36079GF HD64F36079G 3.3-V model H8/36079LF HD64F36079L 5.0-V model H8/36078GF HD64F36078G 3.3-V model H8/36078LF HD64F36078L 5.0-V model H8/36077GF HD64F36077G 3.3-V model H8/36077LF HD64F36077L 5.0-V model H8/36074GF HD64F36074G 3.
Section 1 Overview • CPU Operating mode and address space CPU Address Product Classification Product Model Space Flash memory version H8/36079 TM (F-ZTAT version) Group H8/36077 Group 5.0-V model H8/36079GF HD64F36079G 3.3-V model H8/36079LF HD64F36079L 5.0-V model H8/36078GF HD64F36078G 3.3-V model H8/36078LF HD64F36078L 5.0-V model H8/36077GF HD64F36077G 3.3-V model H8/36077LF HD64F36077L 5.0-V model H8/36074GF HD64F36074G 3.
Section 1 Overview Subclock oscillator NMI TEST RES VSS VCC VCL P67/FTIOD1 P66/FTIOC1 P65/FTIOB1 P64/FTIOA1 P63/FTIOD0 P62/FTIOC0 P61/FTIOB0 P60/FTIOA0 P76/TMOV P75/TMCIV P74/TMRIV P72/TXD_2 P71/RXD_2 P70/SCK3_2 P87 P86 P85 Port 1 Port 6 Data bus (lower) Port 7 P57/SCL P56/SDA P55/WKP5/ADTRG P54/WKP4 P53/WKP3 P52/WKP2 P51/WKP1 P50/WKP0 CPU H8/300H Port 8 P30 P31 P32 P33 P34 P35 P36 P37 On-chip oscillator RAM ROM Port 2 IIC2 RTC SCI3 14-bit PWM SCI3_2 Timer Z Watchdog timer Port 3
Section 1 Overview P62/FTIOC0 P61/FTIOB0 NMI P60/FTIOA0 P64/FTIOA1 P65/FTIOB1 P66/FTIOC1 P67/FTIOD1 P85 P86 P87 P20/SCK3 P21/RXD P22/TXD P23 P70/SCK3_2 Pin Arrangement 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P71/RXD_2 49 32 P63/FTIOD0 P72/TXD_2 50 31 P24 P14/IRQ0 51 30 P76/TMOV P15/IRQ1/TMIB1 52 29 P75/TMCIV P16/IRQ2 53 28 P74/TMRIV P17/IRQ3/TRGV 54 27 P57/SCL P33 55 26 P56/SDA P32 56 25 P12 P31 57 24 P11/PWM P30 58 23 P10/TMOW PB3/AN3 59 2
Section 1 Overview 1.4 Pin Functions Table 1.1 Pin Functions Pin No. Type FP-64K FP-64A I/O Functions 12 Input Power supply pin. Connect this pin to the system power supply. VSS 9 Input Ground pin. Connect this pin to the system power supply (0V). AVCC 3 Input Analog power supply pin for the A/D converter. When the A/D converter is not used, connect this pin to the system power supply. VCL 6 Input See section 20, Power Supply Circuit, for a typical connection.
Section 1 Overview Pin No. Type Symbol FP-64K FP-64A I/O Functions Timer V TMOV 30 Output This is an output pin for a waveform generated by the output compare function.
Section 1 Overview Pin No.
Section 2 CPU Section 2 CPU Microcontrollers of the H8/36079 Group and H8/36077 Group have an H8/300H CPU with an internal 32-bit architecture that provides upward compatibility with the H8/300CPU. Products of the H8/36079 Group support an advanced mode with a 16-Mbyte address space while those of the H8/36077 Group support a normal mode with a 64-Kbyte address space.
Section 2 CPU • High-speed operation All frequently-used instructions execute in one or two states 8/16/32-bit register-register add/subtract: 2 state 8 × 8-bit register-register multiply: 14 states 16 ÷ 8-bit register-register divide: 14 states 16 × 16-bit register-register multiply: 22 states 32 ÷ 16-bit register-register divide: 22 states • CPU operating mode H8/36079 Group: Advanced mode H8/36077 Group: Normal mode • Power-down state Transition to power-down state by SLEEP ins
Section 2 CPU 2.1 Address Space and Memory Map Figure 2.1 shows the memory map of the address space of H8/36079 Group and H8/36077 Group.
Section 2 CPU 2.2 Register Configuration The H8/300H CPU has the internal registers shown in figure 2.2. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), and an 8-bit condition-code register (CCR).
Section 2 CPU 2.2.1 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. The general registers are available for use as 32-, 16-, and 8-bit data registers. Figure 2.3 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).
Section 2 CPU Empty area SP (ER7) Stack area Figure 2.4 Relationship between Stack Pointer and Stack Area 2.2.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0).
Section 2 CPU Bit Bit Name Initial Value R/W Description 7 I 1 R/W Interrupt Mask Bit Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence. 6 UI Undefined R/W User Bit Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. 5 H Undefined R/W Half-Carry Flag When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.
Section 2 CPU 2.3 Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.3.1 General Register Data Formats Figure 2.5 shows the data formats in general registers.
Section 2 CPU Data Type General Register Word data Rn Data Format 15 Word data MSB En 15 MSB Longword data 0 LSB 0 LSB ERn 31 16 15 MSB 0 LSB [Legend] ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2.5 General Register Data Formats (2) Rev. 3.00 Sep.
Section 2 CPU 2.3.2 Memory Data Formats Figure 2.6 shows the data formats in memory. The H8/300H CPU can access word data and longword data in memory, however word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, an address error does not occur, however the least significant bit of the address is regarded as 0, so access begins the preceding address. This also applies to instruction fetches.
Section 2 CPU 2.4 Instruction Set 2.4.1 Table of Instructions Classified by Function The H8/300H CPU has 62 instructions. Tables 2.2 to 2.9 summarize the instructions in each functional category. The notation used in tables 2.2 to 2.9 is defined below. Table 2.
Section 2 CPU Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers/address register (ER0 to ER7). Table 2.2 Data Transfer Instructions Instruction Size* Function MOV B/W/L (EAs) → Rd, Rs → (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B (EAs) → Rd Cannot be used in this LSI.
Section 2 CPU Table 2.3 Arithmetic Operations Instructions (1) Instruction Size* Function ADD SUB B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.
Section 2 CPU Table 2.3 Arithmetic Operations Instructions (2) Instruction Size* Function DIVXS B/W Rd ÷ Rs → Rd Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder. CMP B/W/L Rd – Rs, Rd – #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result.
Section 2 CPU Table 2.4 Logic Operations Instructions Instruction Size* Function AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd Performs a logical OR operation on a general register and another general register or immediate data.
Section 2 CPU Table 2.6 Bit Manipulation Instructions (1) Instruction Size* Function BSET B 1 → ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 → ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
Section 2 CPU Table 2.6 Bit Manipulation Instructions (2) Instruction Size* Function BXOR B C ⊕ ( of ) → C XORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B C ⊕ ∼( of ) → C XORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BLD B (
Section 2 CPU Table 2.7 Branch Instructions Instruction Size Function Bcc* Branches to a specified address if a specified condition is true. The branching conditions are listed below.
Section 2 CPU Table 2.8 System Control Instructions Instruction Size* Function TRAPA Starts trap-instruction exception handling. RTE Returns from an exception-handling routine. SLEEP Causes a transition to a power-down state. LDC B/W (EAs) → CCR Moves the source operand contents to the CCR. The CCR size is one byte, but in transfer from memory, data is read by word access. STC B/W CCR → (EAd) Transfers the CCR contents to a destination location.
Section 2 CPU Table 2.9 Block Data Transfer Instructions Instruction Size Function EEPMOV.B if R4L ≠ 0 then Repeat @ER5+ → @ER6+, R4L–1 → R4L Until R4L = 0 else next; EEPMOV.W if R4 ≠ 0 then Repeat @ER5+ → @ER6+, R4–1 → R4 Until R4 = 0 else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed. Rev. 3.00 Sep.
Section 2 CPU 2.4.2 Basic Instruction Formats H8/300H CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op), a register field (r), an effective address extension (EA), and a condition field (cc). Figure 2.7 shows examples of instruction formats. • Operation Field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction.
Section 2 CPU 2.5 Addressing Modes and Effective Address Calculation 2.5.1 Addressing Modes The H8/300H CPU supports the eight addressing modes listed in table 2.10. Each instruction uses a subset of these addressing modes. Addressing modes that can be used differ depending on the instruction. For details, refer to appendix A.4, Combinations of Instructions and Addressing Modes. Arithmetic and logic instructions can use the register direct and immediate modes.
Section 2 CPU (2) Register Indirect@ERn The register field of the instruction code specifies an address register (ERn), the lower 24 bits of which contain the address of the operand on memory. (3) Register Indirect with Displacement@(d:16, ERn) or @(d:24, ERn) A 16-bit or 24-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the lower 24 bits of the sum the address of a memory operand.
Section 2 CPU Table 2.11 Absolute Address Access Ranges Absolute Address Normal Mode Advanced Mode 8 bits (@aa:8) H'FF00 to H'FFFF H'FFFF00 to H'FFFFFF 16 bits (@aa:16) H'0000 to H'FFFF H'000000 to H'007FFF H'FF8000 to H'FFFFFF 24 bits (@aa:24) (6) H'0000 to H'FFFF H'000000 to H'FFFFFF Immediate#xx:8, #xx:16, or #xx:32 The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand.
Section 2 CPU Specified by @aa:8 Dummy Branch address Figure 2.8 Branch Address Specification in Memory Indirect Mode 2.5.2 Effective Address Calculation Table 2.12 indicates how effective addresses are calculated in each addressing mode. For operation in normal mode, the upper 8 bits of the effective address are ignored in order to generate a 16-bit effective address. For operation in advanced mode, the 24-bit result of effective address calculation is generated as the address. Rev. 3.00 Sep.
Section 2 CPU Table 2.12 Effective Address Calculation (1) No 1 Addressing Mode and Instruction Format op 2 Effective Address Calculation Effective Address (EA) Register direct(Rn) rm Operand is general register contents.
Section 2 CPU Table 2.12 Effective Address Calculation (2) No 5 Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Absolute address @aa:8 8 7 23 op abs 0 H'FFFF @aa:16 23 op abs 16 15 0 Sign extension @aa:24 op 0 23 abs 6 Immediate #xx:8/#xx:16/#xx:32 op 7 Operand is immediate data.
Section 2 CPU 2.6 Basic Bus Cycle CPU operation is synchronized by a system clock (φ) or a subclock (φSUB). The period from a rising edge of φ or φSUB to the next rising edge is called one state. A bus cycle consists of two states or three states. The cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules. 2.6.1 Access to On-Chip Memory (RAM, ROM) Access to on-chip memory takes place in two states.
Section 2 CPU 2.6.2 On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits or 16 bits depending on the register. For description on the data bus width and number of accessing states of each register, refer to section 21.1, Register Addresses (Address Order). Registers with 16-bit data bus width can be accessed by word size only. Registers with 8-bit data bus width can be accessed by byte or word size.
Section 2 CPU 2.7 CPU States There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active mode and subactive mode. For the program halt state, there are a sleep mode, standby mode, and sub-sleep mode. These states are shown in figure 2.11. Figure 2.12 shows the state transitions. For details on program execution state and program halt state, refer to section 6, Power-Down Modes.
Section 2 CPU Reset cleared Reset state Exception-handling state Reset occurs Reset occurs Reset occurs Interrupt source Program halt state Interrupt source Exceptionhandling complete Program execution state SLEEP instruction executed Figure 2.12 State Transitions 2.8 Usage Notes 2.8.1 Notes on Data Access to Empty Areas The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip I/O registers areas available to the user.
Section 2 CPU 2.8.3 Bit-Manipulation Instruction The BSET, BCLR, BNOT, BST, and BIST instructions read data from the specified address in byte units, manipulate the data of the target bit, and write data to the same address again in byte units.
Section 2 CPU Example 2: The BSET instruction is executed for port 5. P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at P56. P55 to P50 are output pins and output low-level signals. An example to output a high-level signal at P50 with a BSET instruction is shown below.
Section 2 CPU As a result of the BSET instruction, bit 0 in PDR5 becomes 1, and P50 outputs a high-level signal. However, bits 7 and 6 of PDR5 end up with different values. To prevent this problem, store a copy of the PDR5 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PDR5. • Prior to executing BSET instruction MOV.B MOV.B MOV.
Section 2 CPU (2) Bit manipulation in a register containing a write-only bit Example 3: BCLR instruction executed designating port 5 control register PCR5 P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at P56. P55 to P50 are output pins that output low-level signals. An example of setting the P50 pin as an input pin by the BCLR instruction is shown below. It is assumed that a high-level signal will be input to this input pin.
Section 2 CPU • Prior to executing BCLR instruction MOV.B MOV.B MOV.B #3F, R0L, R0L, R0L @RAM0 @PCR5 The PCR5 value (H'3F) is written to a work area in memory (RAM0) as well as to PCR5.
Section 3 Exception Handling Section 3 Exception Handling Exception handling may be caused by a reset, a trap instruction (TRAPA), or interrupts. • Reset A reset has the highest exception priority. Exception handling starts as soon as the reset is cleared by the RES pin. The chip is also reset when the watchdog timer overflows, and exception handling starts. Exception handling is the same as exception handling by the RES pin.
Section 3 Exception Handling 3.1 Exception Sources and Vector Address Table 3.1 shows the vector addresses and priority of each exception handling. When more than one interrupt is requested, handling is performed from the interrupt with the highest priority. Table 3.
Section 3 Exception Handling Vector Number Relative Module Exception Sources Reserved for system use 20 Timer V Timer V compare match A Timer V compare match B Timer V overflow 22 H'002C to H'002D H'000058 to H'00005B SCI3 23 SCI3 receive data full SCI3 transmit data empty SCI3 transmit end SCI3 receive error H'002E to H'002F H'00005C to H'00005F IIC2 24 Transmit data empty Transmit end Receive data full Arbitration lost/Overrun error NACK detection Stop conditions detected H'0030 to H'0031
Section 3 Exception Handling 3.2 Register Descriptions Interrupts are controlled by the following registers. • Interrupt edge select register 1 (IEGR1) • Interrupt edge select register 2 (IEGR2) • Interrupt enable register 1 (IENR1) • Interrupt enable register 2 (IENR2) • Interrupt flag register 1 (IRR1) • Interrupt flag register 2 (IRR2) • Wakeup interrupt flag register (IWPR) 3.2.
Section 3 Exception Handling 3.2.2 Interrupt Edge Select Register 2 (IEGR2) IEGR2 selects the direction of an edge that generates interrupt requests of the pins ADTRG and WKP5 to WKP0. Bit Bit Name Initial Value R/W Description 7, 6 All 1 Reserved These bits are always read as 1.
Section 3 Exception Handling 3.2.3 Interrupt Enable Register 1 (IENR1) IENR1 enables direct transition interrupts, RTC interrupts, and external pin interrupts. Bit Bit Name Initial Value R/W 7 IENDT 0 R/W Description Direct Transfer Interrupt Enable When this bit is set to 1, direct transition interrupt requests are enabled. 6 IENTA 0 R/W RTC Interrupt Enable When this bit is set to 1, RTC interrupt requests are enabled.
Section 3 Exception Handling 3.2.4 Interrupt Enable Register 2 (IENR2) IENR2 enables, timer B1 overflow interrupts. Bit Bit Name Initial Value R/W Description 7, 6 All 0 Reserved These bits are always read as 0. 5 IENTB1 0 R/W Timer B1 Interrupt Enable When this bit is set to 1, timer B1 overflow interrupt requests are enabled. 4 to 0 All 1 Reserved These bits are always read as 1.
Section 3 Exception Handling Bit Bit Name Initial Value R/W Description 6 IRRTA 0 R/W RTC Interrupt Request Flag [Setting condition] When the RTC counter value overflows [Clearing condition] When IRRTA is cleared by writing 0 5, 4 All 1 Reserved These bits are always read as 1. 3 IRRI3 0 R/W IRQ3 Interrupt Request Flag [Setting condition] When IRQ3 pin is designated for interrupt input and the designated signal edge is detected.
Section 3 Exception Handling 3.2.6 Interrupt Flag Register 2 (IRR2) IRR2 is a status flag register for timer B1 overflow interrupts. Bit Bit Name Initial Value R/W Description 7, 6 All 0 Reserved These bits are always read as 0. 5 IRRTB1 0 R/W Timer B1 Interrupt Request flag [Setting condition] When the timer B1 counter value overflows [Clearing condition] When IRRTB1 is cleared by writing 0 4 to 0 All 1 Reserved These bits are always read as 1. 3.2.
Section 3 Exception Handling Bit Bit Name Initial Value R/W Description 3 IWPF3 0 R/W WKP3 Interrupt Request Flag [Setting condition] When WKP3 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IWPF3 is cleared by writing 0. 2 IWPF2 0 R/W WKP2 Interrupt Request Flag [Setting condition] When WKP2 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IWPF2 is cleared by writing 0.
Section 3 Exception Handling 3.3 Reset Exception Handling When the RES pin goes low, all processing halts and this LSI enters the reset. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized by the reset. To ensure that this LSI is reset at power-up, hold the RES pin low until the clock pulse generator output stabilizes. To reset the chip during operation, hold the RES pin low for at least 10 system clock cycles.
Section 3 Exception Handling 3.4 Interrupt Exception Handling 3.4.1 External Interrupts As the external interrupts, there are NMI, IRQ3 to IRQ0, and WKP5 to WKP0 interrupts. (1) NMI Interrupt NMI interrupt is requested by input signal edge to pin NMI. This interrupt is detected by either rising edge sensing or falling edge sensing, depending on the setting of bit NMIEG in IEGR1. NMI is the highest-priority interrupt, and can always be accepted without depending on the I bit value in CCR.
Section 3 Exception Handling Normal mode operation Reset cleared Internal processing Vector fetch Initial program instruction prefetch RES φ Internal address bus (1) (2) Internal read signal Internal write signal Internal data bus (16 bits) (2) (1) (2) (3) (3) Reset exception handling vector address (H'0000) Program start address Initial program instruction Advanced mode operation Reset cleared Internal processing Vector fetch Initial program instruction prefetch φ RES Internal address bus
Section 3 Exception Handling 3.4.2 Internal Interrupts Each on-chip peripheral module has a flag to show the interrupt request status and the enable bit to enable or disable the interrupt. For RTC interrupt requests and direct transfer interrupt requests generated by execution of a SLEEP instruction, this function is included in IRR1, IRR2, IENR1, and IENR2.
Section 3 Exception Handling Normal mode operation SP - 4 SP (R7) CCR SP - 3 SP + 1 CCR* SP - 2 SP + 2 PCH SP - 1 SP + 3 PCL SP (R7) Stack area Prior to start of interrupt exception handling Even address SP + 4 PC and CCR saved to stack After completion of interrupt exception handling Advanced mode operation SP - 4 SP (R7) SP - 3 SP + 1 PCE SP - 2 SP + 2 PCH SP + 3 PCL SP - 1 SP (R7) Stack area Prior to start of interrupt exception handling CCR Even address SP + 4 PC an
Section 3 Exception Handling 3.4.4 Interrupt Response Time Table 3.2 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handling-routine is executed. Table 3.2 Interrupt Wait States Item States Total 1 to 23 15 to 37 Saving of PC and CCR to stack 4 (17 to 39)* Vector fetch 2 (4)* Instruction fetch 4 Internal processing 4 Waiting time for completion of executing instruction* 1 2 2 Notes: 1.
Section 3 Exception Handling Normal mode operation Interrupt is accepted Interrupt level Instruction decision and wait for end of instruction prefetch Internal processing Prefetch instruction of Internal Vector fetch processing interrupt handling routine Stack access Interrupt request signal φ Internal address bus (1) (3) (5) (6) (8) (9) Internal read signal Internal write signal Internal data bus (16 bits) (2) (4) (1) (1) Instruction prefetch address (Instruction is not executed.
Section 3 Exception Handling 3.5 Usage Notes 3.5.1 Interrupts after Reset If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset.
Section 4 Address Break Section 4 Address Break The address break simplifies on-board program debugging. It requests an address break interrupt when the set break condition is satisfied. The interrupt request is not affected by the I bit of CCR. Break conditions that can be set include instruction execution at a specific address and a combination of access and data at a specific address.
Section 4 Address Break 4.1 Register Descriptions Address break has the following registers. • Address break control register (ABRKCR) • Address break status register (ABRKSR) • Break address register (BARH, BARL) • Break data register (BDRH, BDRL) 4.1.1 Address Break Control Register (ABRKCR) ABRKCR sets address break conditions.
Section 4 Address Break Bit Bit Name Initial Value R/W Description 4 ACMP2 0 R/W Address Compare Condition Select 2 to 0 3 ACMP1 0 R/W 2 ACMP0 0 R/W These bits set the comparison condition between the address set in BAR and the internal address bus.
Section 4 Address Break When an address break is set in the data read cycle or data write cycle, the data bus used will depend on the combination of the byte/word access and address. Table 4.1 shows the access and data bus used. When an I/O register space with an 8-bit data bus width is accessed in word size, a byte access is generated twice. For details on data widths of each register, see section 21.1, Register Addresses (Address Order). Table 4.
Section 4 Address Break 4.1.2 Address Break Status Register (ABRKSR) ABRKSR consists of the address break interrupt flag and the address break interrupt enable bit. Bit Bit Name Initial Value R/W 7 ABIF 0 R/W Description Address Break Interrupt Flag [Setting condition] When the condition set in ABRKCR is satisfied [Clearing condition] When 0 is written after ABIF=1 is read 6 ABIE 0 R/W Address Break Interrupt Enable When this bit is 1, an address break interrupt request is enabled.
Section 4 Address Break 4.2 Operation When the ABIF and ABIE bits in ABRKSR are set to 1, the address break function generates an interrupt request to the CPU. The ABIF bit in ABRKSR is set to 1 by the combination of the address set in BAR, the data set in BDR, and the conditions set in ABRKCR. When the interrupt request is accepted, interrupt exception handling starts after the instruction being executed ends. The address break interrupt is not masked by the I bit in CCR of the CPU. Figures 4.
Section 4 Address Break When the address break is specified in the data read cycle Register setting • ABRKCR = H'A0 • BAR = H'025A Program 0258 025A * 025C 0260 0262 : NOP NOP MOV.W @H'025A,R0 NOP Underline indicates the address NOP to be stacked.
Section 4 Address Break Rev. 3.00 Sep.
Section 5 Clock Pulse Generator Section 5 Clock Pulse Generator The clock pulse generator (CPG) consists of a system clock generating circuitry, a subclock generating circuitry, and two prescalers. The system clock generating circuitry includes an external clock oscillator, a duty correction circuit, an on-chip oscillator, an RC clock divider, a clock select circuit, and a system clock divider. The subclock generating circuitry includes a subclock oscillator, and a subclock divider.
Section 5 Clock Pulse Generator 5.1 Features • Choice of two clock sources On-chip oscillator clock Clock by an external oscillator output • Choice of two types of RC oscillation frequency by the user software 16 MHz 20 MHz • Frequency trimming Since the initial frequency of the on-chip oscillator in the flash memory version is within the range of two frequencies shown above, it is normally unnecessary to trim the frequency. It is, however, still possible to adjust it by rewriting the trimming registers.
Section 5 Clock Pulse Generator 5.2.1 RC Control Register (RCCR) RCCR controls the on-chip oscillator. Bit Bit Name Initial Value R/W 7 RCSTP 0 R/W Description On-Chip Oscillator Standby The on-chip oscillator standby state is entered by setting this bit to 1.
Section 5 Clock Pulse Generator 5.2.2 RC Trimming Data Protect Register (RCTRMDPR) RCTRMDPR controls RCTRMDPR itself and writing to RCTRMDR. Use the MOV instruction to rewrite this register. Bit manipulation instruction cannot change the settings. Bit Bit Name Initial Value R/W Description 7 WRI 1 W Write Inhibit Only when writing 0 to this bit, this register can be written to. This bit is always read as 1.
Section 5 Clock Pulse Generator Initial Value Bit Bit Name 4 TRMDRWE 0 R/W Description R/W Trimming Data Register Write Enable This register can be written to when the LOCKDW bit is 0 and this bit is 1. [Setting condition] • When writing 0 to the WRI bit while writing 1 to the TRMDRWE bit while the PRWE bit is 1 [Clearing conditions] 3 to 0 All 1 • Reset • When writing 0 to the WRI bit and writing 0 to the TRMDRWE bit while the PRWE bit is 1 Reserved These bits are always read as 1.
Section 5 Clock Pulse Generator 5.2.4 Clock Control/Status Register (CKCSR) CKCSR selects the port C function, controls switching the system clocks, and indicates the system clock state.
Section 5 Clock Pulse Generator Bit Bit Name Initial Value R/W Description 4 OSCSEL 0 R/W LSI Operating Clock Select • When OSCBAKE = 0 This bit is used to forcibly select the system clock of this LSI. 0: The on-chip oscillator clock selected as the system clock source 1: The external input selected as the system clock source • When OSCBAKE = 1 This bit is used to switch the on-chip oscillator clock to the external clock.
Section 5 Clock Pulse Generator Bit Bit Name Initial Value R/W Description 1 OSCHLT 1 R External Oscillator Halt Detecting Flag • When OSCBAKE = 1 This bit indicates the checking result of the external oscillator state. 0: External oscillator is running 1: External oscillator is halted. • When OSCBAKE = 0 This bit is non-deterministic; always read as 1. 0 CKSTA 0 R LSI Operating Clock Status 0: This LSI operates on the on-chip oscillator clock. 1: This LSI operates on the external clock.
Section 5 Clock Pulse Generator 5.3 System Clock Select Operation Figure 5.2 shows the state transition of the system clock.
Section 5 Clock Pulse Generator LSI operates on on-chip oscillator clock Start (reset) Write 1 to PMRC0 in CKCSR Write 1 to PMRC1 in CKCSR [1] Write 1 to OSCBAKE in CKCSR [2] Clear CKSWIF in CKCSR to 0 Write 1 to CKSWIE in CKCSR [3] Write 1 to OSCSEL in CKCSR [4] [5] Switched to external clock? (CKSTA in CKCSR is 1) No [1] External oscillation starts to be enabled when pins PC1 and PC0 are specified as external clock pins. Write 0 to bit PMRC1 to input the external clock.
Section 5 Clock Pulse Generator LSI operates on on-chip oscillator clock [1] External oscillation starts to be enabled when pins PC1 and PC0 are specified as external clock pins. Write 0 to bit PMRC1 to input the external clock.
Section 5 Clock Pulse Generator LSI operates on external clock [1] When 0 is written to the OSCSEL bit, this LSI switches from the external clock to the on-chip oscillator clock after a φ stop duration. The φ halt duration here is the duration while the φRC clock rises seven times after the OSCSEL bit becomes 0. Start (LSI operates on external clock) Write 0 to OSCBAKE in CKCSR [2] Writing 0 to PMRC0 disables the external oscillation input.
Section 5 Clock Pulse Generator 5.3.2 Clock Switching Timing The timing for switching clocks are shown in figures 5.6 to 5.8.
Section 5 Clock Pulse Generator φOSC φRC φ OSCSEL PHISTOP (Internal signal) CKSTA CKSWIF External RC clock operation φ halt* On-chip oscillator clock operation [Legend] φOSC: External clock φRC: On-chip oscillator clock φ: System clock OSCSEL: Bit 4 in CKCSR PHISTOP: System clock stop control signal CKSTA: Bit 0 in CKCSR CKSWIF: Bit 2 in CKCSR Note: * The φ halt duration is the duration from the timing when the φ clock stops to the seventh rising edge of the φRC clock. Figure 5.
Section 5 Clock Pulse Generator External clock halt φOSC φRC φ OSCHLT PHISTOP (Internal signal) CKSTA CKSWIF External clock operation φOSC halt detected*1 φ halt*2 On-chip oscillator clock operation Tchk [Legend] φOSC: External clock φRC: On-chip oscillator clock φ: System clock OSCHLT: Bit 1 in CKCSR PHISTOP: System clock stop control signal CKSTA: Bit 0 in CKCSR CKSWIF: Bit 2 in CKCSR Notes: 1. 44 × φRC ≤ Tchk ≤ 48 × φRC 2.
Section 5 Clock Pulse Generator 5.4 Trimming of On-Chip Oscillator Frequency Users can trim the on-chip oscillator clock, supplying the external reference pulses with the input capture function in internal timer Z. An example of trimming flow and a timing chart are shown in figures 5.9 and 5.10, respectively.
Section 5 Clock Pulse Generator φRC FTIOA0 input capture input tA (µs) Timer Z TCNT M−1 GRA_0 M N GRC_0 M+1 M N Capture 1 M+α M+α M Capture 2 Figure 5.10 Timing Chart of Trimming of On-Chip Oscillator Frequency The on-chip oscillator frequency is gained by the expression below. Since the input-capture input is sampled by the φRC clock, the calculated result may include a sampling error of ±1 cycle of the φRC clock.
Section 5 Clock Pulse Generator 5.5 External Oscillators There are two methods to supply external clock pulses into this LSI: connecting a crystal or ceramic resonator, and an external clock. Oscillation pins OSC1 and OSC2 are common with general ports PC0 and PC1, respectively. To set pins PC0 and PC1 as crystal resonator or external clock input ports, refer to section 5.2.4, Clock Control/Status Register (CKCSR). Figure 5.11 shows a block diagram of an external clock oscillator.
Section 5 Clock Pulse Generator LS RS CS PC0/OSC1 PC1/OSC2/CLKOUT CO Figure 5.13 Equivalent Circuit of Crystal Resonator Table 5.1 Crystal Resonator Parameters Frequency (MHz) 4 8 10 16 20 RS (Max.) 120 Ω 80 Ω 60 Ω 50 Ω 40 Ω CO (Max.) 5.5.2 70 pF Connecting Ceramic Resonator Figure 5.14 shows an example of connecting a ceramic resonator. C1 PC0/OSC1 C2 PC1/OSC2/CLKOUT C1 = C 2 = 5 to 30 pF Figure 5.14 Example of Connection to Ceramic Resonator 5.5.
Section 5 Clock Pulse Generator 5.6 Subclock Oscillator Figure 5.16 shows a block diagram of the subclock oscillator. X2 8 MΩ X1 Note : Resistance here is a reference value. Figure 5.16 Block Diagram of Subclock Oscillator 5.6.1 Connecting 32.768-kHz Crystal Resonator Clock pulses can be supplied to the subclock divider by connecting a 32.768-kHz crystal resonator, as shown in figure 5.17. Figure 5.18 shows the equivalent circuit of the 32.768-kHz crystal resonator.
Section 5 Clock Pulse Generator 5.6.2 Pin Connection when Not Using Subclock When the subclock is not used, connect pin X1 to VCL or VSS and leave pin X2 open, as shown in figure 5.19. VCL or VSS X1 X2 Open Figure 5.19 Pin Connection when not Using Subclock 5.7 Prescaler 5.7.1 Prescaler S Prescaler S is a 13-bit counter using the system clock (φ) as its input clock. The outputs, which are divided clocks, are used as internal clocks by the on-chip peripheral modules.
Section 5 Clock Pulse Generator 5.8 Usage Notes 5.8.1 Note on Resonators Resonator characteristics are closely related to board design and should be carefully evaluated by the user, referring to the examples shown in this section. Resonator circuit parameters will differ depending on the resonator element, stray capacitance of the PCB, and other factors. Suitable values should be determined in consultation with the resonator element manufacturer.
Section 6 Power-Down Modes Section 6 Power-Down Modes This LSI has six modes of operation after a reset. These include a normal active mode and four power-down modes, in which power consumption is significantly reduced. Module standby mode reduces power consumption by selectively halting on-chip module functions. • Active mode The CPU and all on-chip peripheral modules are operable on the system clock. The system clock frequency can be selected from φosc, φosc/8, φosc/16, φosc/32, and φosc/64.
Section 6 Power-Down Modes 6.1 Register Descriptions The registers related to power-down modes are listed below. • System control register 1 (SYSCR1) • System control register 2 (SYSCR2) • Module standby control register 1 (MSTCR1) • Module standby control register 2 (MSTCR2) 6.1.1 System Control Register 1 (SYSCR1) SYSCR1 controls the power-down modes, as well as SYSCR2.
Section 6 Power-Down Modes Bit Bit Name Initial Value R/W Description 6 STS2 0 R/W Standby Timer Select 2 to 0 5 STS1 0 R/W 4 STS0 0 R/W These bits set the wait time from when the external clock oscillator starts functioning until the clock is supplied, in shifting from standby mode, subactive mode, or subsleep mode, to active mode or sleep mode. During the wait time, this LSI automatically selects the on-chip oscillator clock as its system clock and counts the number of wait states.
Section 6 Power-Down Modes Table 6.1 Operating Frequency and Waiting Time Bit Name Operating Frequency STS2 STS1 STS0 Waiting Time 20 MHz 16 MHz 10 MHz 8 MHz 5 MHz 4 MHz 0 0 1 1 0 1 0 8,192 states 0.4 0.5 0.8 1.0 1.6 2.0 1 16,384 states 0.8 1.0 1.6 2.0 3.3 4.1 0 32,768 states 1.6 2.0 3.3 4.1 6.6 8.2 1 65,536 states 3.3 4.1 6.6 8.2 13.1 16.4 0 131,072 states 6.6 8.2 13.1 16.4 26.2 32.8 1 1,024 states 0.05 0.06 0.10 0.13 0.20 0.
Section 6 Power-Down Modes 6.1.2 System Control Register 2 (SYSCR2) SYSCR2 controls the power-down modes, as well as SYSCR1. Bit Bit Name Initial Value R/W Description 7 SMSEL 0 R/W Sleep Mode Selection 6 LSON 0 R/W Low Speed on Flag 5 DTON 0 R/W Direct Transfer on Flag These bits select the mode to enter after the execution of a SLEEP instruction, as well as bit SSBY of SYSCR1. For details, see table 6.2.
Section 6 Power-Down Modes 6.1.3 Module Standby Control Register 1 (MSTCR1) MSTCR1 allows the on-chip peripheral modules to enter a standby state in module units. Bit Bit Name Initial Value R/W Description 7 0 Reserved This bit is always read as 0.
Section 6 Power-Down Modes 6.1.4 Module Standby Control Register 2 (MSTCR2) MSTCR2 allows the on-chip peripheral modules to enter a standby state in module units. Bit Bit Name Initial Value R/W 7 MSTS3_2 0 R/W Description SCI3_2 Module Standby SCI3_2 enters standby mode when this bit is set to1 6, 5 All 0 Reserved These bits are always read as 0.
Section 6 Power-Down Modes 6.2 Mode Transitions and States of LSI Figure 6.1 shows the possible transitions among these operating modes. A transition is made from the program execution state to the program halt state by executing a SLEEP instruction. Interrupts allow for returning from the program halt state to the program execution state. A direct transition between active mode and subactive mode, which are both program execution states, can be made without halting the program.
Section 6 Power-Down Modes Table 6.2 Transition Mode after SLEEP Instruction Execution and Transition Mode due to Interrupt DTON SSBY SMSEL LSON Transition Mode after SLEEP Instruction Execution 0 0 0 0 Sleep mode 1 1 0 Active mode Subactive mode Subsleep mode 1 1 Transition Mode due to Interrupt Active mode Subactive mode 1 X X Standby mode Active mode X 0* 0 Active mode (direct transition) X X 1 Subactive mode (direct transition) X: Don’t care.
Section 6 Power-Down Modes Table 6.
Section 6 Power-Down Modes 6.2.1 Sleep Mode In sleep mode, CPU operation is halted but the on-chip peripheral modules function at the clock frequency set by the MA2, MA1, and MA0 bits in SYSCR2. CPU register contents are retained. When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts. Sleep mode is not cleared if the I bit of the condition code register (CCR) is set to 1 or the requested interrupt is disabled in the interrupt enable register.
Section 6 Power-Down Modes 6.2.3 Subsleep Mode In subsleep mode, operation of the CPU and on-chip peripheral modules other than RTC is halted. As long as a required voltage is applied, the contents of CPU registers, the on-chip RAM, and some registers of the on-chip peripheral modules are retained. I/O ports keep the same states as before the transition. Subsleep mode is cleared by an interrupt. When an interrupt is requested, subsleep mode is cleared and interrupt exception handling starts.
Section 6 Power-Down Modes 6.3 Operating Frequency in Active Mode Operation in active mode is clocked at the frequency designated by the MA2, MA1, and MA0 bits in SYSCR2. The operating frequency changes to the set frequency after SLEEP instruction execution. 6.4 Direct Transition The CPU can execute programs in two modes: active and subactive modes. A direct transition is a transition between these two modes without stopping program execution.
Section 6 Power-Down Modes 6.4.2 Direct Transition from Subactive Mode to Active Mode The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (2).
Section 7 ROM Section 7 ROM The features of the flash memory built into this LSI are summarized below. • Programming/erase methods The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units. To erase the entire flash memory, each block must be erased in turn. • Reprogramming capability The flash memory can be reprogrammed up to 1,000 times (Min.).
Section 7 ROM H8/36079GF H8/36079LF H'000000 H'000001 H'000002 Programming unit: 128 bytes H'00007F H'000380 H'000381 H'000382 H'000400 H'000401 H'000402 Programming unit: 128 bytes H'0003FF H'00047F H'000780 H'000781 H'000782 H'000800 H'000801 H'000802 Programming unit: 128 bytes H'0007FF H'00087F H'000B80 H'000B81 H'000B82 H'000C00 H'000C01 H'000C02 Programming unit: 128 bytes H'000BFF H'000C7F H'000F80 H'000F81 H'000F82 H'001000 H'001001 H'001002 Programming unit: 128 bytes H'000FFF H'0010
Section 7 ROM H8/36078GF H8/36078LF H'000000 H'000001 H'000002 Programming unit: 128 bytes H'00007F H'000380 H'000381 H'000382 H'000400 H'000401 H'000402 Programming unit: 128 bytes H'0003FF H'00047F H'000780 H'000781 H'000782 H'000800 H'000801 H'000802 Programming unit: 128 bytes H'0007FF H'00087F H'000B80 H'000B81 H'000B82 H'000C00 H'000C01 H'000C02 Programming unit: 128 bytes H'000BFF H'000C7F H'000F80 H'000F81 H'000F82 H'001000 H'001001 H'001002 Programming unit: 128 bytes H'000FFF H'0010
Section 7 ROM H8/36077GF H8/36077LF H'0000 H'0001 H'0002 Programming unit: 128 bytes H'007F H'0380 H'0400 H'0381 H'0401 H'0382 H'0402 Programming unit: 128 bytes H'03FF H'047F H'0780 H'0800 H'0781 H'0801 H'0782 H'0802 H'0B80 H'0C00 H'0B81 H'0C01 H'0B82 H'0C02 Programming unit: 128 bytes H'0BFF H'0C7F H'0F80 H'1000 H'0F81 H'1001 H'0F82 H'1002 Programming unit: 128 bytes H'0FFF H'107F H'7F80 H'8000 H'7F81 H'8001 H'7F82 H'8002 Programming unit: 128 bytes H'7FFF H'807F H'BF80 H'C000
Section 7 ROM H8/36074GF H8/36074LF H'0000 H'0001 H'0002 Programming unit: 128 bytes H'007F H'0380 H'0400 H'0381 H'0401 H'0382 H'0402 Programming unit: 128 bytes H'03FF H'047F H'0780 H'0800 H'0781 H'0801 H'0782 H'0802 Programming unit: 128 bytes H'07FF H'087F H'0B80 H'0C00 H'0B81 H'0C01 H'0B82 H'0C02 Programming unit: 128 bytes H'0BFF H'0C7F H'0F80 H'1000 H'0F81 H'1001 H'0F82 H'1002 Programming unit: 128 bytes H'0FFF H'107F H'7F80 H'7F81 H'7F82 Erase unit: 1 Kbyte Erase unit: 1
Section 7 ROM 7.2 Register Descriptions The flash memory has the following registers. • Flash memory control register 1 (FLMCR1) • Flash memory control register 2 (FLMCR2) • Erase block register 1 (EBR1) • Flash memory power control register (FLPWCR) • Flash memory enable register (FENR) 7.2.1 Flash Memory Control Register 1 (FLMCR1) FLMCR1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode.
Section 7 ROM Bit Bit Name Initial Value R/W Description 3 EV 0 R/W Erase-Verify When this bit is set to 1, the flash memory changes to erase-verify mode. When it is cleared to 0, erase-verify mode is cancelled. 2 PV 0 R/W Program-Verify When this bit is set to 1, the flash memory changes to program-verify mode. When it is cleared to 0, programverify mode is cancelled. 1 E 0 R/W Erase When this bit is set to 1 while SWE=1 and ESU=1, the flash memory changes to erase mode.
Section 7 ROM 7.2.3 Erase Block Register 1 (EBR1) EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 to be automatically cleared to 0. (1) H8/36079GF and H8/36079LF Bit Initial Bit Name Value R/W Description 7 EB7 0 R/W When this bit is set to 1, 32 Kbytes of H'018000 to H'01FFFF will be erased.
Section 7 ROM (3) H8/36077GF and H8/36077LF Bit Initial Bit Name Value R/W Description 7 0 Reserved. This bit is always read as 0. 6 EB6 0 R/W When this bit is set to 1, 8 Kbytes of H'C000 to H'DFFF will be erased. 5 EB5 0 R/W When this bit is set to 1, 16 Kbytes of H'8000 to H'BFFF will be erased. 4 EB4 0 R/W When this bit is set to 1, 28 Kbytes of H'1000 to H'7FFF will be erased. 3 EB3 0 R/W When this bit is set to 1, 1 Kbyte of H'0C00 to H'0FFF will be erased.
Section 7 ROM 7.2.4 Flash Memory Power Control Register (FLPWCR) FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI switches to subactive mode. There are two modes: mode in which operation of the power supply circuit of flash memory is partly halted in power-down mode and flash memory can be read, and mode in which even if a transition is made to subactive mode, operation of the power supply circuit of flash memory is retained and flash memory can be read.
Section 7 ROM 7.3 On-Board Programming Modes There are two modes for programming/erasing of the flash memory; boot mode, which enables onboard programming/erasing, and programmer mode, in which programming/erasing is performed with a PROM programmer. On-board programming/erasing can also be performed in user program mode. At reset-start in reset mode, this LSI changes to a mode depending on the TEST pin settings, NMI pin settings, and input level of each port, as shown in table 7.1.
Section 7 ROM pulled up on the board if necessary. After the reset is complete, it takes approximately 100 states before the chip is ready to measure the low-level period. 4. After matching the bit rates, the chip transmits one H'00 byte to the host to indicate the completion of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the chip.
Section 7 ROM Boot Mode Operation Host Operation Communication Contents Processing Contents Transfer of number of bytes of programming control program Flash memory erase Bit rate adjustment Boot mode initiation Item Table 7.2 LSI Operation Processing Contents Branches to boot program at reset-start. Boot program initiation Continuously transmits data H'00 at specified bit rate. Transmits data H'55 when data H'00 is received error-free. H'00, H'00 . . .
Section 7 ROM Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible Host Bit Rate System Clock Frequency Range of LSI 9,600 bps 10 MHz 4,800 bps 7.3.2 Programming/Erasing in User Program Mode On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. The user must set branching conditions and provide on-board means of supplying programming data.
Section 7 ROM 7.4 Flash Memory Programming/Erasing A software method using the CPU is employed to program and erase flash memory in the onboard programming modes. Depending on the FLMCR1 setting, the flash memory operates in one of the following four modes: Program mode, program-verify mode, erase mode, and erase-verify mode. The programming control program in boot mode and the user program/erase control program in user program mode use these operating modes in combination to perform programming/erasing.
Section 7 ROM 8. The maximum number of repetitions of the program/program-verify sequence of the same bit is 1,000.
Section 7 ROM Table 7.4 Reprogram Data Computation Table Program Data Verify Data Reprogram Data Comments 0 0 1 Programming completed 0 1 0 Reprogram bit 1 0 1 1 1 1 Remains in erased state Table 7.
Section 7 ROM 7.4.2 Erase/Erase-Verify When erasing flash memory, the erase/erase-verify flowchart shown in figure 7.4 should be followed. 1. Prewriting (setting erase block data to all 0s) is not necessary. 2. Erasing is performed in block units. Make only a single-bit specification in the erase block register (EBR1). To erase multiple blocks, each block must be erased in turn. 3. The time during which the E bit is set to 1 is the flash memory erase time. 4.
Section 7 ROM Erase start SWE bit ← 1 Wait 1 µs n←1 Set EBR1 Enable WDT ESU bit ← 1 Wait 100 µs E bit ← 1 Wait 10 ms E bit ← 0 Wait 10 µs ESU bit ← 10 10 µs Disable WDT EV bit ← 1 Wait 20 µs Set block start address as verify address H'FF dummy write to verify address Wait 2 µs * n←n+1 Read verify data No Verify data + all 1s ? Increment address Yes No Last address of block ? Yes No EV bit ← 0 EV bit ← 0 Wait 4 µs Wait 4µs All erase block erased ? n ≤100 ? Yes Yes No Yes SWE bit ← 0 SWE b
Section 7 ROM 7.5 Program/Erase Protection There are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 7.5.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset, subactive mode, subsleep mode, or standby mode.
Section 7 ROM The FLMCR1, FLMCR2, and EBR1 settings are retained, however program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be reentered by re-setting the P or E bit. However, PV and EV bit settings are retained, and a transition can be made to verify mode. Error protection can be cleared only by a reset. 7.
Section 7 ROM Table 7.7 Flash Memory Operating States Flash Memory Operating State LSI Operating State PDWND = 0 (Initial Value) PDWND = 1 Active mode Normal operating mode Normal operating mode Subactive mode Power-down mode Normal operating mode Sleep mode Normal operating mode Normal operating mode Subsleep mode Standby mode Standby mode Standby mode Standby mode Standby mode Rev. 3.00 Sep.
Section 8 RAM Section 8 RAM Microcontrollers of the H8/36079 Group and H8/36077 Group have an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling two-state access by the CPU to both byte data and word data. Product Classification Flash memory version H8/36079 Group (F-ZTAT version) H8/36077 Group RAM Size RAM Address 5.0-V specification H8/36079GF 3.3-V specification H8/36079LF 5.0-V specification H8/36078GF 3.3-V specification H8/36078LF 5.
Section 8 RAM Rev. 3.00 Sep.
Section 9 I/O Ports Section 9 I/O Ports This LSI has 47 general I/O ports and 8 general input-only ports. Port 6 is a large current port, which can drive 20 mA (@VOL = 1.5 V) when a low level signal is output. Any of these ports can become an input port immediately after a reset. They can also be used as I/O pins of the on-chip peripheral modules or external interrupt input pins, and these functions can be switched depending on the register settings.
Section 9 I/O Ports 9.1.1 Port Mode Register 1 (PMR1) PMR1 switches the functions of pins in port 1 and port 2. Bit Bit Name Initial Value R/W Description 7 IRQ3 0 R/W This bit selects the function of pin P17/IRQ3/TRGV. 0: General I/O port 1: IRQ3/TRGV input pin 6 IRQ2 0 R/W This bit selects the function of pin P16/IRQ2. 0: General I/O port 1: IRQ2 input pin 5 IRQ1 0 R/W This bit selects the function of pin P15/IRQ1/TMIB1.
Section 9 I/O Ports 9.1.2 Port Control Register 1 (PCR1) PCR1 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 1. Bit Bit Name Initial Value R/W Description 7 PCR17 0 W 6 PCR16 0 W 5 PCR15 0 W When the corresponding pin is designated in PMR1 as a general I/O pin, setting a PCR1 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. 4 PCR14 0 W Bit 3 is a reserved bit.
Section 9 I/O Ports 9.1.4 Port Pull-Up Control Register 1 (PUCR1) PUCR1 controls the pull-up MOS in bit units of the pins set as the input ports. Bit Bit Name Initial Value R/W Description 7 PUCR17 0 R/W 6 PUCR16 0 R/W 5 PUCR15 0 R/W Only bits for which PCR1 is cleared are valid. The pull-up MOS of P17 to P14 and P12 to P10 pins enter the onstate when these bits are set to 1, while they enter the off-state when these bits are cleared to 0. 4 PUCR14 0 R/W Bit 3 is a reserved bit.
Section 9 I/O Ports P16/IRQ2 pin Register PMR1 PCR1 Bit Name IRQ2 PCR16 Pin Function Setting value 0 0 P16 input pin 1 P16 output pin x IRQ2 input pin 1 [Legend] x: Don't care. P15/IRQ1/TMIB1 pin Register PMR1 PCR1 Bit Name IRQ1 PCR15 Setting value 0 1 Pin Function 0 P15 input pin 1 P15 output pin x IRQ1 input/TMIB1 input pin [Legend] x: Don't care.
Section 9 I/O Ports P11/PWM pin Register PMR1 PCR1 Bit Name PWM PCR11 Pin Function Setting value 0 0 P11 input pin 1 P11 output pin x PWM output pin 1 [Legend] x: Don't care. P10/TMOW pin Register PMR1 PCR1 Bit Name TMOW PCR10 Setting value 0 1 0 P10 input pin 1 P10 output pin x TMOW output pin [Legend] x: Don't care. Rev. 3.00 Sep.
Section 9 I/O Ports 9.2 Port 2 Port 2 is a general I/O port also functioning as SCI3 I/O pins. Each pin of the port 2 is shown in figure 9.2. The register settings of PMR1and SCI3 have priority for functions of the pins for both uses. P24 P23 Port 2 P22/TXD P21/RXD P20/SCK3 Figure 9.2 Port 2 Pin Configuration Port 2 has the following registers. • Port control register 2 (PCR2) • Port data register 2 (PDR2) • Port mode register 3 (PMR3) 9.2.
Section 9 I/O Ports 9.2.2 Port Data Register 2 (PDR2) PDR2 is a general I/O port data register of port 2. Bit Bit Name Initial Value R/W Description 7 to 5 All 1 Reserved These bits are always read as 1. 4 P24 0 R/W PDR2 stores output data for port 2 pins. 3 P23 0 R/W 2 P22 0 R/W 1 P21 0 R/W If PDR2 is read while PCR2 bits are set to 1, the value stored in PDR2 is read.
Section 9 I/O Ports 9.2.4 Pin Functions The correspondence between the register specification and the port functions is shown below.
Section 9 I/O Ports P21/RXD pin Register SCR3 PCR2 Bit Name RE PCR21 Pin Function Setting Value 0 0 P21 input pin 1 P21 output pin x RXD input pin 1 [Legend] x: Don't care. P20/SCK3 pin Register SCR3 Bit Name CKE1 Setting Value 0 SMR PCR2 CKE0 COM PCR20 0 0 Pin Function 0 P20 input pin 1 P20 output pin 0 0 1 x SCK3 output pin 0 1 x x SCK3 output pin 1 x x x SCK3 input pin [Legend] x: Don't care. Rev. 3.00 Sep.
Section 9 I/O Ports 9.3 Port 3 Port 3 is a general I/O port. Each pin of the port 3 is shown in figure 9.3. P37 P36 P35 P34 Port 3 P33 P32 P31 P30 Figure 9.3 Port 3 Pin Configuration Port 3 has the following registers. • Port control register 3 (PCR3) • Port data register 3 (PDR3) 9.3.1 Port Control Register 3 (PCR3) PCR3 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 3.
Section 9 I/O Ports 9.3.2 Port Data Register 3 (PDR3) PDR3 is a general I/O port data register of port 3. Bit Bit Name Initial Value R/W Description 7 P37 0 R/W PDR3 stores output data for port 3 pins. 6 P36 0 R/W 5 P35 0 R/W 4 P34 0 R/W If PDR3 is read while PCR3 bits are set to 1, the value stored in PDR3 is read. If PDR3 is read while PCR3 bits are cleared to 0, the pin states are read regardless of the value stored in PDR3.
Section 9 I/O Ports P35 pin Register PCR3 Bit Name PCR35 Pin Function Setting Value 0 P35 input pin 1 P35 output pin P34 pin Register PCR3 Bit Name PCR34 Pin Function Setting Value 0 P34 input pin 1 P34 output pin P33 pin Register PCR3 Bit Name PCR33 Pin Function Setting Value 0 P33 input pin 1 P33 output pin P32 pin Register PCR3 Bit Name PCR32 Pin Function Setting Value 0 P32 input pin 1 P32 output pin Rev. 3.00 Sep.
Section 9 I/O Ports P31 pin Register PCR3 Bit Name PCR31 Pin Function Setting Value 0 P31 input pin 1 P31 output pin P30 pin Register PCR3 Bit Name PCR30 Pin Function Setting Value 0 P30 input pin 1 P30 output pin Rev. 3.00 Sep.
Section 9 I/O Ports 9.4 Port 5 2 Port 5 is a general I/O port also functioning as an I C bus interface I/O pin, an A/D trigger input pin, and wakeup interrupt input pin. Each pin of the port 5 is shown in figure 9.4. The register 2 setting of the I C bus interface register has priority for functions of the pins P57/SCL and P56/SDA.
Section 9 I/O Ports 9.4.1 Port Mode Register 5 (PMR5) PMR5 switches the functions of pins in port 5. Bit Bit Name Initial Value R/W Description 7 POF57 0 R/W 6 POF56 0 R/W When the bit is set to 1, the corresponding pin is cut off by PMOS and it functions as the NMOS open-drain output. When cleared to 0, the pin functions as the CMOS output. 5 WKP5 0 R/W This bit selects the function of pin P55/WKP5/ADTRG.
Section 9 I/O Ports 9.4.2 Port Control Register 5 (PCR5) PCR5 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 5. Bit Bit Name Initial Value R/W Description 7 PCR57 0 W 6 PCR56 0 W 5 PCR55 0 W When each of the port 5 pins P57 to P50 functions as a general I/O port, setting a PCR5 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port.
Section 9 I/O Ports 9.4.4 Port Pull-Up Control Register 5 (PUCR5) PUCR5 controls the pull-up MOS in bit units of the pins set as the input ports. Bit Bit Name Initial Value R/W Description 7, 6 All 0 Reserved These bits are always read as 0. 5 PUCR55 0 R/W 4 PUCR54 0 R/W 3 PUCR53 0 R/W 2 PUCR52 0 R/W 1 PUCR51 0 R/W 0 PUCR50 0 R/W 9.4.5 Pin Functions Only bits for which PCR5 is cleared are valid.
Section 9 I/O Ports P56/SDA pin Register ICCR1 PCR5 Bit Name ICE PCR56 Pin Function Setting Value 0 0 P56 input pin 1 P56 output pin x SDA I/O pin 1 [Legend] x: Don't care. SDA performs the NMOS open-drain output that enables a direct bus drive. P55/WKP5/ADTRG pin Register PMR5 PCR5 Bit Name WKP5 PCR55 Pin Function Setting Value 0 0 P55 input pin 1 P55 output pin x WKP5/ADTRG input pin 1 [Legend] x: Don't care.
Section 9 I/O Ports P53/WKP3 pin Register PMR5 PCR5 Bit Name WKP3 PCR53 Pin Function Setting Value 0 0 P53 input pin 1 P53 output pin x WKP3 input pin 1 [Legend] x: Don't care. P52/WKP2 pin Register PMR5 PCR5 Bit Name WKP2 PCR52 Setting Value 0 1 Pin Function 0 P52 input pin 1 P52 output pin x WKP2 input pin [Legend] x: Don't care.
Section 9 I/O Ports 9.5 Port 6 Port 6 is a general I/O port also functioning as a timer Z I/O pin. Each pin of the port 6 is shown in figure 9.5. The register setting of the timer Z has priority for functions of the pins for both uses. P67/FTIOD1 P66/FTIOC1 P65/FTIOB1 P64/FTIOA1 Port 6 P63/FTIOD0 P62/FTIOC0 P61/FTIOB0 P60/FTIOA0 Figure 9.5 Port 6 Pin Configuration Port 6 has the following registers. • Port control register 6 (PCR6) • Port data register 6 (PDR6) 9.5.
Section 9 I/O Ports 9.5.2 Port Data Register 6 (PDR6) PDR6 is a general I/O port data register of port 6. Bit Bit Name Initial Value R/W Description 7 P67 0 R/W Stores output data for port 6 pins. 6 P66 0 R/W 5 P65 0 R/W 4 P64 0 R/W If PDR6 is read while PCR6 bits are set to 1, the value stored in PDR6 are read. If PDR6 is read while PCR6 bits are cleared to 0, the pin states are read regardless of the value stored in PDR6.
Section 9 I/O Ports P66/FTIOC1 pin Register TOER TFCR Bit Name EC1 IOC2 to CMD1 and CMD0 PWMC1 IOC0 PCR66 Pin Function 00 0 P66 input/FTIOC1 input pin 1 P66 output pin x FTIOC1 output pin Setting Value 1 0 00 TPMR 0 TIORC1 000 or 1xx 0 001 or 01x 1 xxx Other than x 00 xxx TIORA1 PCR6 [Legend] x: Don't care.
Section 9 I/O Ports P64/FTIOA1 pin Register TOER TFCR TIORA1 PCR6 Bit Name EB1 CMD1 to CMD0 IOA2 to IOA0 PCR64 xx 000 or 1xx Setting Value 1 0 Pin Function 0 P64 input/FTIOA1 input pin 1 P64 output pin 00 001 or 01x x FTIOA1 output pin TIORC0 PCR6 [Legend] x: Don't care.
Section 9 I/O Ports P61/FTIOB0 pin Register TOER TFCR TPMR Bit Name EB0 CMD1 to CMD0 IOB2 to PWMB0 IOB0 PCR61 Pin Function 00 0 0 P61 input/FTIOB0 input pin 1 P61 output pin x FTIOB0 output pin Setting Value 1 0 00 TIORA0 000 or 1xx 0 001 or 01x 1 xxx Other than x 00 xxx PCR6 [Legend] x: Don't care.
Section 9 I/O Ports 9.6 Port 7 Port 7 is a general I/O port also functioning as a timer V I/O pin and SCI3_2 I/O pin. Each pin of the port 7 is shown in figure 9.6. The register settings of the timer V and SCI3_2 have priority for functions of the pins for both uses. P76/TMOV P75/TMCIV P74/TMRIV Port 7 P72/TXD_2 P71/RXD_2 P70/SCK3_2 Figure 9.6 Port 7 Pin Configuration Port 7 has the following registers. • Port control register 7 (PCR7) • Port data register 7 (PDR7) 9.6.
Section 9 I/O Ports 9.6.2 Port Data Register 7 (PDR7) PDR7 is a general I/O port data register of port 7. Bit Bit Name Initial Value R/W Description 7 1 Stores output data for port 7 pins. 6 P76 0 R/W 5 P75 0 R/W 4 P74 0 R/W If PDR7 is read while PCR7 bits are set to 1, the value stored in PDR7 are read. If PDR7 is read while PCR7 bits are cleared to 0, the pin states are read regardless of the value stored in PDR7. 3 1 2 P72 0 R/W 1 P71 0 R/W 0 P70 0 R/W 9.
Section 9 I/O Ports P74/TMRIV pin Register PCR7 Bit Name PCR74 Pin Function Setting Value 0 P74 input/TMRIV input pin 1 P74 output/TMRIV input pin P72/TXD_2 pin Register PMR1 PCR7 Bit Name TXD2 PCR72 Pin Function Setting Value 0 0 P72 input pin 1 P72 output pin x TXD_2 output pin 1 [Legend] x: Don't care. P71/RXD_2 pin Register SCR3_2 PCR7 Bit Name RE PCR71 Pin Function Setting Value 0 0 P71 input pin 1 P71 output pin x RXD_2 input pin 1 [Legend] x: Don't care.
Section 9 I/O Ports 9.7 Port 8 Port 8 is a general I/O port. Each pin of the port 8 is shown in figure 9.7. P87 Port 8 P86 P85 Figure 9.7 Port 8 Pin Configuration Port 8 has the following registers. • Port control register 8 (PCR8) • Port data register 8 (PDR8) 9.7.1 Port Control Register 8 (PCR8) PCR8 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 8.
Section 9 I/O Ports 9.7.3 Pin Functions The correspondence between the register specification and the port functions is shown below. P87 pin Register PCR8 Bit Name PCR87 Pin Function Setting Value 0 P87 input pin 1 P87 output pin P86 pin Register PCR8 Bit Name PCR86 Pin Function Setting Value 0 P86 input pin 1 P86 output pin P85 pin Register PCR8 Bit Name PCR85 Pin Function Setting Value 0 P85 input pin 1 P85 output pin Rev. 3.00 Sep.
Section 9 I/O Ports 9.8 Port B Port B is an input port also functioning as an A/D converter analog input pin. Each pin of the port B is shown in figure 9.8. PB7/AN7/ExtU PB6/AN6/ExtD PB5/AN5 PB4/AN4 Port B PB3/AN3 PB2/AN2 PB1/AN1 PB0/AN0 Figure 9.8 Port B Pin Configuration Port B has the following register. • Port data register B (PDRB) 9.8.1 Port Data Register B (PDRB) PDRB is a general input-only port data register of port B.
Section 9 I/O Ports 9.8.2 Pin Functions The correspondence between the register specification and the port functions is shown below. PB0/AN0 pin Register Bit Name ADCSR SCAN Setting Value 0 CH2 CH1 CH0 Pin Function 0 0 0 AN0 input pin x x 1 Other than above PB0 output pin [Legend] x: Don't care. PB1/AN1 pin Register Bit Name ADCSR SCAN Setting Value 0 CH2 CH1 CH0 Pin Function 0 0 1 AN1 input pin 0 1 1 x 1 Other than above PB1 output pin [Legend] x: Don't care.
Section 9 I/O Ports PB3/AN3 pin Register Bit Name ADCSR SCAN Setting Value 0 CH2 CH1 CH0 Pin Function 0 1 1 AN3 input pin 1 Other than above PB3 output pin PB4/AN4 pin Register Bit Name ADCSR SCAN Setting Value 0 CH2 CH1 CH0 Pin Function 1 0 0 AN4 input pin x x 1 Other than above PB4 output pin [Legend] x: Don't care.
Section 9 I/O Ports PB6/AN6/ExtD pin Register Bit Name ADCSR SCAN CH2 Setting Value 0 LVDCR CH1 1 CH0 VDDII Pin Function 0 0 AN6 input/ExtD input pin 1 AN6 input pin 0 PB6 input/ExtD input pin 1 PB6 input pin 1 x 0 0 1 x Other than above [Legend] x: Don't care.
Section 9 I/O Ports 9.9 Port C Port C is a general I/O port also functioning as an external oscillation pin and clock output pin. Each pin of the port C is shown in figure 9.9. The register setting of CKCSR has priority for functions of the pins for both uses. PC1/OSC2/CLKOUT Port C PC0/OSC1 Figure 9.9 Port C Pin Configuration Port C has the following registers. • Port control register C (PCRC) • Port data register C (PDRC) 9.9.
Section 9 I/O Ports 9.9.2 Port Data Register C (PDRC) PDRC is a general I/O port data register of port C. Bit Bit Name Initial Value R/W Description 7 to 2 Reserved 1 PC1 0 R/W These bits store output data for port C pins. 0 PC0 0 R/W If PDRC is read while PCRC bits are set to 1, the value stored in PDRC is read. If PDRC is read while PCRC bits are cleared to 0, the pin states are read regardless of the value stored in PDRC. 9.9.
Section 10 Realtime Clock (RTC) Section 10 Realtime Clock (RTC) The realtime clock (RTC) is a timer used to count time ranging from a second to a week. Figure 10.1 shows the block diagram of the RTC. 10.
Section 10 Realtime Clock (RTC) 10.2 Input/Output Pin Table 10.1 shows the RTC input/output pin. Table 10.1 Pin Configuration Name Abbreviation I/O Function Clock output TMOW Output RTC divided clock output Rev. 3.00 Sep.
Section 10 Realtime Clock (RTC) 10.3 Register Descriptions The RTC has the following registers. • Second data register/free running counter data register (RSECDR) • Minute data register (RMINDR) • Hour data register (RHRDR) • Day-of-week data register (RWKDR) • RTC control register 1 (RTCCR1) • RTC control register 2 (RTCCR2) • Clock source select register (RTCCSR) 10.3.1 Second Data Register/Free Running Counter Data Register (RSECDR) RSECDR counts the BCD-coded second value.
Section 10 Realtime Clock (RTC) 10.3.2 Minute Data Register (RMINDR) RMINDR counts the BCD-coded minute value on the carry generated once per minute by the RSECDR counting. The setting range is decimal 00 to 59. Bit Bit Name Initial Value R/W Description 7 BSY — R RTC Busy This bit is set to 1 when the RTC is updating (operating) the values of second, minute, hour, and day-of-week data registers.
Section 10 Realtime Clock (RTC) 10.3.3 Hour Data Register (RHRDR) RHRDR counts the BCD-coded hour value on the carry generated once per hour by RMINDR. The setting range is either decimal 00 to 11 or 00 to 23 by the selection of the 12/24 bit in RTCCR1. Bit Bit Name Initial Value R/W Description 7 BSY — R RTC Busy This bit is set to 1 when the RTC is updating (operating) the values of second, minute, hour, and day-of-week data registers.
Section 10 Realtime Clock (RTC) 10.3.4 Day-of-Week Data Register (RWKDR) RWKDR counts the BCD-coded day-of-week value on the carry generated once per day by RHRDR. The setting range is decimal 0 to 6 using bits WK2 to WK0. Bit Bit Name Initial Value R/W Description 7 BSY — R RTC Busy This bit is set to 1 when the RTC is updating (operating) the values of second, minute, hour, and day-of-week data registers.
Section 10 Realtime Clock (RTC) 10.3.5 RTC Control Register 1 (RTCCR1) RTCCR1 controls start/stop and reset of the clock timer. For the definition of time expression, see figure 10.2. Bit Bit Name Initial Value R/W Description 7 RUN — R/W RTC Operation Start 0: Stops RTC operation 1: Starts RTC operation 6 12/24 — R/W Operating Mode 0: RTC operates in 12-hour mode. RHRDR counts on 0 to 11. 1: RTC operates in 24-hour mode. RHRDR counts on 0 to 23. 5 PM — R/W a.m./p.m. 0: Indicates a.m.
Section 10 Realtime Clock (RTC) 10.3.6 RTC Control Register 2 (RTCCR2) RTCCR2 controls RTC periodic interrupts of weeks, days, hours, minutes, and seconds. Enabling interrupts of weeks, days, hours, minutes, and seconds sets the IRRTA flag to 1 in the interrupt flag register 1 (IRR1) when an interrupt occurs. It also controls an overflow interrupt of a free running counter when RTC operates as a free running counter.
Section 10 Realtime Clock (RTC) 10.3.7 Clock Source Select Register (RTCCSR) RTCCSR selects clock source. A free running counter controls start/stop of counter operation by the RUN bit in RTCCR1. When a clock other than 32.768 kHz is selected, the RTC is disabled and operates as an 8-bit free running counter. When the RTC operates as an 8-bit free running counter, RSECDR enables counter values to be read.
Section 10 Realtime Clock (RTC) 10.4 Operation 10.4.1 Initial Settings of Registers after Power-On The RTC registers that store second, minute, hour, and day-of week data are not reset by a RES input. Therefore, all registers must be set to their initial values after power-on. Once the register setting are made, the RTC provides an accurate time as long as power is supplied regardless of a RES input. 10.4.2 Initial Setting Procedure Figure 10.3 shows the procedure for the initial setting of the RTC.
Section 10 Realtime Clock (RTC) 10.4.3 Data Reading Procedure When the seconds, minutes, hours, or day-of-week datum is updated while time data is being read, the data obtained may not be correct, and so the time data must be read again. Figure 10.4 shows an example in which correct data is not obtained. In this example, since only RSECDR is read after data update, about 1-minute inconsistency occurs. To avoid reading in this timing, the following processing must be performed. 1.
Section 10 Realtime Clock (RTC) 10.5 Interrupt Sources There are five kinds of RTC interrupts: week interrupts, day interrupts, hour interrupts, minute interrupts, and second interrupts. When using an interrupt, initiate the RTC last after other registers are set. Do not set multiple interrupt enable bits in RTCCR2 simultaneously to 1. When an interrupt request of the RTC occurs, the IRRTA flag in IRR1 is set to 1. When clearing the flag, write 0. Table 10.
Section 11 Timer B1 Section 11 Timer B1 Timer B1 is an 8-bit timer that increments each time a clock pulse is input. This timer has two operating modes, interval and auto reload. Figure 11.1 shows a block diagram of timer B1. 11.1 Features • Selection of seven internal clock sources (φ/8192, φ/2048, φ/512, φ/256, φ/64, φ/16, and φ/4) or an external clock (can be used to count external events). • An interrupt is generated when the counter overflows.
Section 11 Timer B1 11.2 Input/Output Pin Table 11.1 shows the timer B1 pin configuration. Table 11.1 Pin Configuration Name Abbreviation I/O Function Timer B1 event input TMIB1 Input Event input to TCB1 Rev. 3.00 Sep.
Section 11 Timer B1 11.3 Register Descriptions The timer B1 has the following registers. • Timer mode register B1 (TMB1) • Timer counter B1 (TCB1) • Timer load register B1 (TLB1) 11.3.1 Timer Mode Register B1 (TMB1) TMB1 selects the auto-reload function and input clock. Bit Bit Name Initial Value R/W Description 7 TMB17 0 R/W Auto-reload function select 0: Interval timer function selected 1: Auto-reload function selected 6 to 3 All 1 Reserved These bits are always read as 1.
Section 11 Timer B1 11.3.2 Timer Counter B1 (TCB1) TCB1 is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock source for input to this counter is selected by bits TMB12 to TMB10 in TMB1. TCB1 values can be read by the CPU at any time. When TCB1 overflows from H'FF to H'00 or to the value set in TLB1, the IRRTB1 flag in IRR2 is set to 1. TCB1 is allocated to the same address as TLB1. TCB1 is initialized to H'00. 11.3.
Section 11 Timer B1 11.4.2 Auto-Reload Timer Operation Setting bit TMB17 in TMB1 to 1 causes timer B1 to function as an 8-bit auto-reload timer. When a reload value is set in TLB1, the same value is loaded into TCB1, becoming the value from which TCB1 starts its count. After the count value in TCB1 reaches H'FF, the next clock signal input causes timer B1 to overflow. The TLB1 value is then loaded into TCB1, and the count continues from that value.
Section 11 Timer B1 Rev. 3.00 Sep.
Section 12 Timer V Section 12 Timer V Timer V is an 8-bit timer based on an 8-bit counter. Timer V counts external events. Comparematch signals with two registers can also be used to reset the counter, request an interrupt, or output a pulse signal with an arbitrary duty cycle. Counting can be initiated by a trigger input at the TRGV pin, enabling pulse output control to be synchronized to the trigger, with an arbitrary delay from the trigger input. Figure 12.1 shows a block diagram of timer V. 12.
Section 12 Timer V TCRV1 TCORB Trigger control TRGV Comparator TCNTV Internal data bus Clock select TMCIV Comparator φ PSS TCORA TMRIV Clear control TCRV0 Interrupt request control TMOV [Legend] TCORA: TCORB: TCNTV: TCSRV: TCRV0: TCRV1: PSS: CMIA: CMIB: OVI: Output control TCSRV Time constant register A Time constant register B Timer counter V Timer control/status register V Timer control register V0 Timer control register V1 Prescaler S Compare-match interrupt A Compare-match interrupt B
Section 12 Timer V 12.2 Input/Output Pins Table 12.1 shows the timer V pin configuration. Table 12.1 Pin Configuration Name Abbreviation I/O Function Timer V output TMOV Output Timer V waveform output Timer V clock input TMCIV Input Clock input to TCNTV Timer V reset input TMRIV Input External input to reset TCNTV Trigger input TRGV Input Trigger input to initiate counting 12.3 Register Descriptions Time V has the following registers.
Section 12 Timer V 12.3.2 Time Constant Registers A and B (TCORA, TCORB) TCORA and TCORB have the same function. TCORA and TCORB are 8-bit read/write registers. TCORA and TCNTV are compared at all times. When the TCORA and TCNTV contents match, CMFA is set to 1 in TCSRV. If CMIEA is also set to 1 in TCRV0, a CPU interrupt is requested. Note that they must not be compared during the T3 state of a TCORA write cycle.
Section 12 Timer V Bit Bit Name Initial Value R/W Description 2 CKS2 0 R/W Clock Select 2 to 0 1 CKS1 0 R/W 0 CKS0 0 R/W These bits select clock signals to input to TCNTV and the counting condition in combination with ICKS0 in TCRV1. Refer to table 12.2. Table 12.
Section 12 Timer V Bit Bit Name Initial Value R/W Description 6 CMFA 0 R/W Compare Match Flag A Setting condition: When the TCNTV value matches the TCORA value Clearing condition: After reading CMFA = 1, cleared by writing 0 to CMFA 5 OVF 0 R/W Timer Overflow Flag Setting condition: When TCNTV overflows from H'FF to H'00 Clearing condition: After reading OVF = 1, cleared by writing 0 to OVF 4 1 3 OS3 0 R/W Output Select 3 and 2 2 OS2 0 R/W These bits select an output method
Section 12 Timer V 12.3.5 Timer Control Register V1 (TCRV1) TCRV1 selects the edge at the TRGV pin, enables TRGV input, and selects the clock input to TCNTV. Bit Bit Name Initial Value R/W Description 7 to 5 All 1 Reserved These bits are always read as 1. 4 TVEG1 0 R/W TRGV Input Edge Select 3 TVEG0 0 R/W These bits select the TRGV input edge.
Section 12 Timer V 12.4 Operation 12.4.1 Timer V Operation 1. According to table 12.2, six internal/external clock signals output by prescaler S can be selected as the timer V operating clock signals. When the operating clock signal is selected, TCNTV starts counting-up. Figure 12.2 shows the count timing with an internal clock signal selected, and figure 12.3 shows the count timing with both edges of an external clock signal selected. 2.
Section 12 Timer V φ Internal clock TCNTV input clock TCNTV N–1 N N+1 Figure 12.2 Increment Timing with Internal Clock φ TMCIV (External clock input pin) TCNTV input clock TCNTV N–1 N N+1 Figure 12.3 Increment Timing with External Clock φ TCNTV H'FF H'00 Overflow signal OVF Figure 12.4 OVF Set Timing Rev. 3.00 Sep.
Section 12 Timer V φ TCNTV N TCORA or TCORB N N+1 Compare match signal CMFA or CMFB Figure 12.5 CMFA and CMFB Set Timing φ Compare match A signal Timer V output pin Figure 12.6 TMOV Output Timing φ Compare match A signal TCNTV N H'00 Figure 12.7 Clear Timing by Compare Match Rev. 3.00 Sep.
Section 12 Timer V φ TMRIV (External counter reset input pin) TCNTV reset signal N–1 TCNTV N H'00 Figure 12.8 Clear Timing by TMRIV Input 12.5 Timer V Application Examples 12.5.1 Pulse Output with Arbitrary Duty Cycle Figure 12.9 shows an example of output of pulses with an arbitrary duty cycle. 1. Set bits CCLR1 and CCLR0 in TCRV0 so that TCNTV will be cleared by compare match with TCORA. 2.
Section 12 Timer V 12.5.2 Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input The trigger function can be used to output a pulse with an arbitrary pulse width at an arbitrary delay from the TRGV input, as shown in figure 12.10. To set up this output: 1. Set bits CCLR1 and CCLR0 in TCRV0 so that TCNTV will be cleared by compare match with TCORB. 2. Set bits OS3 to OS0 in TCSRV so that the output will go to 1 at compare match with TCORA and to 0 at compare match with TCORB. 3.
Section 12 Timer V 12.6 Usage Notes The following types of contention or operation can occur in timer V operation. 1. Writing to registers is performed in the T3 state of a TCNTV write cycle. If a TCNTV clear signal is generated in the T3 state of a TCNTV write cycle, as shown in figure 12.11, clearing takes precedence and the write to the counter is not carried out. If counting-up is generated in the T3 state of a TCNTV write cycle, writing takes precedence. 2.
Section 12 Timer V TCORA write cycle by CPU T1 T2 T3 φ Address TCORA address Internal write signal TCNTV N N+1 TCORA N M TCORA write data Compare match signal Inhibited Figure 12.12 Contention between TCORA Write and Compare Match Clock before switching Clock after switching Count clock TCNTV N N+1 N+2 Write to CKS1 and CKS0 Figure 12.13 Internal Clock Switching and TCNTV Operation Rev. 3.00 Sep.
Section 13 Timer Z Section 13 Timer Z The timer Z has a 16-bit timer with two channels. Figures 13.1, 13.2, and 13.3 show the block diagrams of entire timer Z, its channel 0, and its channel 1, respectively. For details on the timer Z functions, refer to table 13.1. 13.
Section 13 Timer Z • Eleven interrupt sources Four compare match/input capture interrupts and an overflow interrupt are available for each channel. An underflow interrupt can be set for channel 1. Table 13.
Section 13 Timer Z ITMZ0 FTIOA0 ITMZ1 FTIOB0 FTIOC0 FTIOD0 Control logic FTIOA1 FTIOB1 FTIOC1 FTIOD1 φ, φ/2, φ/4, φ/8 ADTRG Channel 0 timer Channel 1 timer TSTR TMDR TPMR TFCR TOER TOCR Module data bus [Legend] TSTR: Timer start register (8 bits) TMDR: Timer mode register (8 bits) TPMR: Timer PWM mode register (8 bits) TFCR: Timer function control register (8 bits) TOER: Timer output master enable register (8 bits) TOCR: Timer output control register (8 bits) ADTRG: A/D conversio
Section 13 Timer Z FTIOA0 FTIOB0 φ, φ/2, φ/4, φ/8 FTIOC0 Clock select FTIOD0 Control logic ITMZ0 Module data bus [Legend] TCNT_0: GRA_0, GRB_0, GRC_0, GRD_0: TCR_0: TIORA_0: TIORC_0: TSR_0: TIER_0: POCR_0: ITMZ0: Timer counter_0 (16 bits) General registers A_0, B_0, C_0, and D_0 (input capture/output compare registers: 16 bits × 4) Timer control register_0 (8 bits) Timer I/O control register A_0 (8 bits) Timer I/O control register C_0 (8 bits) Timer status register_0 (8 bits) Timer interrupt enabl
Section 13 Timer Z FTIOA1 FTIOB1 φ, φ/2, φ/4, φ/8 FTIOC1 Clock select FTIOD1 Control logic ITMZ1 POCR_1 TIER_1 TSR_1 TIORC_1 TIORA_1 TCR_1 GRD_1 GRC_1 GRB_1 GRA_1 TCNT_1 Comparator Module data bus [Legend] TCNT_1: GRA_1, GRB_1, GRC_1, GRD_1: TCR_1: TIORA_1: TIORC_1: TSR_1: TIER_1: POCR_1: ITMZ1: Timer counter_1 (16 bits) General registers A_1, B_1, C_1, and D_1 (input capture/output compare registers: 16 bits × 4) Timer control register_1 (8 bits) Timer I/O control register A_1 (8 bits
Section 13 Timer Z 13.2 Input/Output Pins Table 13.2 summarizes the timer Z pins. Table 13.
Section 13 Timer Z 13.3 Register Descriptions The timer Z has the following registers.
Section 13 Timer Z • General register C_1 (GRC_1) • General register D_1 (GRD_1) 13.3.1 Timer Start Register (TSTR) TSTR selects the operation/stop for the TCNT counter. Bit Bit Name Initial Value R/W Description 7 to 2 All 1 Reserved These bits are always read as 1, and cannot be modified. 1 STR1 0 R/W Channel 1 Counter Start 0: TCNT_1 halts counting 1: TCNT_1 starts counting 0 STR0 0 R/W Channel 0 Counter Start 0: TCNT_0 halts counting 1: TCNT_0 starts counting 13.3.
Section 13 Timer Z Bit Bit Name Initial Value R/W Description 4 BFC0 0 R/W Buffer Operation C0 0: GRC_0 operates normally 1: GRA_0 and GRC_0 are used together for buffer operation 3 to 1 All 1 Reserved These bits are always read as 1, and cannot be modified. 0 SYNC 0 R/W Timer Synchronization 0: TCNT_1 and TCNT_0 operate as a different timer counter 1: TCNT_1 and TCNT_0 are synchronized TCNT_1 and TCNT_0 can be pre-set or cleared synchronously 13.3.
Section 13 Timer Z Bit Bit Name Initial Value R/W Description 2 PWMD0 0 R/W PWM Mode D0 0: FTIOD0 operates normally 1: FTIOD0 operates in PWM mode 1 PWMC0 0 R/W PWM Mode C0 0: FTIOC0 operates normally 1: FTIOC0 operates in PWM mode 0 PWMB0 0 R/W PWM Mode B0 0: FTIOB0 operates normally 1: FTIOB0 operates in PWM mode 13.3.4 Timer Function Control Register (TFCR) TFCR selects the settings and output levels for each operating mode.
Section 13 Timer Z Bit Bit Name Initial Value R/W Description 3 OLS1 0 R/W Output Level Select 1 Selects the counter-phase output levels in reset synchronous PWM mode or complementary PWM mode. 0: Initial output is high and the active level is low. 1: Initial output is low and the active level is high. 2 OLS0 0 R/W Output Level Select 0 Selects the normal-phase output levels in reset synchronous PWM mode or complementary PWM mode. 0: Initial output is high and the active level is low.
Section 13 Timer Z TCNT_0 TCNT_1 Normal phase Normal phase Active level Active level Counter phase Counter phase Initial output Initial output Active level Active level Reset synchronous PWM mode Complementary PWM mode Note: Write H'00 to TOCR to start initial outputs after stopping the counter. Figure 13.4 Example of Outputs in Reset Synchronous PWM Mode and Complementary PWM Mode 13.3.5 Timer Output Master Enable Register (TOER) TOER enables/disables the outputs for channel 0 and channel 1.
Section 13 Timer Z Bit Bit Name Initial Value R/W Description 5 EB1 1 R/W Master Enable B1 0: FTIOB1 pin output is enabled according to the TPMR, TFCR, and TIORA_1 settings 1: FTIOB1 pin output is disabled regardless of the TPMR, TFCR, and TIORA_1 settings (FTIOB1 pin is operated as an I/O port).
Section 13 Timer Z 13.3.6 Timer Output Control Register (TOCR) TOCR selects the initial outputs before the first occurrence of a compare match. Note that bits OLS1 and OLS0 in TFCR set these initial outputs in reset synchronous PWM mode and complementary PWM mode.
Section 13 Timer Z 13.3.7 Timer Counter (TCNT) The timer Z has two TCNT counters (TCNT_0 and TCNT_1), one for each channel. The TCNT counters are 16-bit readable/writable registers that increment/decrement according to input clocks. Input clocks can be selected by bits TPSC2 to TPSC0 in TCR. TCNT0 and TCNT 1 increment/decrement in complementary PWM mode, while they only increment in other modes.
Section 13 Timer Z 13.3.9 Timer Control Register (TCR) The TCR registers select a TCNT counter clock, an edge when an external clock is selected, and counter clearing sources. Timer Z has a total of two TCR registers, one for each channel.
Section 13 Timer Z 13.3.10 Timer I/O Control Register (TIORA and TIORC) The TIOR registers control the general registers (GR). Timer Z has four TIOR registers (TIORA_0, TIORA_1, TIORC_0, and TIORC_1), two for each channel. In PWM mode including complementary PWM mode and reset synchronous PWM mode, the settings of TIOR are invalid. TIORA: TIORA selects whether GRA or GRB is used as an output compare register or an input capture register.
Section 13 Timer Z Bit Bit Name Initial value R/W Description 2 IOA2 0 R/W I/O Control A2 to A0 1 IOA1 0 R/W GRA is an output compare register: 0 IOA0 0 R/W 000: Disables pin output by compare match 001: 0 output by GRA compare match 010: 1 output by GRA compare match 011: Toggle output by GRA compare match GRA is an input capture register: 100: Input capture to GRA at the rising edge 101: Input capture to GRA at the falling edge 11X: Input capture to GRA at both rising and falling edges
Section 13 Timer Z Bit Bit Name Initial value R/W Description 2 IOC2 0 R/W I/O Control C2 to C0 1 IOC1 0 R/W GRC is an output compare register: 0 IOC0 0 R/W 000: Disables pin output by compare match 001: 0 output by GRC compare match 010: 1 output by GRC compare match 011: Toggle Output by GRC compare match GRC is an input capture register: 100: Input capture to GRC at the rising edge 101: Input capture to GRC at the falling edge 11X: Input capture to GRC at both rising and falling edges
Section 13 Timer Z 13.3.11 Timer Status Register (TSR) TSR indicates generation of an overflow/underflow of TCNT and a compare match/input capture of GRA, GRB, GRC, and GRD. These flags are interrupt sources. If an interrupt is enabled by a corresponding bit in TIER, TSR requests an interrupt for the CPU. Timer Z has two TSR registers, one for each channel. Bit Bit Name Initial value R/W Description 7, 6 All 1 Reserved These bits are always read as 1.
Section 13 Timer Z Bit Bit Name Initial value R/W Description 2 IMFC 0 R/W Input Capture/Compare Match Flag C [Setting conditions] • When TCNT = GRC and GRC is functioning as output compare register • When TCNT value is transferred to GRC by input capture signal and GRC is functioning as input capture register [Clearing condition] • 1 IMFB 0 R/W When 0 is written to IMFC after reading IMFC = 1 Input Capture/Compare Match Flag B [Setting conditions] • When TCNT = GRB and GRB is functionin
Section 13 Timer Z 13.3.12 Timer Interrupt Enable Register (TIER) TIER enables or disables interrupt requests for overflow or GR compare match/input capture. Timer Z has two TIER registers, one for each channel. Bit Bit Name Initial value R/W Description 7 to 5 All 1 Reserved 4 OVIE 0 R/W These bits are always read as 1.
Section 13 Timer Z 13.3.13 PWM Mode Output Level Control Register (POCR) POCR control the active level in PWM mode. Timer Z has two POCR registers, one for each channel. Bit Bit Name Initial value R/W Description 7 to 3 All 1 Reserved 2 POLD 0 R/W These bits are always read as 1.
Section 13 Timer Z 13.3.14 Interface with CPU 1. 16-bit register TCNT and GR are 16-bit registers. Reading/writing in a 16-bit unit is enabled but disabled in an 8-bit unit since the data bus with the CPU is 16-bit width. These registers must always be accessed in a 16-bit unit. Figure 13.5 shows an example of accessing the 16-bit registers. Internal data bus H C P L Module data bus Bus interface U TCNTH TCNTL Figure 13.5 Accessing Operation of 16-Bit Register (between CPU and TCNT (16 bits)) 2.
Section 13 Timer Z 13.4 Operation 13.4.1 Counter Operation When one of bits STR0 and STR1 in TSTR is set to 1, the TCNT counter for the corresponding channel begins counting. TCNT can operate as a free-running counter, periodic counter, for example. Figure 13.7 shows an example of the counter operation setting procedure.
Section 13 Timer Z 1. Free-running count operation and periodic count operation Immediately after a reset, the TCNT counters for channels 0 and 1 are all designated as freerunning counters. When the relevant bit in TSTR is set to 1, the corresponding TCNT counter starts an increment operation as a free-running counter. When TCNT overflows, the OVF flag in TSR is set to 1. If the value of the OVIE bit in the corresponding TIER is 1 at this point, timer Z requests an interrupt.
Section 13 Timer Z TCNT value Counter cleared by GR compare match GR value H'0000 Time STR IMF Figure 13.9 Periodic Counter Operation 2. TCNT count timing A. Internal clock operation A system clock (φ) or three types of clocks (φ/2, φ/4, or φ/8) that divides the system clock can be selected by bits TPSC2 to TPSC0 in TCR. Figure 13.10 illustrates this timing. φ Internal clock TCNT input TCNT N-1 N N+1 Figure 13.10 Count Timing at Internal Clock Operation Rev. 3.00 Sep.
Section 13 Timer Z B. External clock operation An external clock input pin (TCLK) can be selected by bits TPSC2 to TPSC0 in TCR, and a detection edge can be selected by bits CKEG1 and CKEG0. To detect an external clock, the rising edge, falling edge, or both edges can be selected. The pulse width of the external clock needs two or more system clocks. Note that an external clock does not operate correctly with the lower pulse width. Figure 13.
Section 13 Timer Z 13.4.2 Waveform Output by Compare Match Timer Z can perform 0, 1, or toggle output from the corresponding FTIOA, FTIOB, FTIOC, or FTIOD output pin using compare match A, B, C, or D. Figure 13.12 shows an example of the setting procedure for waveform output by compare match.
Section 13 Timer Z TCNT value H'FFFF Time H'0000 FTIOB No change FTIOA No change No change No change Figure 13.13 Example of 0 Output/1 Output Operation Figure 13.14 shows an example of toggle output. In this example, TCNT has been designated as a periodic counter (with counter clearing on compare match B), and settings have been made such that the output is toggled by both compare match A and compare match B.
Section 13 Timer Z 2. Output compare timing The compare match signal is generated in the last state in which TCNT and GR match (when TCNT changes from the matching value to the next value). When the compare match signal is generated, the output value selected in TIOR is output at the compare match output pin (FTIOA, FTIOB, FTIOC, or FTIOD). When TCNT matches GR, the compare match signal is generated only after the next TCNT input clock pulse is input. Figure 13.
Section 13 Timer Z Input selection Select input edge of input capture [1] Start counter operation [2] [1] Designate GR as an input capture register by means of TIOR, and select rising edge, falling edge, or both edges as the input edge of the input capture signal. [2] Set the STR bit in TSTR to 1 to start the TCNT counter operation. Figure 13.16 Example of Input Capture Operation Setting Procedure Rev. 3.00 Sep.
Section 13 Timer Z 1. Example of input capture operation Figure 13.17 shows an example of input capture operation. In this example, both rising and falling edges have been selected as the FTIOA pin input capture input edge, the falling edge has been selected as the FTIOB pin input capture input edge, and counter clearing by GRB input capture has been designated for TCNT.
Section 13 Timer Z 2. Input capture signal timing Input capture on the rising edge, falling edge, or both edges can be selected through settings in TIOR. Figure 13.18 shows the timing when the rising edge is selected. The pulse width of the input capture signal must be at least two system clock (φ) cycles. φ Input capture input Input capture signal TCNT N GR N Figure 13.18 Input Capture Signal Timing Rev. 3.00 Sep.
Section 13 Timer Z 13.4.4 Synchronous Operation In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables GR to be increased with respect to a single time base. Figure 13.19 shows an example of the synchronous operation setting procedure.
Section 13 Timer Z Figure 13.20 shows an example of synchronous operation. In this example, synchronous operation has been selected, FTIOB0 and FTIOB1 have been designated for PWM mode, GRA_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 counter clearing source. In addition, the same input clock has been set as the counter input clock for channel 0 and channel 1. Two-phase PWM waveforms are output from pins FTIOB0 and FTIOB1.
Section 13 Timer Z Table 13.3 Initial Output Level of FTIOB0 Pin TOB0 POLB Initial Output Level 0 0 1 0 1 0 1 0 0 1 1 1 PWM mode Select counter clock [1] Select counter clearing source [2] Set PWM mode [3] Set initial output level [4] Select output level [5] Set GR [6] Enable waveform output [7] Start counter operation [8] [1] Select the counter clock with bits TPSC2 to TOSC0 in TCR.
Section 13 Timer Z Figure 13.22 shows an example of operation in PWM mode. The output signals go to 1 and TCNT is reset at compare match A, and the output signals go to 0 at compare match B, C, and D (TOB, TOC, and TOD = 0, POLB, POLC, and POLD = 0). Counter cleared by GRA compare match TCNT value GRA GRB GRC GRD H'0000 Time FTIOB FTIOC FTIOD Figure 13.22 Example of PWM Mode Operation (1) Rev. 3.00 Sep.
Section 13 Timer Z Figure 13.23 shows another example of operation in PWM mode. The output signals go to 0 and TCNT is reset at compare match A, and the output signals go to 1 at compare match B, C, and D (TOB, TOC, and TOD = 0, POLB, POLC, and POLD = 1). Counter cleared by GRA compare match TCNT value GRA GRB GRC GRD H'0000 Time FTIOB FTIOC FTIOD Figure 13.23 Example of PWM Mode Operation (2) Figures 13.24 (when TOB, TOC, and TOD = 0, POLB, POLC, and POLD = 0) and 13.
Section 13 Timer Z TCNT value GRB rewritten GRA GRB GRB rewritten Time H'0000 0% duty FTIOB TCNT value GRB rewritten When cycle register and duty register compare matches occur simultaneously, duty register compare match has priority. GRA GRB rewritten GRB rewritten GRB H'0000 Time FTIOB 100% duty When cycle register and duty register compare matches occur simultaneously, duty register compare match has priority.
Section 13 Timer Z TCNT value GRB rewritten GRA GRB GRB rewritten H'0000 Time FTIOB 0% duty TCNT value GRB rewritten When cycle register and duty register compare matches occur simultaneously, duty register compare match has priority. GRA GRB rewritten GRB rewritten GRB Time H'0000 100% duty FTIOB When cycle register and duty register compare matches occur simultaneously, duty register compare match has priority.
Section 13 Timer Z 13.4.6 Reset Synchronous PWM Mode Three normal- and counter-phase PWM waveforms are output by combining channels 0 and 1 that one of changing points of waveforms will be common. In reset synchronous PWM mode, the FTIOB0 to FTIOD0 and FTIOA1 to FTIOD1 pins become PWM-output pins automatically. TCNT_0 performs an increment operation. Tables 13.4 and 13.5 show the PWM-output pins used and the register settings, respectively. Figure 13.
Section 13 Timer Z Reset synchronous PWM mode Stop counter operation [1] Select counter clock [2] Select counter clearing source [3] Set reset synchronous PWM mode [4] Initialize the output pin [5] Set TCNT [6] Set GR [7] Enable waveform output [8] Start counter operation [9] [1] Clear bit STR0 in TSTR to 0 and stop the counter operation of TCNT_0. Set reset synchronous PWM mode after TCNT_0 stops. [2] Select the counter clock with bits TPSC2 to TOSC0 in TCR.
Section 13 Timer Z Figures 13.27 and 13.28 show examples of operation in reset synchronous PWM mode. Counter cleared by GRA compare match TCNT value GRA_0 GRB_0 GRA_1 GRB_1 H'0000 Time FTIOB0 FTIOD0 FTIOA1 FTIOC1 FTIOB1 FTIOD1 FTIOC0 Figure 13.27 Example of Reset Synchronous PWM Mode Operation (OLS0 = OLS1 = 1) Rev. 3.00 Sep.
Section 13 Timer Z Counter cleared by GRA compare match TCNT value GRA_0 GRB_0 GRA_1 GRB_1 H'0000 Time FTIOB0 FTIOD0 FTIOA1 FTIOC1 FTIOB1 FTIOD1 FTIOC0 Figure 13.28 Example of Reset Synchronous PWM Mode Operation (OLS0 = OLS1 = 0) In reset synchronous PWM mode, TCNT_0 and TCNT_1 perform increment and independent operations, respectively. However, GRA_1 and GRB_1 are separated from TCNT_1.
Section 13 Timer Z 13.4.7 Complementary PWM Mode Three PWM waveforms for non-overlapped normal and counter phases are output by combining channels 0 and 1. In complementary PWM mode, the FTIOB0 to FTIOD0 and FTIOA1 to FTIOD1 pins become PWM-output pins automatically. TCNT_0 and TCNT_1 perform an increment or decrement operation. Tables 13.6 and 13.7 show the output pins and register settings in complementary PWM mode, respectively. Figure 13.
Section 13 Timer Z Complementary PWM mode Stop counter operation [1] Initialize output pin [2] Select counter clock [3] Set complementary PWM mode [4] Initialize output pin [5] Set TCNT [6] Set GR [7] Enable waveform output [8] Start counter operation [9] [1] Clear bits STR0 and STR1 in TSTR to 0, and stop the counter operation of TCNT_0. Stop TCNT_0 and TCNT_1 and set complementary PWM mode. [2] Write H'00 to TOCR.
Section 13 Timer Z 1. Canceling Procedure of Complementary PWM Mode: Figure 13.30 shows the complementary PWM mode canceling procedure. Complementary PWM mode Stop counter operation [1] Cancel complementary PWM mode [2] [1] Clear bit CMD1 in TFCR to 0, and set channels 0 and 1 to normal operation. [2] After setting channels 0 and 1 to normal operation, clear bits STR0 and STR1 in TSTR to 0 and stop TCNT0 and TCNT1. Figure 13.30 Canceling Procedure of Complementary PWM Mode Rev.
Section 13 Timer Z 2. Examples of Complementary PWM Mode Operation: Figure 13.31 shows an example of complementary PWM mode operation. In complementary PWM mode, TCNT_0 and TCNT_1 perform an increment or decrement operation. When TCNT_0 and GRA_0 are compared and their contents match, the counter is decremented, and when TCNT_1 underflows, the counter is incremented.
Section 13 Timer Z Figure 13.32 (1) and (2) show examples of PWM waveform output with 0% duty and 100% duty in complementary PWM mode (for one phase). • TPSC2 = TPSC1 = TPSC0 = 0 Set GRB_0 to H'0000 or a value equal to or more than GRA_0. The waveform with a duty cycle of 0% and 100% can be output. When buffer operation is used together, the duty cycles can easily be changed, including the above settings, during operation. For details on buffer operation, refer to section 13.4.8, Buffer Operation.
Section 13 Timer Z TCNT values GRA0 GRB0 H'0000 Time FTIOB0 FTIOD0 0% duty (a) When duty is 0% TCNT values GRA0 GRB0 H'0000 Time FTIOB0 FTIOD0 100% duty (b) When duty is 100% Figure 13.32 (1) Example of Complementary PWM Mode Operation (TPSC2 = TPSC1 = TPSC0 = 0) (2) Rev. 3.00 Sep.
Section 13 Timer Z TCNT values GRA0 GRB0 H'0000 Time FTIOB0 FTIOD0 0% duty (a) When duty is 0% TCNT values GRA0 GRB0 H'0000 Time FTIOB0 FTIOD0 100% duty (b) When duty is 100% Figure 13.32 (2) Example of Complementary PWM Mode Operation (TPSC2 = TPSC1 = TPSC0 ≠ 0) (3) Rev. 3.00 Sep.
Section 13 Timer Z In complementary PWM mode, when the counter switches from up-counter to down-counter or vice versa, TCNT_0 and TCNT_1 overshoots or undershoots, respectively. In this case, the conditions to set the IMFA flag in channel 0 and the UDF flag in channel 1 differ from usual settings. Also, the transfer conditions in buffer operation differ from usual settings. Such timings are shown in figures 13.33 and 13.34.
Section 13 Timer Z When the counter is incremented or decremented, the IMFA flag of channel 0 is set to 1, and when the register is underflowed, the UDF flag of channel 0 is set to 1. After buffer operation has been designated for BR, BR is transferred to GR when the counter is incremented by compare match A0 or when TCNT_1 is underflowed. If the φ or φ/2 clock is selected by TPSC2 to TPSC0 bits, the OVF flag is not set to 1 at the timing that the counter value changes from H'FFFF to H'0000.
Section 13 Timer Z To change duty cycles while a waveform with a duty cycle of 0% or 100% is being output, make sure the following procedure. • To change duty cycles while a 0%-duty cycle waveform is being output, write to GR while H'0000 ≤ TCNT_1 < previous GR value • To change duty cycles while a 100%-duty cycle waveform is being output, write to GR while previous GR value< TCNT_0 ≤ GRA_0 Note that changing from a 0%-duty cycle waveform to a 100%-duty cycle waveform and vice versa is not possible. b.
Section 13 Timer Z 13.4.8 Buffer Operation Buffer operation differs depending on whether GR has been designated for an input capture register or an output compare register, or in reset synchronous PWM mode or complementary PWM mode. Table 13.8 shows the register combinations used in buffer operation. Table 13.8 Register Combinations in Buffer Operation General Register Buffer Register GRA GRC GRB GRD 1.
Section 13 Timer Z Input capture signal General register Buffer register TCNT Figure 13.36 Input Capture Buffer Operation 3. Complementary PWM Mode When the counter switches from counting up to counting down or vice versa, the value of the buffer register is transferred to the general register. Here, the value of the buffer register is transferred to the general register in the following timing: A. When TCNT_0 and GRA_0 are compared and their contents match B. When TCNT_1 underflows 4.
Section 13 Timer Z 6. Examples of Buffer Operation Figure 13.38 shows an operation example in which GRA has been designated as an output compare register, and buffer operation has been designated for GRA and GRC. This is an example of TCNT operating as a periodic counter cleared by compare match B. Pins FTIOA and FTIOB are set for toggle output by compare match A and B.
Section 13 Timer Z φ n TCNT n+1 Compare match signal Buffer transfer signal N GRC GRA n N Figure 13.39 Example of Compare Match Timing for Buffer Operation Rev. 3.00 Sep.
Section 13 Timer Z Figure 13.40 shows an operation example in which GRA has been designated as an input capture register, and buffer operation has been designated for GRA and GRC. Counter clearing by input capture B has been set for TCNT, and falling edges have been selected as the FIOCB pin input capture input edge. And both rising and falling edges have been selected as the FIOCA pin input capture input edge.
Section 13 Timer Z φ FTIO pin Input capture signal TCNT n n+1 N N+1 GRA M n n N GRC m M M n Figure 13.41 Input Capture Timing of Buffer Operation Rev. 3.00 Sep.
Section 13 Timer Z Figures 13.42 and 13.43 show the operation examples when buffer operation has been designated for GRB_0 and GRD_0 in complementary PWM mode. These are examples when a PWM waveform of 0% duty is created by using the buffer operation and performing GRD_0 ≥ GRA_0. Data is transferred from GRD_0 to GRB_0 according to the settings of CMD_0 and CMD_1 when TCNT_0 and GRA_0 are compared and their contents match or when TCNT_1 underflows.
Section 13 Timer Z GRB_0 (When restored, data will be transferred to the saved location regardless of the CMD1 and CMD0 values) TCNT values TCNT_0 GRA_0 TCNT_1 H'0999 H'0000 Time GRB_0 GRD_0 H'0999 GRB_0 H'0999 H'0000 H'0999 H'0000 H'0999 FTIOC0 FTIOD0 Figure 13.43 Buffer Operation (4) (Buffer Operation in Complementary PWM Mode CMD1 = CMD0 = 1) Rev. 3.00 Sep.
Section 13 Timer Z 13.4.9 Timer Z Output Timing The outputs of channels 0 and 1 can be disabled or inverted by the settings of TOER and TOCR and the external level. 1. Output Disable/Enable Timing of Timer Z by TOER: Setting the master enable bit in TOER to 1 disables the output of timer Z. By setting the PCR and PDR of the corresponding I/O port beforehand, any value can be output. Figure 13.44 shows the timing to enable or disable the output of timer Z by TOER.
Section 13 Timer Z 2. Output Disable Timing of Timer Z by External Trigger: When P54/WKP4 is set as a WKP4 input pin, and low level is input to WKP4, the master enable bit in TOER is set to 1 and the output of timer Z will be disabled. φ WKP4 TOER Timer Z output pin N H'FF I/O port Timer Z output Timer Z output I/O port Figure 13.45 Example of Output Disable Timing of Timer Z by External Trigger Rev. 3.00 Sep.
Section 13 Timer Z 3. Output Inverse Timing by TFCR: The output level can be inverted by inverting the OLS1 and OLS0 bits in TFCR in reset synchronous PWM mode or complementary PWM mode. Figure 13.46 shows the timing. T1 T2 φ Address bus TOER address TFCR Timer Z output pin Inverted Figure 13.46 Example of Output Inverse Timing of Timer Z by Writing to TFCR 4. Output Inverse Timing by POCR: The output level can be inverted by inverting the POLD, POLC, and POLB bits in POCR in PWM mode. Figure 13.
Section 13 Timer Z 13.5 Interrupts There are three kinds of timer Z interrupt sources; input capture/compare match, overflow, and underflow. An interrupt is requested when the corresponding interrupt request flag is set to 1 while the corresponding interrupt enable bit is set to 1. 13.5.1 Status Flag Set Timing 1. IMF Flag Set Timing: The IMF flag is set to 1 by the compare match signal that is generated when the GR matches with the TCNT.
Section 13 Timer Z 2. IMF Flag Set Timing at Input Capture: When an input capture signal is generated, the IMF flag is set to 1 and the value of TCNT is simultaneously transferred to corresponding GR. Figure 13.49 shows the timing. φ Input capture signal IMF TCNT N GR N ITMZ Figure 13.49 IMF Flag Set Timing at Input Capture 3. Overflow Flag (OVF) Set Timing: The overflow flag is set to 1 when the TCNT overflows. Figure 13.50 shows the timing.
Section 13 Timer Z 13.5.2 Status Flag Clearing Timing The status flag can be cleared by writing 0 after reading 1 from the CPU. Figure 13.51 shows the timing in this case. φ Address TSR address WTSR (internal write signal) IMF, OVF ITMZ Figure 13.51 Status Flag Clearing Timing Rev. 3.00 Sep.
Section 13 Timer Z 13.6 Usage Notes 1. Contention between TCNT Write and Clear Operations: If a counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing has priority and the TCNT write is not performed. Figure 13.52 shows the timing in this case. TCNT write cycle T1 T2 φ TCNT address WTCNT (internal write signal) Counter clear signal TCNT N H'0000 Clearing has priority. Figure 13.52 Contention between TCNT Write and Clear Operations 2.
Section 13 Timer Z TCNT write cycle T1 T2 φ TCNT address WTCNT (internal write signal) TCNT input clock M N TCNT TCNT write data Figure 13.53 Contention between TCNT Write and Increment Operations 3. Contention between GR Write and Compare Match: If a compare match occurs in the T2 state of a GR write cycle, GR write has priority and the compare match signal is disabled. Figure 13.54 shows the timing in this case.
Section 13 Timer Z 4. Contention between TCNT Write and Overflow/Underflow: If overflow/underflow occurs in the T2 state of a TCNT write cycle, TCNT write has priority without an increment operation. At this time, the OVF flag is set to 1. Figure 13.55 shows the timing in this case. TCNT write cycle T1 T2 φ TCNT address WTCNT (internal write signal) TCNT input clock Overflow signal TCNT H'FFFF M TCNT write data OVF Figure 13.55 Contention between TCNT Write and Overflow Rev. 3.00 Sep.
Section 13 Timer Z 5. Contention between GR Read and Input Capture: If an input capture signal is generated in the T1 state of a GR read cycle, the data that is read will be transferred before input capture transfer. Figure 13.56 shows the timing in this case. GR read cycle T1 T2 φ GR address Internal read signal Input capture signal GR Internal data bus X M X Figure 13.56 Contention between GR Read and Input Capture Rev. 3.00 Sep.
Section 13 Timer Z 6. Contention between Count Clearing and Increment Operations by Input Capture: If an input capture and increment signals are simultaneously generated, count clearing by the input capture operation has priority without an increment operation. The TCNT contents before clearing counter are transferred to GR. Figure 13.57 shows the timing in this case. φ Input capture signal Counter clear signal TCNT input clock TCNT N GR H'0000 N Clearing has priority. Figure 13.
Section 13 Timer Z 7. Contention between GR Write and Input Capture: If an input capture signal is generated in the T2 state of a GR write cycle, the input capture operation has priority and the write to GR is not performed. Figure 13.58 shows the timing in this case. GR write cycle T1 T2 φ Address bus GR address WGR (internal write signal) Input capture signal TCNT GR N M GR write data Figure 13.58 Contention between GR Write and Input Capture 8.
Section 13 Timer Z 9. Note on Writing to the TOA0 to TOD0 Bits and the TOA1 to TOD1 Bits in TOCR: The TOA0 to TOD0 bits and the TOA1 to TOD1 bits in TOCR decide the value of the FTIO pin, which is output until the first compare match occurs. Once a compare match occurs and this compare match changes the values of FTIOA0 to FTIOD0 and FTIOA1 to FTIOD1 output, the values of the FTIOA0 to FTIOD0 and FTIOA1 to FTIOD1 pin output and the values read from the TOA0 to TOD0 and TOA1 to TOD1 bits may differ.
Section 14 Watchdog Timer Section 14 Watchdog Timer The watchdog timer is an 8-bit timer that can generate an internal reset signal for this LSI if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. WDT dedicated internal oscillator φ CLK TCSRWD PSS TCWD Internal data bus The block diagram of the watchdog timer is shown in figure 14.1.
Section 14 Watchdog Timer 14.2 Register Descriptions The watchdog timer has the following registers. • Timer control/status register WD (TCSRWD) • Timer counter WD (TCWD) • Timer mode register WD (TMWD) 14.2.1 Timer Control/Status Register WD (TCSRWD) TCSRWD performs the TCSRWD and TCWD write control. TCSRWD also controls the watchdog timer operation and indicates the operating state. TCSRWD must be rewritten by using the MOV instruction.
Section 14 Watchdog Timer Bit Bit Name Initial Value R/W Description 2 WDON 1 R/W Watchdog Timer On TCWD starts counting up when the WDON bit is set to 1 and halts when the WDON bit is cleared to 0. The watchdog timer is enabled in the initial state. When the watchdog timer is not used, clear the WDON bit to 0.
Section 14 Watchdog Timer 14.2.2 Timer Counter WD (TCWD) TCWD is an 8-bit readable/writable up-counter. When TCWD overflows from H'FF to H'00, the internal reset signal is generated and the WRST bit in TCSRWD is set to 1. TCWD is initialized to H'00. 14.2.3 Timer Mode Register WD (TMWD) TMWD selects the input clock. Bit Bit Name Initial Value R/W Description 7 to 4 All 1 Reserved These bits are always read as 1.
Section 14 Watchdog Timer 14.3 Operation The watchdog timer is provided with an 8-bit counter. After the reset state is released, TCWD starts counting up. When the TCWD count value overflows H'FF, an internal reset signal is generated. The internal reset signal is output for a period of 256 φOSC clock cycles. As TCWD is a writable counter, it starts counting from the value set in TCWD. An overflow period in the range of 1 to 256 input clock cycles can therefore be set, according to the TCWD set value.
Section 14 Watchdog Timer Rev. 3.00 Sep.
Section 15 14-Bit PWM Section 15 14-Bit PWM The 14-bit PWM is a pulse division type PWM that can be used for electronic tuner control, etc. Figure 15.1 shows a block diagram of the 14-bit PWM. 15.1 Features • Choice of two conversion periods A conversion period of 32768/φ with a minimum modulation width of 2/φ, or a conversion period of 16384/φ with a minimum modulation width of 1/φ, can be selected.
Section 15 14-Bit PWM 15.2 Input/Output Pin Table 15.1 shows the 14-bit PWM pin configuration. Table 15.1 Pin Configuration Name Abbreviation I/O Function 14-bit PWM square-wave output PWM 14-bit PWM square-wave output pin Rev. 3.00 Sep.
Section 15 14-Bit PWM 15.3 Register Descriptions The 14-bit PWM has the following registers. • PWM control register (PWCR) • PWM data register U (PWDRU) • PWM data register L (PWDRL) 15.3.1 PWM Control Register (PWCR) PWCR selects the conversion period. Bit Bit Name Initial Value R/W Description 7 to 1 All 1 Reserved 0 PWCR0 0 R/W Clock Select These bits are always read as 1, and cannot be modified.
Section 15 14-Bit PWM 15.4 Operation When using the 14-bit PWM, set the registers in this sequence: 1. Set the PWM bit in the port mode register 1 (PMR1) to set the P11/PWM pin to function as a PWM output pin. 2. Set the PWCR0 bit in PWCR to select a conversion period of either. 3. Set the output waveform data in PWDRU and PWDRL. Be sure to write byte data first to PWDRL and then to PWDRU.
Section 16 Serial Communication Interface 3 (SCI3) Section 16 Serial Communication Interface 3 (SCI3) This LSI includes a serial communication interface 3 (SCI3), which has independent two channels. The SCI3 can handle both asynchronous and clock synchronous serial communication.
Section 16 Serial Communication Interface 3 (SCI3) Clock synchronous mode • Data length: 8 bits • Receive error detection: Overrun errors Table 16.
Section 16 Serial Communication Interface 3 (SCI3) SCK3 External clock Internal clock (φ/64, φ/16, φ/4, φ) Baud rate generator BRC BRR Clock Transmit/receive control circuit Internal data bus SMR SCR3 SSR TXD TSR TDR RXD RSR RDR Interrupt request (TEI, TXI, RXI, ERI) [Legend] Receive shift register RSR: Receive data register RDR: Transmit shift register TSR: Transmit data register TDR: Serial mode register SMR: SCR3: Serial control register 3 Serial status register SSR: Bit rate register BRR
Section 16 Serial Communication Interface 3 (SCI3) 16.2 Input/Output Pins Table 16.2 shows the SCI3 pin configuration. Table 16.2 Pin Configuration Pin Name Abbreviation I/O Function SCI3 clock SCK3 I/O SCI3 clock input/output SCI3 receive data input RXD Input SCI3 receive data input SCI3 transmit data output TXD Output SCI3 transmit data output Rev. 3.00 Sep.
Section 16 Serial Communication Interface 3 (SCI3) 16.3 Register Descriptions The SCI3 has the following registers for each channel. • Receive shift register (RSR) • Receive data register (RDR) • Transmit shift register (TSR) • Transmit data register (TDR) • Serial mode register (SMR) • Serial control register 3 (SCR3) • Serial status register (SSR) • Bit rate register (BRR) 16.3.
Section 16 Serial Communication Interface 3 (SCI3) 16.3.4 Transmit Data Register (TDR) TDR is an 8-bit register that stores data for transmission. When the SCI3 detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission. The doublebuffered structure of TDR and TSR enables continuous serial transmission.
Section 16 Serial Communication Interface 3 (SCI3) Bit Bit Name Initial Value R/W Description 3 STOP 0 R/W Stop Bit Length (enabled only in asynchronous mode) Selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits For reception, only the first stop bit is checked, regardless of the value in the bit. If the second stop bit is 0, it is treated as the start bit of the next transmit character.
Section 16 Serial Communication Interface 3 (SCI3) 16.3.6 Serial Control Register 3 (SCR3) SCR3 is a register that enables or disables SCI3 transfer operations and interrupt requests, and is also used to select the transfer clock source. For details on interrupt requests, refer to section 16.7, Interrupts. Bit Bit Name Initial Value R/W Description 7 TIE 0 R/W Transmit Interrupt Enable When this bit is set to 1, the TXI interrupt request is enabled.
Section 16 Serial Communication Interface 3 (SCI3) Bit Bit Name Initial Value R/W Description 1 CKE1 0 R/W Clock Enable 0 and 1 0 CKE0 0 R/W Selects the clock source. • Asynchronous mode 00: On-chip baud rate generator 01: On-chip baud rate generator Outputs a clock of the same frequency as the bit rate from the SCK3 pin. 10: External clock Inputs a clock with a frequency 16 times the bit rate from the SCK3 pin.
Section 16 Serial Communication Interface 3 (SCI3) 16.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI3 and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, OER, PER, and FER; they can only be cleared. Bit Bit Name Initial Value R/W Description 7 TDRE 1 R/W Transmit Data Register Empty Indicates whether TDR contains transmit data.
Section 16 Serial Communication Interface 3 (SCI3) Bit Bit Name Initial Value R/W Description 3 PER 0 R/W Parity Error [Setting condition] • When a parity error is detected during reception [Clearing condition] • 2 TEND 1 R When 0 is written to PER after reading PER = 1 Transmit End [Setting conditions] • When the TE bit in SCR3 is 0 • When TDRE = 1 at transmission of the last bit of a 1frame serial transmit character [Clearing conditions] 1 MPBR 0 R • When 0 is written to TDRE af
Section 16 Serial Communication Interface 3 (SCI3) 16.3.8 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. The initial value of BRR is H'FF. Table 16.3 shows the relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0 of SMR in asynchronous mode. Table 16.4 shows the maximum bit rate for each frequency in asynchronous mode. The values shown in both tables 16.3 and 16.4 are values in active (highspeed) mode. Table 16.
Section 16 Serial Communication Interface 3 (SCI3) Table 16.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) Operating Frequency φ (MHz) 2 2.097152 2.4576 3 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 1 141 0.03 1 148 –0.04 1 174 –0.26 1 212 0.03 150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16 300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16 600 0 103 0.16 0 108 0.21 0 127 0.
Section 16 Serial Communication Interface 3 (SCI3) Table 16.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) Operating Frequency φ (MHz) 6 6.144 7.3728 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) 110 2 106 –0.44 2 108 0.08 2 130 –0.07 150 2 77 0.16 2 79 0.00 2 95 0.00 300 1 155 0.16 1 159 0.00 1 191 0.00 600 1 77 0.16 1 79 0.00 1 95 0.00 1200 0 155 0.16 0 159 0.00 0 191 0.00 2400 0 77 0.16 0 79 0.
Section 16 Serial Communication Interface 3 (SCI3) Table 16.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (3) Operating Frequency φ (MHz) 12.288 14 14.7456 16 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 217 0.08 2 248 –0.17 3 64 0.70 3 70 0.03 150 2 159 0.00 2 181 0.16 2 191 0.00 2 207 0.16 300 2 79 0.00 2 90 0.16 2 95 0.00 2 103 0.16 600 1 159 0.00 1 181 0.16 1 191 0.00 1 207 0.
Section 16 Serial Communication Interface 3 (SCI3) Table 16.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) φ (MHz) Maximum Bit Rate (bit/s) n N φ (MHz) Maximum Bit Rate (bit/s) n N 2 62500 0 0 8 250000 0 0 2.097152 65536 0 0 9.8304 307200 0 0 2.4576 76800 0 0 10 312500 0 0 3 93750 0 0 12 375000 0 0 3.6864 115200 0 0 12.288 384000 0 0 4 125000 0 0 14 437500 0 0 4.9152 153600 0 0 14.
Section 16 Serial Communication Interface 3 (SCI3) Table 16.5 Examples of BRR Settings for Various Bit Rates (Clock Synchronous Mode) (1) Operating Frequency φ (MHz) 2 4 8 Bit Rate (bit/s) n N n N n N 110 3 70 — — — 250 2 124 2 249 3 500 1 249 2 124 1k 1 124 1 2.
Section 16 Serial Communication Interface 3 (SCI3) Table 16.5 Examples of BRR Settings for Various Bit Rates (Clock Synchronous Mode) (2) Operating Frequency φ (MHz) 18 20 Bit Rate (bit/s) n N n N 110 — — — — 250 — — — — 500 3 140 3 155 1k 3 69 3 77 2.5k 2 112 2 124 5k 1 224 1 249 10k 1 112 1 124 25k 0 179 0 199 50k 0 89 0 99 100k 0 44 0 49 250k 0 17 0 19 500k 0 8 0 9 1M 0 4 0 4 2M — — — — 2.
Section 16 Serial Communication Interface 3 (SCI3) 16.4 Operation in Asynchronous Mode Figure 16.2 shows the general format for asynchronous serial communication. One character (or frame) consists of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and finally stop bits (high level). Inside the SCI3, the transmitter and receiver are independent units, enabling full-duplex.
Section 16 Serial Communication Interface 3 (SCI3) 16.4.2 SCI3 Initialization Before transmitting and receiving data, you should first clear the TE and RE bits in SCR3 to 0, then initialize the SCI3 as described below. When the operating mode, or transfer format, is changed for example, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1.
Section 16 Serial Communication Interface 3 (SCI3) 16.4.3 Data Transmission Figure 16.5 shows an example of operation for transmission in asynchronous mode. In transmission, the SCI3 operates as described below. 1. The SCI3 monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI3 recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI3 sets the TDRE flag to 1 and starts transmission.
Section 16 Serial Communication Interface 3 (SCI3) Start transmission [1] Read TDRE flag in SSR No TDRE = 1 Yes Write transmit data to TDR Yes [2] All data transmitted? [1] Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automaticaly cleared to 0. [2] To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR.
Section 16 Serial Communication Interface 3 (SCI3) 16.4.4 Serial Data Reception Figure 16.7 shows an example of operation for reception in asynchronous mode. In serial reception, the SCI3 operates as described below. 1. The SCI3 monitors the communication line. If a start bit is detected, the SCI3 performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit. 2.
Section 16 Serial Communication Interface 3 (SCI3) Table 16.6 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 16.8 shows a sample flow chart for serial data reception. Table 16.
Section 16 Serial Communication Interface 3 (SCI3) Start reception Read OER, PER, and FER flags in SSR [1] Yes OER+PER+FER = 1 [4] No Error processing (Continued on next page) Read RDRF flag in SSR [2] No RDRF = 1 Yes Read receive data in RDR [1] Read the OER, PER, and FER flags in SSR to identify the error. If a receive error occurs, performs the appropriate error processing. [2] Read SSR and check that RDRF = 1, then read the receive data in RDR. The RDRF flag is cleared automatically.
Section 16 Serial Communication Interface 3 (SCI3) [4] Error processing No OER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No Framing error processing No PER = 1 Yes Parity error processing (A) Clear OER, PER, and FER flags in SSR to 0 Figure 16.8 Sample Serial Reception Data Flowchart (Asynchronous Mode) (2) Rev. 3.00 Sep.
Section 16 Serial Communication Interface 3 (SCI3) 16.5 Operation in Clock Synchronous Mode Figure 16.9 shows the general format for clock synchronous communication. In clock synchronous mode, data is transmitted or received synchronous with clock pulses. A single character in the transmit data consists of the 8-bit data starting from the LSB. In clock synchronous serial communication, data on the transmission line is output from one falling edge of the synchronization clock to the next.
Section 16 Serial Communication Interface 3 (SCI3) 16.5.3 Serial Data Transmission Figure 16.10 shows an example of SCI3 operation for transmission in clock synchronous mode. In serial transmission, the SCI3 operates as described below. 1. The SCI3 monitors the TDRE flag in SSR, and if the flag is 0, the SCI3 recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. The SCI3 sets the TDRE flag to 1 and starts transmission.
Section 16 Serial Communication Interface 3 (SCI3) Start transmission [1] [1] Read TDRE flag in SSR No TDRE = 1 Yes [2] Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0 and clocks are output to start the data transmission. To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR.
Section 16 Serial Communication Interface 3 (SCI3) 16.5.4 Serial Data Reception (Clock Synchronous Mode) Figure 16.12 shows an example of SCI3 operation for reception in clock synchronous mode. In serial reception, the SCI3 operates as described below. 1. The SCI3 performs internal initialization synchronous with a synchronization clock input or output, starts receiving data. 2. The SCI3 stores the receive data in RSR. 3.
Section 16 Serial Communication Interface 3 (SCI3) Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 16.13 shows a sample flow chart for serial data reception. Start reception [1] [1] Read OER flag in SSR [2] Yes OER = 1 [4] No Error processing [3] (Continued below) Read RDRF flag in SSR [2] [4] No RDRF = 1 Yes Read the OER flag in SSR to determine if there is an error.
Section 16 Serial Communication Interface 3 (SCI3) 16.5.5 Simultaneous Serial Data Transmission and Reception Figure 16.14 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations. To switch from transmit mode to simultaneous transmit and receive mode, after checking that the SCI3 has finished transmission and the TDRE and TEND flags are set to 1, clear TE to 0.
Section 16 Serial Communication Interface 3 (SCI3) Start transmission/reception Read TDRE flag in SSR [1] [1] No TDRE = 1 Yes Write transmit data to TDR Read OER flag in SSR OER = 1 No Read RDRF flag in SSR Yes [4] Error processing [2] No RDRF = 1 Yes Read receive data in RDR Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0.
Section 16 Serial Communication Interface 3 (SCI3) 16.6 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer between a number of processors sharing communication lines by asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is performed, each receiving station is addressed by a unique ID code.
Section 16 Serial Communication Interface 3 (SCI3) Transmitting station Serial transmission line Receiving station A Receiving station B Receiving station C Receiving station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial data H'01 H'AA (MPB = 1) (MPB = 0) ID transmission cycle = Data transmission cycle = receiving station Data transmission to specification receiving station specified by ID Legend MPB: Multiprocessor bit Figure 16.
Section 16 Serial Communication Interface 3 (SCI3) Start transmission [1] [1] Read TDRE flag in SSR No TDRE = 1 [2] Yes Set MPBT bit in SSR [3] Write transmit data to TDR Yes [2] Read SSR and check that the TDRE flag is set to 1, set the MPBT bit in SSR to 0 or 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0. To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR.
Section 16 Serial Communication Interface 3 (SCI3) 16.6.2 Multiprocessor Serial Data Reception Figure 16.17 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR3 is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI3 operations are the same as those in asynchronous mode. Figure 16.
Section 16 Serial Communication Interface 3 (SCI3) [1] [2] Start reception Set MPIE bit in SCR3 to 1 [1] Read OER and FER flags in SSR [2] [3] Yes FER+OER = 1 No Read RDRF flag in SSR [3] No [4] [5] RDRF = 1 Yes Read receive data in RDR No This station’s ID? Set the MPIE bit in SCR3 to 1. Read OER and FER in SSR to check for errors. Receive error processing is performed in cases where a receive error occurs.
Section 16 Serial Communication Interface 3 (SCI3) [5] Error processing No OER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No [A] Framing error processing Clear OER, and FER flags in SSR to 0 Figure 16.17 Sample Multiprocessor Serial Reception Flowchart (2) Rev. 3.00 Sep.
Section 16 Serial Communication Interface 3 (SCI3) Start bit Serial data 1 0 Receive data (ID1) D0 D1 D7 MPB 1 Stop Start bit bit 1 0 Receive data (Data1) D0 1 frame D1 D7 MPB Stop bit Mark state (idle state) 0 1 1 1 frame MPIE RDRF RDR value ID1 LSI operation User processing RXI interrupt request is not generated, and RDR retains its state RDRF flag cleared to 0 RXI interrupt request MPIE cleared to 0 RDR data read When data is not this station's ID, MPIE is set to 1 again (a)
Section 16 Serial Communication Interface 3 (SCI3) 16.7 Interrupts SCI3 creates the following six interrupt requests: transmission end, transmit data empty, receive data full, and receive errors (overrun error, framing error, and parity error). Table 16.7 shows the interrupt sources. Table 16.
Section 16 Serial Communication Interface 3 (SCI3) 16.8 Usage Notes 16.8.1 Break Detection and Processing When framing error detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, setting the FER flag, and possibly the PER flag. Note that as the SCI3 continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. 16.8.
Section 16 Serial Communication Interface 3 (SCI3) 16.8.4 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI3 operates on a basic clock with a frequency of 16 times the transfer rate. In reception, the SCI3 samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the basic clock as shown in figure 16.19.
Section 16 Serial Communication Interface 3 (SCI3) Rev. 3.00 Sep.
Section 17 I2C Bus Interface 2 (IIC2) 2 Section 17 I C Bus Interface 2 (IIC2) 2 2 The I C bus interface 2 conforms to and provides a subset of the Philips I C bus (inter-IC bus) 2 interface functions. The register configuration that controls the I C bus differs partly from the Philips configuration, however. 2 Figure 17.1 shows a block diagram of the I C bus interface 2. Figure 17.2 shows an example of I/O pin connections to external circuits. 17.
Section 17 I2C Bus Interface 2 (IIC2) Transfer clock generation circuit SCL Transmission/ reception control circuit Output control ICCR1 ICCR2 ICMR Internal data bus Noise canceler ICDRT SDA Output control SAR ICDRS Address comparator Noise canceler ICDRR Bus state decision circuit Arbitration decision circuit ICSR ICIER Interrupt generator [Legend] ICCR1: ICCR2: ICMR: ICSR: ICIER: ICDRT: ICDRR: ICDRS: SAR: 2 I C bus control register 1 I2C bus control register 2 I2C bus mode register I2C b
Section 17 I2C Bus Interface 2 (IIC2) Vcc SCL in Vcc SCL SCL SDA SDA SCL out SDA in SCL in SCL out SCL SDA (Master) SCL SDA SDA out SCL in SCL out SDA in SDA in SDA out SDA out (Slave 1) (Slave 2) Figure 17.2 External Circuit Connections of I/O Pins 17.2 Input/Output Pins 2 Table 17.1 summarizes the input/output pins used by the I C bus interface 2. 2 Table 17.
Section 17 I2C Bus Interface 2 (IIC2) 17.3 Register Descriptions 2 The I C bus interface 2 has the following registers: • I C bus control register 1 (ICCR1) 2 • I C bus control register 2 (ICCR2) 2 • I C bus mode register (ICMR) 2 • I C bus interrupt enable register (ICIER) 2 • I C bus status register (ICSR) 2 • I C bus slave address register (SAR) 2 • I C bus transmit data register (ICDRT) 2 • I C bus receive data register (ICDRR) 2 • I C bus shift register (ICDRS) 2 17.3.
Section 17 I2C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 5 MST 0 R/W Master/Slave Select 4 TRS 0 R/W Transmit/Receive Select 2 In master mode with the I C bus format, when arbitration is lost, MST and TRS are both reset by hardware, causing a transition to slave receive mode. Modification of the TRS bit should be made between transfer frames.
Section 17 I2C Bus Interface 2 (IIC2) Table 17.2 Transfer Rate Bit 3 Bit 2 Bit 1 Bit 0 Transfer Rate CKS3 CKS2 CKS1 CKS0 Clock 0 0 1 0 1 φ = 8 MHz φ = 10 MHz φ = 16 MHz φ = 20 MHz 0 φ/28 179 kHz 286 kHz 357 kHz 571 kHz 714 kHz 1 φ/40 125 kHz 200 kHz 250 kHz 400 kHz 500 kHz 0 φ/48 104 kHz 167 kHz 208 kHz 333 kHz 417 kHz 1 φ/64 78.1 kHz 125 kHz 156 kHz 250 kHz 313 kHz 0 0 φ/80 62.5 kHz 100 kHz 125 kHz 200 kHz 250 kHz 1 φ/100 50.0 kHz 80.
Section 17 I2C Bus Interface 2 (IIC2) 17.3.2 2 I C Bus Control Register 2 (ICCR2) ICCR1 issues start/stop conditions, manipulates the SDA pin, monitors the SCL pin, and controls 2 reset in the control part of the I C bus interface 2. Bit Bit Name Initial Value R/W Description 7 BBSY 0 R/W Bus Busy 2 This bit enables to confirm whether the I C bus is occupied or released and to issue start/stop conditions in master mode. With the clock synchronous serial format, 2 this bit has no meaning.
Section 17 I2C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 4 SDAOP 1 R/W SDAO Write Protect This bit controls change of output level of the SDA pin by modifying the SDAO bit. To change the output level, clear SDAO and SDAOP to 0 or set SDAO to 1 and clear SDAOP to 0 by the MOV instruction. This bit is always read as 1. 3 SCLO 1 R This bit monitors SCL output level. When SCLO is 1, SCL pin outputs high. When SCLO is 0, SCL pin outputs low.
Section 17 I2C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 6 WAIT 0 R/W Wait Insertion Bit 2 In master mode with the I C bus format, this bit selects whether to insert a wait after data transfer except the acknowledge bit. When WAIT is set to 1, after the fall of the clock for the final data bit, low period is extended for two transfer clocks. If WAIT is cleared to 0, data and acknowledge bits are transferred consecutively with no wait inserted.
Section 17 I2C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 2 BC2 0 R/W Bit Counter 2 to 0 1 BC1 0 R/W 0 BC0 0 R/W These bits specify the number of bits to be transferred next. When read, the remaining number of transfer bits is 2 indicated. With the I C bus format, the data is transferred with one addition acknowledge bit. Bit BC2 to BC0 settings should be made during an interval between transfer frames.
Section 17 I2C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 6 TEIE 0 R/W Transmit End Interrupt Enable This bit enables or disables the transmit end interrupt (TEI) at the rising of the ninth clock while the TDRE bit in ICSR is 1. TEI can be canceled by clearing the TEND bit or the TEIE bit to 0. 0: Transmit end interrupt request (TEI) is disabled. 1: Transmit end interrupt request (TEI) is enabled.
Section 17 I2C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 2 ACKE 0 R/W Acknowledge Bit Judgment Select 0: The value of the receive acknowledge bit is ignored, and continuous transfer is performed. 1: If the receive acknowledge bit is 1, continuous transfer is halted. 1 ACKBR 0 R Receive Acknowledge In transmit mode, this bit stores the acknowledge data that are returned by the receive device. This bit cannot be modified.
Section 17 I2C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 6 TEND 0 R/W Transmit End [Setting conditions] • When the ninth clock of SCL rises with the I C bus format while the TDRE flag is 1 • When the final bit of transmit frame is sent with the clock synchronous serial format 2 [Clearing conditions] 5 RDRF 0 R/W • When 0 is written in TEND after reading TEND = 1 • When data is written to ICDRT with an instruction Receive Data Register Full [Setting condition]
Section 17 I2C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 3 STOP 0 R/W Stop Condition Detection Flag [Setting conditions] • In master mode, when a stop condition is detected after frame transfer • In slave mode, when a stop condition is detected after the following events: A general call is invoked A start condition is detected The first byte in the slave address matches the address set in the SAR [Clearing condition] • 2 AL/OVE 0 R/W When 0 is written in STOP
Section 17 I2C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 1 AAS 0 R/W Slave Address Recognition Flag In slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR. [Setting conditions] • When the slave address is detected in slave receive mode • When the general call address is detected in slave receive mode.
Section 17 I2C Bus Interface 2 (IIC2) 17.3.7 2 I C Bus Transmit Data Register (ICDRT) ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT to ICDRS and starts transferring data. If the next transfer data is written to ICDRT during transferring data of ICDRS, continuous transfer is possible.
Section 17 I2C Bus Interface 2 (IIC2) 17.4 Operation 2 2 The I C bus interface can communicate either in I C bus mode or clock synchronous serial mode by setting FS in SAR. 17.4.1 2 I C Bus Format 2 2 Figure 17.3 shows the I C bus formats. Figure 17.4 shows the I C bus timing. The first frame following a start condition always consists of 8 bits.
Section 17 I2C Bus Interface 2 (IIC2) [Legend] S: Start condition. The master device drives SDA from high to low while SCL is high. SLA: Slave address R/W: Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0. A: Acknowledge. The receive device drives SDA to low. DATA: Transfer data P: Stop condition. The master device drives SDA from low to high while SCL is high. 17.4.
Section 17 I2C Bus Interface 2 (IIC2) SCL (Master output) 1 2 3 4 5 6 SDA (Master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 7 8 Bit 1 Slave address 9 1 Bit 0 Bit 7 2 Bit 6 R/W SDA (Slave output) A TDRE TEND Address + R/W ICDRT ICDRS User processing Data 1 Address + R/W [2] Instruction of start condition issuance Data 2 Data 1 [4] Write data to ICDRT (second byte) [5] Write data to ICDRT (third byte) [3] Write data to ICDRT (first byte) Figure 17.
Section 17 I2C Bus Interface 2 (IIC2) 17.4.3 Master Receive Operation In master receive mode, the master device outputs the receive clock, receives data from the slave device, and returns an acknowledge signal. For master receive mode operation timing, refer to figures 17.7 and 17.8. The reception procedure and operations in master receive mode are shown below. 1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCR1 to 0 to switch from master transmit mode to master receive mode.
Section 17 I2C Bus Interface 2 (IIC2) Master transmit mode SCL (Master output) Master receive mode 9 1 2 3 4 5 6 7 8 9 SDA (Master output) SDA (Slave output) 1 A A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 TDRE TEND TRS RDRF ICDRS Data 1 ICDRR User processing Data 1 [3] Read ICDRR [1] Clear TDRE after clearing TEND and TRS [2] Read ICDRR (dummy read) Figure 17.7 Master Receive Mode Operation Timing (1) Rev. 3.00 Sep.
Section 17 I2C Bus Interface 2 (IIC2) SCL (Master output) 9 SDA (Master output) A SDA (Slave output) 1 2 3 4 5 6 7 8 9 A/A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RDRF RCVD ICDRS Data n Data n-1 ICDRR Data n Data n-1 User processing [5] Read ICDRR after setting RCVD [7] Read ICDRR, and clear RCVD [6] Issue stop condition [8] Set slave receive mode Figure 17.8 Master Receive Mode Operation Timing (2) 17.4.
Section 17 I2C Bus Interface 2 (IIC2) Slave receive mode SCL (Master output) Slave transmit mode 9 1 2 3 4 5 6 7 8 9 SDA (Master output) 1 A SCL (Slave output) SDA (Slave output) A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 TDRE TEND TRS ICDRT ICDRS Data 1 Data 2 Data 1 Data 3 Data 2 ICDRR User processing [2] Write data to ICDRT (data 1) [2] Write data to ICDRT (data 2) [2] Write data to ICDRT (data 3) Figure 17.
Section 17 I2C Bus Interface 2 (IIC2) Slave receive mode Slave transmit mode SCL (Master output) 9 SDA (Master output) A 1 2 3 4 5 6 7 8 9 A SCL (Slave output) SDA (Slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TDRE TEND TRS ICDRT ICDRS Data n ICDRR User processing [3] Clear TEND [4] Read ICDRR (dummy read) after clearing TRS [5] Clear TDRE Figure 17.10 Slave Transmit Mode Operation Timing (2) 17.4.
Section 17 I2C Bus Interface 2 (IIC2) 3. Read ICDRR every time RDRF is set. If 8th receive clock pulse falls while RDRF is 1, SCL is fixed low until ICDRR is read. The change of the acknowledge before reading ICDRR, to be returned to the master device, is reflected to the next transmit frame. 4. The last byte data is read by reading ICDRR.
Section 17 I2C Bus Interface 2 (IIC2) 17.4.6 Clock Synchronous Serial Format This module can be operated with the clock synchronous serial format, by setting the FS bit in SAR to 1. When the MST bit in ICCR1 is 1, the transfer clock output from SCL is selected. When MST is 0, the external clock input is selected. Data Transfer Format Figure 17.13 shows the clock synchronous serial transfer format.
Section 17 I2C Bus Interface 2 (IIC2) Transmit Operation In transmit mode, transmit data is output from SDA, in synchronization with the fall of the transfer clock. The transfer clock is output when MST in ICCR1 is 1, and is input when MST is 0. For transmit mode operation timing, refer to figure 17.14. The transmission procedure and operations in transmit mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) 2.
Section 17 I2C Bus Interface 2 (IIC2) Receive Operation In receive mode, data is latched at the rise of the transfer clock. The transfer clock is output when MST in ICCR1 is 1, and is input when MST is 0. For receive mode operation timing, refer to figure 17.15. The reception procedure and operations in receive mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) 2.
Section 17 I2C Bus Interface 2 (IIC2) 17.4.7 Noise Filter The signal levels on the SCL and SDA pins are internally latched via the noise filter. Figure 17.16 shows a block diagram of the noise filter circuit. The noise filter consists of two cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the system clock. When both outputs of the latches match, its level is output to other blocks by the match detector. If they do not match, the previous value is held.
Section 17 I2C Bus Interface 2 (IIC2) Start Initialize [1] Test the status of the SCL and SDA lines. [2] Set master transmit mode. [3] Issue the start candition. [2] [4] Set the first byte (slave address + R/W) of transmit data. Write 1 to BBSY and 0 to SCP. [3] [5] Wait for 1 byte to be transmitted. Write transmit data in ICDRT [4] [6] Test the acknowledge transferred from the specified slave device. [7] Set the second and subsequent bytes (except for the final byte) of transmit data.
Section 17 I2C Bus Interface 2 (IIC2) Mater receive mode [1] Clear TEND, select master receive mode, and then clear TDRE.* [2] Set acknowledge to the transmit device.* [3] Dummy-read ICDDR.* [4] Wait for 1 byte to be received [5] Check whether it is the (last receive - 1). [6] Read the receive data last. [7] Set acknowledge of the final byte. Disable continuous reception (RCVD = 1). [8] Read the (final byte - 1) of receive data. [9] Wait for the last byte to be receive.
Section 17 I2C Bus Interface 2 (IIC2) [1] Clear the AAS flag. Slave transmit mode Clear AAS in ICSR [1] Write transmit data in ICDRT [2] [3] Wait for ICDRT empty. [4] Set the last byte of transmit data. Read TDRE in ICSR [5] Wait for the last byte to be transmitted. [3] No TDRE=1 ? Yes Yes [6] Clear the TEND flag . [7] Set slave receive mode. Last byte? No [2] Set transmit data for ICDRT (except for the last data). [8] Dummy-read ICDRR to release the SCL line. [4] [9] Clear the TDRE flag.
Section 17 I2C Bus Interface 2 (IIC2) Slave receive mode [1] Clear the AAS flag. Clear AAS in ICSR [1] Clear ACKBT in ICIER to 0 [2] Dummy-read ICDRR [3] [2] Set acknowledge to the transmit device. [3] Dummy-read ICDRR. [5] Check whether it is the (last receive - 1). Read RDRF in ICSR No [4] RDRF=1 ? [6] Read the receive data. [7] Set acknowledge of the last byte. Yes Last receive - 1? [4] Wait for 1 byte to be received. Yes No Read ICDRR [5] [8] Read the (last byte - 1) of receive data.
Section 17 I2C Bus Interface 2 (IIC2) 17.5 Interrupt Request There are six interrupt requests in this module; transmit data empty, transmit end, receive data full, NACK receive, STOP recognition, and arbitration lost/overrun error. Table 17.3 shows the contents of each interrupt request. Table 17.
Section 17 I2C Bus Interface 2 (IIC2) 17.6 Bit Synchronous Circuit In master mode, this module has a possibility that high level period may be short in the two states described below. • When SCL is driven to low by the slave device • When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pullup resistance) Therefore, it monitors SCL and communicates by bit with synchronization. Figure 17.21 shows the timing of the bit synchronous circuit and table 17.
Section 17 I2C Bus Interface 2 (IIC2) 17.7 Usage Notes 17.7.1 Issue (Retransmission) of Start/Stop Conditions In master mode, when the start/stop conditions are issued (retransmitted) at the specific timing under the following condition 1 or 2, such conditions may not be output successfully. To avoid this, issue (retransmit) the start/stop conditions after the fall of the ninth clock is confirmed. Check 2 the SCLO bit in the I C control register 2 (IICR2) to confirm the fall of the ninth clock. 1.
Section 17 I2C Bus Interface 2 (IIC2) 17.7.3 (1) Restriction in Use of Multi-Master Restriction on Setting Transfer Rate 2 In multi-master usage when I C transfer rate setting of this LSI is lower than those of the other masters, unexpected length of SCL may occasionally be output. To avoid this, the specified value must be greater than or equal to the value produced by multiplying the fastest transfer rate among the other masters by 1/1.8.
Section 17 I2C Bus Interface 2 (IIC2) Rev. 3.00 Sep.
Section 18 A/D Converter Section 18 A/D Converter This LSI includes a successive approximation type 10-bit A/D converter that allows up to eight analog input channels to be selected. The block diagram of the A/D converter is shown in figure 18.1. 18.1 Features • 10-bit resolution • Eight input channels • Conversion time: at least 3.
Section 18 A/D Converter Module data bus AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Analog multiplexer 10-bit D/A Bus interface Successive approximations register AVCC Internal data bus A D D R A A D D R B A D D R C A D D R D A D C S R A D C R + Control circuit Comparator Sample-andhold circuit ADTRG [Legend] ADCR: ADCSR: ADDRA: ADDRB: ADDRC: ADDRD: A/D control register A/D control/status register A/D data register A A/D data register B A/D data register C A/D data register D Figure 18.
Section 18 A/D Converter 18.2 Input/Output Pins Table 18.1 summarizes the input pins used by the A/D converter. The 8 analog input pins are divided into two groups; analog input pins 0 to 3 (AN0 to AN3) comprising group 0, analog input pins 4 to 7 (AN4 to AN7) comprising group 1. The AVcc pin is the power supply pin for the analog block in the A/D converter. Table 18.
Section 18 A/D Converter 18.3 Register Descriptions The A/D converter has the following registers. • A/D data register A (ADDRA) • A/D data register B (ADDRB) • A/D data register C (ADDRC) • A/D data register D (ADDRD) • A/D control/status register (ADCSR) • A/D control register (ADCR) 18.3.1 A/D Data Registers A to D (ADDRA to ADDRD) There are four 16-bit read-only ADDR registers; ADDRA to ADDRD, used to store the results of A/D conversion.
Section 18 A/D Converter 18.3.2 A/D Control/Status Register (ADCSR) ADCSR consists of the control bits and conversion end status bits of the A/D converter.
Section 18 A/D Converter Bit Bit Name Initial Value R/W Description 2 CH2 0 R/W Channel Select 2 to 0 1 CH1 0 R/W Select analog input channels. 0 CH0 0 R/W When SCAN = 0 When SCAN = 1 000: AN0 000: AN0 001: AN1 001: AN0 and AN1 010: AN2 010: AN0 to AN2 011: AN3 011: AN0 to AN3 100: AN4 100: AN4 101: AN5 101: AN4 and AN5 110: AN6 110: AN4 to AN6 111: AN7 111: AN4 to AN7 18.3.
Section 18 A/D Converter 18.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes; single mode and scan mode. When changing the operating mode or analog input channel, in order to prevent incorrect operation, first clear the bit ADST in ADCSR to 0. The ADST bit can be set at the same time as the operating mode or analog input channel is changed. 18.4.
Section 18 A/D Converter 18.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (tD) has passed after the ADST bit is set to 1, then starts conversion. Figure 18.2 shows the A/D conversion timing. Table 18.3 shows the A/D conversion time. As indicated in figure 18.2, the A/D conversion time includes tD and the input sampling time.
Section 18 A/D Converter Table 18.3 A/D Conversion Time (Single Mode) CKS = 0 Item Symbol Min. Typ. CKS = 1 Max. Min. Typ. Max. A/D conversion start delay time tD 6 — 9 4 — 5 Input sampling time tSPL — 31 — — 15 — A/D conversion time tCONV 131 — 134 69 — 70 Note: All values represent the number of states. 18.4.4 External Trigger Input Timing A/D conversion can also be started by an external trigger input.
Section 18 A/D Converter 18.5 A/D Conversion Accuracy Definitions This LSI's A/D conversion accuracy definitions are given below. • Resolution The number of A/D converter digital output codes • Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 18.4). • Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value 0000000000 to 0000000001 (see figure 18.5).
Section 18 A/D Converter Digital output Ideal A/D conversion characteristic 111 110 101 100 011 010 Quantization error 001 000 1 8 2 8 3 8 4 8 5 8 6 8 7 FS 8 Analog input voltage Figure 18.4 A/D Conversion Accuracy Definitions (1) Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic Offset error FS Analog input voltage Figure 18.5 A/D Conversion Accuracy Definitions (2) Rev. 3.00 Sep.
Section 18 A/D Converter 18.6 Usage Notes 18.6.1 Permissible Signal Source Impedance This LSI's analog input is designed such that conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 kΩ or less.
Section 19 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits Section 19 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits This LSI can include a band-gap circuit (BGR, band-gap regulator), a power-on reset circuit and low-voltage detection circuit. BGR supplies a reference voltage to the on-chip oscillator and low-voltage detection circuit. Figure 19.1 shows the block diagram of how BGR is allocated.
Section 19 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits 19.1 Features • BGR circuit Supplies stable reference voltage covering the entire operating voltage range and the operating temperature range. • Power-on reset circuit Uses an external capacitor to generate an internal reset signal when power is first supplied. • Low-voltage detection circuit LVDR: Monitors the power-supply voltage, and generates an internal reset signal when the voltage falls below a given value.
Section 19 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits φ 150 kΩ OVF CK PSS R R RES Noise filter circuit CRES Internal reset signal Q S Power-on reset circuit Noise filter circuit External power supply Vcc Vreset VintU VintD ExtD LVDRES LVDINT Interrupt control circuit LVDSR Internal data bus LVDCR Ladder network ExtU VDDII Interrupt request VBGR [Legend] PSS: LVDCR: LVDSR: VBGR: ExtD: ExtU: VDDII: Prescaler S Low-voltage-detection control register Low-voltage-de
Section 19 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits 19.2 Register Descriptions The low-voltage detection circuit has the following registers. • Low-voltage-detection control register (LVDCR) • Low-voltage-detection status register (LVDSR) • Reset source decision register (LVDRF) 19.2.
Section 19 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits Bit Bit Name Initial Value R/W Description 1 LVDDE 0 R/W Voltage-Fall-Interrupt Enable 0: Interrupt on the power-supply voltage falling disabled 1: Interrupt on the power-supply voltage falling enabled 0 LVDUE 0 R/W Voltage-Rise-Interrupt Enable 0: Interrupt on the power-supply voltage rising disabled 1: Interrupt on the power-supply voltage rising enabled Notes: 1.
Section 19 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits 19.2.2 Low-Voltage-Detection Status Register (LVDSR) LVDSR indicates whether the power-supply voltage falls below or rises above the respective given values. Bit Bit Name Initial Value R/W Description 7 to 2 All 1 Reserved 1 LVDDF 0* R/W These bits are always read as 1 and cannot be modified. LVD Power-Supply Voltage Fall Flag [Setting condition] • When the power-supply voltage falls below Vint (D) (Typ.
Section 19 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits 19.2.3 Reset Source Decision Register (LVDRF) LVDSR indicates sources of resets. Bit Bit Name Initial Value R/W 7 to 2 Description Reserved The read value is undefined and these bits cannot be modified.
Section 19 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits 19.3 Operations 19.3.1 Power-On Reset Circuit Figure 19.3 shows the timing of the operation of the power-on reset circuit. As the power-supply voltage rises, the capacitor which is externally connected to the RES pin is gradually charged via the internal pull-up resistor (Typ. 150 kΩ). While the RES signal is driven low, the prescaler S and the entire chip retains the reset state.
Section 19 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits tPWON Vcc Vpor Vss RES Vss PSS-reset signal OVF Internal reset signal 131,072 cycles PSS counter starts Reset released Figure 19.3 Operational Timing of Power-On Reset Circuit 19.3.2 Low-Voltage Detection Circuit LVDR (Reset by Low Voltage Detection) Circuit: Figure 19.4 shows the timing of the operation of the LVDR circuit. The LVDR circuit is kept enabled during the LSI's operation.
Section 19 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits VCC Vreset VLVDRmin VSS LVDRES PSS-reset signal OVF Internal reset signal 131,072 cycles PSS counter starts Reset released Figure 19.4 Operating Timing of LVDR Circuit Rev. 3.00 Sep.
Section 19 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits Low Voltage Detection Interrupt (LVDI) Circuit (When Internally Generated Voltage is used for Detection): Figure 19.5 shows the timing of the operation of the LVDI circuit. The LVDI circuit is enabled after a power-on reset, however, the interrupt request is disabled. To enable the LVDI, the LVDDF bit and LVDUF bit in LVDSR must be cleared to 0 and then the LVDDE bit or LVDUE bit in LVDCR must be set to 1.
Section 19 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits Low Voltage Detection Interrupt (LVDI) Circuit (When Voltages Input via ExtU and ExtD Pins are used for Detection): Figure 19.6 shows the timing of the LVDI circuit. The LVDI circuit is enabled after a power-on reset, however, the interrupt request is disabled. To enable the LVDI, the LVDDF and LVDUF bits in LVDSR must be cleared to 0 and the LVDDE or LVDUE bit in LVDCR must be set to 1.
Section 19 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits External power supply voltage ExtD input voltage ExtU input voltage (1) (2) Vexd (3) (4) Vreset1 VSS LVDINT LVDDE LVDDF LVDUE LVDUF IRQ0 interrupt generated IRQ0 interrupt generated Figure 19.6 Operational Timing of LVDI Circuit (When Compared Voltage is Input through ExtU and ExtD Pins) Rev. 3.00 Sep.
Section 19 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits 19.3.3 Deciding Reset Source The source of a reset can be decided by reading the reset source decision register (LVDRF) in the reset exception handler (see table 19.2). After that, writing 0 to the bit can clear the flag and can be ready to decide the next reset source. Figure 19.7 shows a timing of setting the bits in the register. Table 19.
Section 20 Power Supply Circuit Section 20 Power Supply Circuit This LSI incorporates an internal power supply step-down circuit. Use of this circuit enables the internal power supply to be fixed at a constant level of approximately 3.0 V, independently of the voltage of the power supply connected to the external V pin. As a result, the current consumed when an external power supply is used at 3.0 V or above can be held down to virtually the same low level as when used at approximately 3.0 V. CC 20.
Section 20 Power Supply Circuit 20.2 Power Supply Connection of 3.3-V-Specification Microcontrollers Connect the external power supply to the V and V pins as shown in figure 20.2. The power supply voltage must be within a range of 3.0 to 3.6 V. Otherwise, correct operation is not guaranteed. CL SS VCC Step-down circuit Internal logic VCC = 3.0 to 3.6 V VCL Internal power supply VSS Figure 20.2 Power Supply Connection of 3.3-V-Specification Microcontrollers Rev. 3.00 Sep.
Section 21 List of Registers Section 21 List of Registers The register list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. Register addresses (address order) • The register addresses listed in the table are the address values (16 bits) in the 64-Kbyte address space.
Section 21 List of Registers 21.1 Register Addresses (Address Order) The data-bus width column indicates the number of bits. The access-state column shows the number of states of the selected basic clock that is required for access to the register. Note: Access to undefined or reserved addresses should not take place. Correct operation of the access itself or later operations is not guaranteed when such a register is accessed.
Section 21 List of Registers Address Module Name Data Bus Width Access State 16 H'F71C Timer Z 16 2 16 H'F71E Timer Z 16 2 Register Abbreviation Bit No General register C_1 GRC_1 General register D_1 GRD_1 Timer start register TSTR 8 H'F720 Timer Z 8 2 Timer mode register TMDR 8 H'F721 Timer Z 8 2 Timer PWM mode register TPMR 8 H'F722 Timer Z 8 2 Timer Z, for common use TFCR 8 H'F723 Timer Z 8 2 Timer output master enable register TOER 8 H'F724 Timer Z
Section 21 List of Registers Data Bus Width Access State 8 2 H'F738 to H'F73F 8 H'F740 SCI3_2 8 3 BRR_2 8 H'F741 SCI3_2 8 3 Serial control register 3_2 SCR3_2 8 H'F742 SCI3_2 8 3 Transmit data register_2 TDR_2 8 H'F743 SCI3_2 8 3 Serial status register_2 SSR_2 8 H'F744 SCI3_2 8 3 Receive data register_2 RDR_2 8 H'F745 SCI3_2 8 3 H'F746, H'F747 SCI3_2 I2C bus control register 1 ICCR1 8 H'F748 IIC2 8 2 I2C bus control register 2 ICC
Section 21 List of Registers Address Module Name Data Bus Width Access State 8 H'FF93 ROM 8 2 H'FF94 to ROM H'FF9A Flash memory enable register FENR 8 H'FF9B 8 2 H'FF9C to ROM H'FF9F Timer control register V0 TCRV0 8 H'FFA0 Timer V 8 3 Timer control/status register V TCSRV 8 H'FFA1 Timer V 8 3 Time constant register A TCORA 8 H'FFA2 Timer V 8 3 Time constant register B TCORB 8 H'FFA3 Timer V 8 3 Timer counter V TCNTV 8 H'FFA4 Timer
Section 21 List of Registers Bit No Module Address Name Data Bus Width Access State ADCR 8 H'FFB9 8 3 H'FFBA, H'FFBB PWM data register L PWDRL 8 H'FFBC 14-bit PWM 8 2 PWM data register U PWDRU 8 H'FFBD 14-bit PWM 8 2 PWM control register PWCR 8 H'FFBE 14-bit PWM 8 2 H'FFBF 14-bit PWM Register Abbreviation A/D control register A/D converter Timer control/status register WD TCSRWD 8 H'FFC0 WDT* 1 8 2 Timer counter WD TCWD H'FFC1 W
Section 21 List of Registers Bit No Module Address Name Data Bus Width Access State PDR6 8 H'FFD9 I/O port 8 2 Port data register 7 PDR7 8 H'FFDA I/O port 8 2 Port data register 8 PDR8 8 H'FFDB I/O port 8 2 H'FFDC I/O port Port data register B PDRB 8 H'FFDD I/O port 8 2 Port data register C PDRC 8 H'FFDE I/O port 8 2 H'FFDF I/O port Port mode register 1 PMR1 8 H'FFE0 I/O port 8 2 Port mode register 5 PMR5 8 H'FFE1 I/O port
Section 21 List of Registers Bit No Module Address Name Data Bus Width Access State IRR2 8 H'FFF7 Interrupt 8 2 IWPR 8 H'FFF8 Interrupt 8 2 Register Abbreviation Interrupt flag register 2 Wakeup interrupt flag register Module standby control register 1 MSTCR1 8 H'FFF9 Low power 8 2 Module standby control register 2 MSTCR2 8 H'FFFA Low power 8 2 H'FFEB Low power H'FFFC to H'FFFF Notes: 1. WDT: Watchdog timer 2.
Section 21 List of Registers 21.2 Register Bits The addresses and bit names of the registers in the on-chip peripheral modules are listed below. The 16-bit register is indicated in two rows, 8 bits for each row.
Section 21 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name GRB_1 GRB1H7 GRB1H6 GRB1H5 GRB1H4 GRB1H3 GRB1H2 GRB1H1 GRB1H0 Timer Z GRB1L7 GRB1L6 GRB1L5 GRB1L4 GRB1L3 GRB1L2 GRB1L1 GRB1L0 GRC1H7 GRC1H6 GRC1H5 GRC1H4 GRC1H3 GRC1H2 GRC1H1 GRC1H0 GRC1L7 GRC1L6 GRC1L5 GRC1L4 GRC1L3 GRC1L2 GRC1L1 GRC1L0 GRC_1 GRD_1 GRD1H7 GRD1H6 GRD1H5 GRD1H4 GRD1H3 GRD1H2 GRD1H1 GRD1H0 GRD1L7 GRD1L6 GRD1L5 GRD1L4 GRD1L3 GRD1L2
Section 21 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name TDR_2 TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0 SCI3_2 SSR_2 TDRE RDRF OER FER PER TEND MPBR MPBT RDR_2 RDR7 RDR6 RDR5 RDR4 RDR3 RDR2 RDR1 RDR0 ICCR1 ICE RCVD MST TRS CKS3 CKS2 CKS1 CKS0 IIC2 ICCR2 BBSY SCP SDAO SDAOP SCLO IICRST ICMR MLS WAIT BCWP BC2 BC1 BC0 ICIER TIE TEIE RIE NAKIE STIE ACKE ACKBR ACKBT ICSR TDRE TEND R
Section 21 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name TDR TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0 SCI3 SSR TDRE RDRF OER FER PER TEND MPBR MPBT RDR RDR7 RDR6 RDR5 RDR4 RDR3 RDR2 RDR1 RDR0 ADDRA AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 A/D AD1 AD0 converter AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 AD9 AD8
Section 21 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name PDR2 P24 P23 P22 P21 P20 I/O port PDR3 P37 P36 P35 P34 P33 P32 P31 P30 PDR5 P57 P56 P55 P54 P53 P52 P51 P50 PDR6 P67 P66 P65 P64 P63 P62 P61 P60 PDR7 P76 P75 P74 P72 P71 P70 PDR8 P87 P86 P85 PDRB PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PDRC PC1 PC0 PMR1 IRQ3 IRQ2 IRQ1 IRQ0 TXD2 PWM TXD TMOW
Section 21 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name MSTCR1 MSTIIC MSTS3 MSTAD MSTWD MSTTV MSTTA Low power MSTCR2 MSTS3_2 MSTTB1 MSTTZ MSTPWM Notes: 1. 2. 3. 4. The LVDSEL bit is only provided for the 5.0-V specification products. WDT: Watchdog timer The BARE register is only provided for microcontrollers that support advanced mode.
Section 21 List of Registers 21.
Section 21 List of Registers Register Name Reset Active Sleep Subactive Subsleep Standby Module RSECDR RTC RMINDR RHRDR RWKDR RTCCR1 RTCCR2 RTCCSR Initialized LVDCR Initialized LVDSR Initialized LVDRF CKCSR Initialized CPG RCCR Initialized On-chip RCTRMDPR Initialized
Section 21 List of Registers Register Name Reset Active Sleep Subactive Subsleep Standby Module FLMCR1 Initialized Initialized Initialized Initialized ROM FLMCR2 Initialized FLPWCR Initialized EBR1 Initialized Initialized Initialized Initialized FENR Initialized TCRV0 Initialized Initialized Initialized Initialized TCSRV Initialized Initialized Initialized Initialized TCORA Initialized Initialized
Section 21 List of Registers Register Name Reset Active Sleep Subactive Subsleep Standby Module BARH Initialized Address break BARL Initialized BDRH Initialized Initialized BDRL 2 BARE* Initialized PUCR1 Initialized PUCR5 Initialized PDR1 Initialized PDR2 Initialized PDR3 Initialized PDR5 Initialized PDR6 Initiali
Section 21 List of Registers Register Name Reset Active Sleep Subactive Subsleep Standby Module IEGR1 Initialized Interrupt IEGR2 Initialized IENR1 Initialized IENR2 Initialized IRR1 Initialized IRR2 Initialized IWPR Initialized MSTCR1 Initialized MSTCR2 Initialized Low power Notes: is not initialized 1. WDT: Watchdog timer 2.
Section 21 List of Registers Rev. 3.00 Sep.
Section 22 Electrical Characteristics Section 22 Electrical Characteristics 22.1 Absolute Maximum Ratings Table 22.1 Absolute Maximum Ratings Item Symbol Value Unit Note Power supply voltage VCC –0.3 to +7.0 V * Analog power supply voltage AVCC –0.3 to +7.0 V Ports other than ports VIN B and X1 –0.3 to VCC +0.3 V Port B –0.3 to AVCC +0.3 V X1 –0.3 to 4.
Section 22 Electrical Characteristics 22.2 Electrical Characteristics (F-ZTAT™ 5.0-V Version) 22.2.1 Power Supply Voltage and Operating Ranges (1) Power Supply Voltage and Oscillation Frequency Range φOSC (MHz) φW (kHz) 20.0 32.768 4.0 4.5 • AVCC = 4.5 to 5.5 V • Active mode • Sleep mode Rev. 3.00 Sep. 10, 2007 Page 416 of 528 REJ09B0216-0300 5.5 VCC (V) 4.5 • AVCC = 4.5 to 5.5 V • All operating modes 5.
Section 22 Electrical Characteristics (2) Power Supply Voltage and Operating Frequency Range φ (MHz) 20.0 φSUB (kHz) 16.384 8.192 4.096 4.0 4.5 5.5 VCC (V) • AVCC = 4.5 to 5.5 V • Active mode • Sleep mode (When MA2 in SYSCR2 = 0 ) 4.5 5.5 VCC (V) • AVCC = 4.5 to 5.5 V • Subactive mode • Subsleep mode φ (kHz) 2500 78.125 4.5 5.5 VCC (V) • AVCC = 4.5 to 5.5 V • Active mode • Sleep mode (When MA2 in SYSCR2 = 1 ) Rev. 3.00 Sep.
Section 22 Electrical Characteristics (3) Analog Power Supply Voltage and A/D Converter Accuracy Guaranteed Range φ (MHz) 20.0 4.0 4.5 5.5 AVCC (V) • VCC = 4.5 to 5.5 V • Active mode • Sleep mode (4) Range of Power Supply Voltage and Oscillation Frequency when Low-Voltage Detection Circuit is Used φosc (MHz) 20.0 16.0 4.0 Vcc (V) 3.0 4.5 5.5 Operation guaranteed range Operation guaranteed range except A/D conversion accuracy Rev. 3.00 Sep.
Section 22 Electrical Characteristics 22.2.2 DC Characteristics Table 22.2 DC Characteristics (1) VCC = 4.5 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C/–40 to +85°C, unless otherwise indicated. Values Item Symbol Input high VIH voltage Min. Typ. Max. Unit RES, NMI, WKP0 to WKP5, IRQ0 to IRQ3, ADTRG, TMIB1, TMRIV, TMCIV, FTIOA0 to FTIOD0, FTIOA1 to FTIOD1, SCK3, SCK3_2, TRGV VCC × 0.8 — VCC + 0.
Section 22 Electrical Characteristics Values Item Symbol Applicable Pins Input low voltage VIL RXD, RXD_2, SCL, SDA, P10 to P12, P14 to P17, P20 to P24, P30 to P37, P50 to P57, P60 to P67, P70 to P72, P74 to P76, P85 to P87, PC0, PC1 PB0 to PB7 Test Condition Output low voltage VOH VOL Max. Unit –0.3 — VCC × 0.3 V — AVCC × 0.3 V –0.3 — 0.5 V V P10 to P12, P14 to P17, P20 to P24, P30 to P37, P50 to P55, P60 to P67, P70 to P72, P74 to P76, P85 to P87, PC0, PC1 –IOH = 1.5 mA VCC – 1.
Section 22 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition Min Typ Max Unit Input/ output leakage current | IIL | OSC1, TMIB1, RES, NMI, WKP0 to WKP5, IRQ0 to IRQ3, ADTRG, TRGV, TMRIV, TMCIV, FTIOA0 to FTIOD0, FTIOA1 to FTIOD1 RXD, SCK3, RXD_2, SCK3_2, SCL, SDA VIN = 0.5 V to (VCC – 0.5 V) — — 1.0 µA P10 to P12, P14 to P17, P20 to P24, P30 to P37, P50 to P57, P60 to P67, P70 to P72, P74 to P76, P85 to P87, PC0, PC1 VIN = 0.5 V to (VCC – 0.5 V) — — 1.
Section 22 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition Min. Typ. Max. Unit Notes Sleep mode supply current ISLEEP1 VCC Sleep mode 1 VCC = 5.0 V, fOSC = 20 MHz — 12.0 20.0 mA * Sleep mode 1 VCC = 5.0 V, fOSC = 10 MHz — 6.5 — Sleep mode 2 VCC = 5.0 V, fOSC = 20 MHz — 2.5 4.0 Sleep mode 2 VCC = 5.0 V, fOSC = 10 MHz — 2.2 — VCC = 5.0 V 32-kHz crystal resonator (φSUB = φW/2) — 95.0 145.0 VCC = 5.0 V 32-kHz crystal resonator (φSUB = φW/8) — 85.
Section 22 Electrical Characteristics Note: * Pin states during supply current measurement are given below (excluding current in the pull-up MOS transistors and output buffers).
Section 22 Electrical Characteristics Table 22.2 DC Characteristics (2) VCC = 4.5 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C/–40 to +85°C, unless otherwise indicated. Item Symbol Permissible output low current (per pin) IOL Permissible output low current (total) ∑IOL Applicable Pins Values Test Condition Min. Typ. Max. Unit Output pins except port 6, SCL, and SDA — — 2.0 mA Port 6 — — 20.0 Output pins except port 6, SCL, and SDA — — 40.0 Port 6, SCL, and SDA — — 80.
Section 22 Electrical Characteristics 22.2.3 AC Characteristics Table 22.3 AC Characteristics VCC = 4.5 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75°C/-40 to +85°C, unless otherwise indicated. Item Applicable Symbol Pins Values Test Condition Min. Typ. Max. Unit Reference Figure 4.0 — 20.0 MHz *1 1 — 64 tOSC *2 — — 12.8 µs System clock oscillation frequency fOSC System clock (φ) cycle time tcyc Subclock oscillation frequency fW X1, X2 — 32.
Section 22 Electrical Characteristics Item RES pin low width Applicable Symbol Pins tREL RES Values Typ. Max. Unit Reference Figure At power-on and in trc modes other than those below — — ms Figure 22.2 In active mode and 2500 sleep mode — — ns Test Condition Min.
Section 22 Electrical Characteristics Item On-chip oscillator oscillation frequency Applicable Symbol Pins fRC Values Test Condition Min. Typ. Max. Unit Vcc = 5.0 V, Ta = 25°C, FSEL = 1, VCLSEL = 0 19.70 20.0 20.30 MHz FSEL = 1, 19.40 Ta = -20 to +75°C, VCLSEL = 0 20.0 20.60 FSEL = 1, 19.20 Ta = -40 to +85°C, VCLSEL = 0 20.00 20.80 Vcc = 5.0 V, Ta = 25°C, FSEL = 0, VCLSEL = 0 15.76 16.0 16.24 FSEL = 0, 15.52 Ta = -20 to +75°C, VCLSEL = 0 16.0 16.48 FSEL = 0, 15.
Section 22 Electrical Characteristics 2 Table 22.4 I C Bus Interface Timing VCC = 4.5 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75°C/-40 to +85°C, unless otherwise indicated. Item Symbol SCL input cycle time tSCL Test Condition Values Max. Unit Reference Figure 12tcyc + 600 — — ns Figure 22.4 Min. Typ.
Section 22 Electrical Characteristics Table 22.5 Serial Communication Interface (SCI) Timing VCC = 4.5 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75°C/-40 to +85°C, unless otherwise indicated. Item Input clock cycle Asynchronous Symbol Applicable Pins tScyc SCK3 Clock synchronous Values Test Condition Min. Typ. Max. Unit Reference Figure 4 — — Figure 22.5 6 — — tcyc Input clock pulse width tSCKW SCK3 0.4 — 0.
Section 22 Electrical Characteristics 22.2.4 A/D Converter Characteristics Table 22.6 A/D Converter Characteristics VCC = 4.5 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75°C/-40 to +85°C, unless otherwise indicated. Item Symbol Applicable Pins Test Condition Values Min. Typ. Max. Unit Reference Figure V *1 Analog power supply AVCC voltage AVCC 4.5 VCC 5.5 Analog input voltage AVIN AN0 to AN7 VSS – 0.3 — AVCC + 0.3 V Analog power supply AIOPE current AVCC AVCC = 5.
Section 22 Electrical Characteristics Item Symbol Applicable Pins Conversion time (single mode) Test Condition Values Min. AVCC = 4.5 to 134 5.5 V Nonlinearity error — Typ. Max. Unit — — tcyc — ±3.5 LSB Offset error — — ±3.5 LSB Full-scale error — — ±3.5 LSB Quantization error — — ±0.5 LSB Absolute accuracy — — ±4.0 LSB Reference Figure Notes: 1. Set AVCC = VCC when the A/D converter is not used. 2.
Section 22 Electrical Characteristics 22.2.6 Flash Memory Characteristics Table 22.8 Flash Memory Characteristics VCC = 4.5 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75°C/-40 to +85°C, unless otherwise indicated. Test Condition Values Item Symbol Min. Typ. Max. Unit Programming time (per 128 bytes)*1*2*4 tP — 7.0 200.0 ms Erase time (per block) *1*3*6 tE — 10.0 20.
Section 22 Electrical Characteristics Item Erasing Symbol Test Condition Values Min. Typ. Max.
Section 22 Electrical Characteristics 22.2.7 Power-Supply-Voltage Detection Circuit Characteristics Table 22.9 Power-Supply-Voltage Detection Circuit Characteristics VSS = 0.0 V, Ta = -20 to +75°C/-40 to +85°C, unless otherwise indicated. Values Item Symbol Test Condition Min. Typ. Max. Unit Power-supply falling detection voltage Vint (D) LVDSEL = 0 3.4 3.7 — V Power-supply rising detection voltage Vint (U) LVDSEL = 0 — 4.0 4.
Section 22 Electrical Characteristics 22.2.9 Power-On Reset Circuit Characteristics Table 22.11 Power-On Reset Circuit Characteristics VSS = 0.0 V, Ta = -20 to +75°C/-40 to +85°C, unless otherwise indicated. Test Condition Values Item Symbol Min. Typ.
Section 22 Electrical Characteristics 22.3 Electrical Characteristics (F-ZTAT™ 3.3-V Version) 22.3.1 Power Supply Voltage and Operating Ranges (1) Power Supply Voltage and Oscillation Frequency Range φosc (MHz) φw (kHz) 16.0 32.768 4.0 3.0 • AVCC = 3.0 to 3.6 V • Active mode • Sleep mode Rev. 3.00 Sep. 10, 2007 Page 436 of 528 REJ09B0216-0300 3.6 VCC (V) 3.0 3.6 • AVCC = 3.0 to 3.
Section 22 Electrical Characteristics (2) Power Supply Voltage and Operating Frequency Range φ (MHz) φSUB (kHz) 16.0 16.384 8.192 4.096 4.0 3.0 φ (kHz) 3.6 3.0 VCC (V) • AVCC = 3.0 to 3.6 V • Active mode • Sleep mode (When MA2 in SYSCR2 = 0) 3.6 VCC (V) • AVCC = 3.0 to 3.6 V • Subactive mode • Subsleep mode 2500 78.125 3.0 3.6 VCC (V) • AVCC = 3.0 to 3.
Section 22 Electrical Characteristics 22.3.2 DC Characteristics Table 22.12 DC Characteristics (1) VCC = 3.0 to 3.6 V, VSS = 0.0 V, Ta = -20 to +75°C/-40 to +85°C, unless otherwise indicated. Values Item Symbol Input high VIH voltage Min. Typ. Max. Unit RES, NMI, WKP0 to WKP5, IRQ0 to IRQ3, ADTRG, TMIB1, TMRIV, TMCIV, FTIOA0 to FTIOD0, FTIOA1 to FTIOD1, SCK3, SCK3_2, TRGV VCC × 0.9 — VCC + 0.
Section 22 Electrical Characteristics Values Item Symbol Applicable Pins Input low voltage VIL RXD, RXD_2, SCL, SDA, P10 to P12, P14 to P17, P20 to P24, P30 to P37, P50 to P57, P60 to P67, P70 to P72, P74 to P76, P85 to P87, PC0, PC1 PB0 to PB7 Test Condition Output low voltage VOH VOL Typ. Max. Unit –0.3 — VCC × 0.2 V AVCC = 3.0 to 3.6 V –0.3 — AVCC × 0.2 V –0.3 — 0.3 V V OSC1 Output high voltage Min.
Section 22 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition Min Typ Max Unit Input/ output leakage current | IIL | OSC1, TMIB1, RES, NMI, WKP0 to WKP5, IRQ0 to IRQ3, ADTRG, TRGV, TMRIV, TMCIV, FTIOA0 to FTIOD0, FTIOA1 to FTIOD1 RXD, SCK3, RXD_2, SCK3_2, SCL, SDA VIN = 0.5 V to (VCC – 0.5 V) — — 1.0 µA P10 to P12, P14 to P17, P20 to P24, P30 to P37, P50 to P57, P60 to P67, P70 to P72, P74 to P76, P85 to P87, PC0, PC1 VIN = 0.5 V to (VCC – 0.5 V) — — 1.
Section 22 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition Min. Typ. Max. Unit Notes Sleep mode supply current ISLEEP1 VCC Sleep mode 1 VCC = 3.3 V, fOSC = 16 MHz — 9.0 14.0 mA * Sleep mode 1 VCC = 3.3 V, fOSC = 10 MHz — 6.5 — Sleep mode 2 VCC = 3.3 V, fOSC = 16 MHz — 2.2 3.5 Sleep mode 2 VCC = 3.3 V, fOSC = 10 MHz — 2.0 — VCC = 3.3 V 32-kHz crystal resonator (φSUB = φW/2) — 95.0 145.0 VCC = 3.3 V 32-kHz crystal resonator (φSUB = φW/8) — 85.
Section 22 Electrical Characteristics Note: * Pin states during supply current measurement are given below (excluding current in the pull-up MOS transistors and output buffers).
Section 22 Electrical Characteristics Table 22.12 DC Characteristics (2) VCC = 3.0 to 3.6 V, VSS = 0.0 V, Ta = -20 to +75°C/-40 to +85°C, unless otherwise indicated. Item Symbol Permissible output low current (per pin) IOL Permissible output low current (total) ∑IOL Applicable Pins Values Test Condition Min. Typ. Max. Unit Output pins except port 6, SCL, and SDA — — 2.0 mA Port 6 — — 20.0 Output pins except port 6, SCL, and SDA — — 40.0 Port 6, SCL, and SDA — — 80.
Section 22 Electrical Characteristics 22.3.3 AC Characteristics Table 22.13 AC Characteristics VCC = 3.0 to 3.6 V, VSS = 0.0 V, Ta = -20 to +75°C/-40 to +85°C, unless otherwise indicated. Item Symbol System clock oscillation frequency fOSC System clock (φ) cycle time tcyc Subclock oscillation frequency fW Watch clock (φW) cycle time tW Subclock (φSUB) cycle time tsubcyc Applicable Pins Min. Typ. Max. Unit Reference Figure 4.0 — 16.0 MHz *1 1 — 64 tOSC *2 — — 12.
Section 22 Electrical Characteristics Item Symbol Applicable Pins RES pin low width tREL RES Values Typ. Max. Unit Reference Figure At power-on and in trc modes other than those below — — ms Figure 22.2 In active mode and 2500 sleep mode — — ns Test Condition Min.
Section 22 Electrical Characteristics Item Symbol On-chip oscillator oscillation frequency fRC Applicable Pins Values Test Condition Min. Typ. Max. Unit Vcc = 3.3 V Ta = 25°C FSEL= 1 VCLSEL= 0 19.70 20.00 20.30 MHz FSEL = 1, 19.40 Ta = -20 to +75°C, VCLSEL = 0 20.00 20.60 FSEL = 1, Ta = -40 to 85°C, VCLSEL = 0 19.2 20.0 20.8 Vcc = 3.3 V, Ta = 25°C, FSEL = 0, VCLSEL = 0 15.76 16.00 16.24 FSEL = 0, Ta = -20 to +75°C VCLSEL = 0 15.52 16.0 16.48 FSEL = 0, 15.
Section 22 Electrical Characteristics 2 Table 22.14 I C Bus Interface Timing VCC = 3.0 to 3.6 V, VSS = 0.0 V, Ta = -20 to +75°C/-40 to +85°C, unless otherwise indicated. Item Symbol SCL input cycle time tSCL Test Condition Values Max. Unit Reference Figure 12tcyc + 600 — — ns Figure 22.4 Min. Typ.
Section 22 Electrical Characteristics Table 22.15 Serial Communication Interface (SCI) Timing VCC = 3.0 to 3.6 V, VSS = 0.0 V, Ta = -20 to +75°C/-40 to +85°C, unless otherwise indicated. Item Input clock cycle Asynchronous Symbol Applicable Pins tScyc SCK3 Clock synchronous Values Test Condition Min. Typ. Max. Unit Reference Figure 4 — — Figure 22.5 6 — — tcyc Input clock pulse width tSCKW SCK3 0.4 — 0.
Section 22 Electrical Characteristics 22.3.4 A/D Converter Characteristics Table 22.16 A/D Converter Characteristics VCC = 3.0 to 3.6 V, VSS = 0.0 V, Ta = -20 to +75°C/-40 to +85°C, unless otherwise indicated. Item Symbol Applicable Pins Test Condition Values Min. Typ. Max. Unit Reference Figure V *1 Analog power supply AVCC voltage AVCC 3.0 VCC 3.6 Analog input voltage AVIN AN0 to AN7 VSS – 0.3 — AVCC + 0.3 V Analog power supply AIOPE current AVCC AVCC = 3.
Section 22 Electrical Characteristics 22.3.5 Watchdog Timer Characteristics Table 22.17 Watchdog Timer Characteristics VCC = 3.0 to 3.6 V, VSS = 0.0 V, Ta = -20 to +75°C/-40 to +85°C, unless otherwise indicated. Item Symbol On-chip oscillator overflow time tOVF Note: * Applicable Pins Test Condition Values Min. Typ. Max. Unit Reference Figure 0.2 0.4 — s * Time until an internal reset is generated after the counter counts from 0 to 255 when the on-chip oscillator is selected Rev. 3.
Section 22 Electrical Characteristics 22.3.6 Flash Memory Characteristics Table 22.18 Flash Memory Characteristics VCC = 3.0 to 3.6 V, VSS = 0.0 V, Ta = -20 to +75°C/-40 to +85°C, unless otherwise indicated. Values Test Condition Item Symbol Min. Typ. Max. Unit Programming time (per 128 bytes)*1*2*4 tP — 7.0 200.0 ms Erase time (per block) *1*3*6 tE — 10.0 20.
Section 22 Electrical Characteristics Item Erasing Symbol Test Condition Values Min. Typ. Max.
Section 22 Electrical Characteristics 22.3.7 Power-Supply-Voltage Detection Circuit Characteristics Table 22.19 Power-Supply-Voltage Detection Circuit Characteristics VSS = 0.0 V, Ta = -20 to +75°C/-40 to +85°C, unless otherwise indicated. Values Item Symbol Min. Typ. Max. Unit Power-supply falling detection voltage Vint (D) 2.8 2.9 3.05 V Power-supply rising detection voltage Vint (U) 2.9 3.0 3.15 V Reset detection voltage 1* Vreset1 — 2.3 2.
Section 22 Electrical Characteristics 22.3.9 Power-On Reset Circuit Characteristics Table 22.21 Power-On Reset Circuit Characteristics VSS = 0.0 V, Ta = -20 to +75°C/-40 to +85°C, unless otherwise indicated. Test Condition Values Item Symbol Min. Typ.
Section 22 Electrical Characteristics 22.4 Operation Timing t OSC VIH OSC1 VIL t CPH t CPL t CPf t CPr Figure 22.1 System Clock Input Timing VCC VCC × 0.7 OSC1 tREL RES VIL VIL tREL Figure 22.2 RES Low Width Timing NMI IRQ0 to IRQ3 WKP0 to WKP5 ADTRG FTIOA0 to FTIOD0, FTIOA1 to FTIOD1, TMCIV, TMRIV TRGV VIH VIL t IL t IH Figure 22.3 Input Timing Rev. 3.00 Sep.
Section 22 Electrical Characteristics VIH SDA VIL tBUF tSTAH tSCLH tSTAS tSP tSTOS SCL P* S* tSf Sr* tSCLL tSCL P* tSDAS tSr tSDAH Note: * S, P, and Sr represent the following: S: Start condition P: Stop condition Sr: Retransmission start condition 2 Figure 22.4 I C Bus Interface Input/Output Timing t SCKW SCK3 t Scyc Figure 22.5 SCK3 Input Clock Timing Rev. 3.00 Sep.
Section 22 Electrical Characteristics t Scyc SCK3 VIH or VOH * VIL or VOL * t TXD * VOH TXD (transmit data) VOL * t RXS t RXH RXD (receive data) Note: * Output timing reference levels Output high: V OH= 2.0 V Output low: V OL= 0.8 V Load conditions are shown in figure 22.7. Figure 22.6 SCI Input/Output Timing in Clock Synchronous Mode Rev. 3.00 Sep.
Section 22 Electrical Characteristics 22.5 Output Load Condition VCC 2.4 kΩ LSI output pin 30 pF 12 k Ω Figure 22.7 Output Load Circuit Rev. 3.00 Sep.
Appendix Appendix A Instruction Set A.
Appendix Symbol Description ↔ Condition Code Notation (cont) Changed according to execution result * Undetermined (no guaranteed value) 0 Cleared to 0 1 Set to 1 — Not affected by execution of the instruction ∆ Varies depending on conditions, described in notes Rev. 3.00 Sep.
Appendix Table A.1 Instruction Set 1. Data Transfer Instructions Condition Code MOV.B @(d:16, ERs), Rd B 4 @(d:16, ERs) → Rd8 — — MOV.B @(d:24, ERs), Rd B 8 @(d:24, ERs) → Rd8 — — MOV.B @ERs+, Rd B @ERs → Rd8 ERs32+1 → ERs32 — — MOV.B @aa:8, Rd B 2 @aa:8 → Rd8 — — MOV.B @aa:16, Rd B 4 @aa:16 → Rd8 — — MOV.B @aa:24, Rd B 6 @aa:24 → Rd8 — — MOV.B Rs, @ERd B Rs8 → @ERd — — MOV.B Rs, @(d:16, ERd) B 4 Rs8 → @(d:16, ERd) — — MOV.
Appendix No. of States*1 Condition Code — — @(d:24, ERs) → ERd32 — — @ERs → ERd32 ERs32+4 → ERs32 — — 6 @aa:16 → ERd32 — — 8 @aa:24 → ERd32 — — ERs32 → @ERd — — ERs32 → @(d:16, ERd) — — ERs32 → @(d:24, ERd) — — ERd32–4 → ERd32 ERs32 → @ERd — — 6 ERs32 → @aa:16 — — 8 ERs32 → @aa:24 — — 0 — 0 — POP POP.W Rn W 2 @SP → Rn16 SP+2 → SP — — POP.L ERn L 4 @SP → ERn32 SP+4 → SP — — 0 — PUSH PUSH.W Rn W 2 SP–2 → SP Rn16 → @SP — — 0 — PUSH.
Appendix 2. Arithmetic Instructions No. of States*1 Condition Code Z V C ↔ ↔ — (2) ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ERd32+ERs32 → ERd32 — (2) ↔ ↔ (3) ↔ ↔ Rd16+Rs16 → Rd16 — (1) ERd32+#xx:32 → ERd32 2 Rd8+#xx:8 +C → Rd8 — 2 B 2 Rd8+Rs8 +C → Rd8 — ADDS ADDS.L #1, ERd L 2 ERd32+1 → ERd32 — — — — — — 2 ADDS.L #2, ERd L 2 ERd32+2 → ERd32 — — — — — — 2 ADDS.L #4, ERd L 2 ERd32+4 → ERd32 — — — — — — 2 INC.B Rd B 2 Rd8+1 → Rd8 — — INC.W #1, Rd W 2 Rd16+1 → Rd16 — — INC.
Appendix No. of States*1 Condition Code Advanced V C ERd32–1 → ERd32 — — L 2 ERd32–2 → ERd32 — — ↔ ↔ — 2 DAS.Rd B 2 Rd8 decimal adjust → Rd8 — * ↔ ↔ ↔ 2 DEC.L #2, ERd ↔ ↔ ↔ — * — 2 B 2 Rd8 × Rs8 → Rd16 (unsigned multiplication) — — — — — — 14 W 2 Rd16 × Rs16 → ERd32 (unsigned multiplication) — — — — — — 22 B 4 Rd8 × Rs8 → Rd16 (signed multiplication) — — ↔ W 4 Rd16 × Rs16 → ERd32 (signed multiplication) — — B 2 W DIVXU DIVXU. B Rs, Rd DIVXU.
Appendix No. of States*1 Condition Code W 2 0–Rd16 → Rd16 — NEG.L ERd L 2 0–ERd32 → ERd32 — EXTU EXTU.W Rd W 2 0 → ( of Rd16) — — 0 EXTU.L ERd L 2 0 → ( of ERd32) — — 0 EXTS EXTS.W Rd W 2 ( of Rd16) → ( of Rd16) — — EXTS.L ERd L 2 ( of ERd32) → ( of ERd32) — — Advanced ↔ ↔ ↔ NEG.W Rd Normal C ↔ ↔ ↔ — ↔ ↔ ↔ V ↔ ↔ ↔ ↔ 0–Rd8 → Rd8 2 0 — 2 ↔ 2 0 — 2 ↔ H B 0 — 2 ↔ Z ↔ I NEG NEG.
Appendix 3. Logic Instructions AND.B Rs, Rd B AND.W #xx:16, Rd W 4 AND.W Rs, Rd W AND.L #xx:32, ERd L AND.L ERs, ERd L OR.B #xx:8, Rd B OR.B Rs, Rd B OR.W #xx:16, Rd W 4 OR.W Rs, Rd W OR.L #xx:32, ERd L OR.L ERs, ERd L XOR.B #xx:8, Rd B XOR.B Rs, Rd B XOR.W #xx:16, Rd W 4 XOR.W Rs, Rd W XOR.L #xx:32, ERd L XOR.L ERs, ERd L 4 ERd32⊕ERs32 → ERd32 — — NOT.B Rd B 2 ¬ Rd8 → Rd8 — — NOT.W Rd W 2 ¬ Rd16 → Rd16 — — NOT.
Appendix 4. Shift Instructions W 2 SHAL.L ERd L 2 SHAR SHAR.B Rd B 2 SHAR.W Rd W 2 SHAR.L ERd L 2 SHLL SHLL.B Rd B 2 SHLL.W Rd W 2 SHLL.L ERd L 2 SHLR SHLR.B Rd B 2 SHLR.W Rd W 2 SHLR.L ERd L 2 ROTXL ROTXL.B Rd B 2 ROTXL.W Rd W 2 ROTXL.L ERd L 2 B 2 ROTXR.W Rd W 2 ROTXR.L ERd L 2 ROTL ROTL.B Rd B 2 ROTL.W Rd W 2 ROTL.L ERd L 2 ROTR ROTR.B Rd B 2 ROTR.W Rd W 2 ROTR.L ERd L 2 ROTXR ROTXR.
Appendix 5.
Appendix B BLD #xx:3, @aa:8 B BILD BILD #xx:3, Rd BST BILD #xx:3, @ERd B BILD #xx:3, @aa:8 B BST #xx:3, Rd B BST #xx:3, @ERd B BST #xx:3, @aa:8 B BIST BIST #xx:3, Rd B BIST #xx:3, @ERd B BIST #xx:3, @aa:8 B BAND BAND #xx:3, Rd B BAND #xx:3, @ERd B BAND #xx:3, @aa:8 B BIAND BIAND #xx:3, Rd BOR B B BIAND #xx:3, @ERd B BIAND #xx:3, @aa:8 B BOR #xx:3, Rd B BOR #xx:3, @ERd B BOR #xx:3, @aa:8 B BIOR BIOR #xx:3, Rd B BIOR #xx:3, @ERd B BIOR #xx:3, @aa:8 B BXOR BXOR #
Appendix 6. Branching Instructions Bcc No.
Appendix JMP BSR JSR RTS JMP @ERn — JMP @aa:24 — JMP @@aa:8 — BSR d:8 — BSR d:16 — JSR @ERn — JSR @aa:24 — JSR @@aa:8 — RTS — No.
Appendix 7. System Control Instructions No.
Appendix 8. Block Transfer Instructions EEPMOV No. of States*1 H N Z V C Normal — @@aa @(d, PC) I EEPMOV. B — 4 if R4L ≠ 0 then repeat @R5 → @R6 R5+1 → R5 R6+1 → R6 R4L–1 → R4L until R4L=0 else next — — — — — — 8+ 4n*2 EEPMOV.
REJ09B0216-0300 Rev. 3.00 Sep. 10, 2007 Page 474 of 528 XOR SUBX OR XOR AND MOV B C D E F BILD CMP BIAND BIST BLD BST TRAPA BEQ A BIXOR BAND AND RTE BNE MOV.B Table A.2 (2) LDC 7 ADDX BIOR BXOR OR BOR BSR BCS RTS BCC AND.B ANDC 6 9 BTST DIVXU BLS XOR.B XORC 5 ADD BCLR MULXU BHI OR.B ORC 4 8 7 BNOT DIVXU MULXU 5 BSET BRN BRA 6 LDC 3 Table A.2 Table A.2 Table A.2 Table A.2 (2) (2) (2) (2) STC NOP 4 3 2 1 0 2 1 Table A.
MOV 7A BRA 58 MOV DAS 1F 79 SUBS 1B 1 CMP CMP ADD BHI 2 ADD BRN NOT 17 DEC ROTXR 13 1A ROTXL 12 DAA 0F SHLR ADDS 0B 11 INC 0A SHLL MOV 01 10 0 OR OR SUB SUB BLS XOR XOR BCS AND AND BEQ BVC SUB 9 BVS NEG NOT DEC ROTR ROTXR DEC ROTL ADDS SLEEP 8 ROTXL EXTU INC 7 SHAR BNE 6 SHLR EXTU INC 5 SHAL BCC LDC/STC 4 SHLL 3 1st byte 2nd byte AH AL BH BL BPL A MOV BMI NEG CMP SUB ROTR ROTL SHAR C D BGE BLT DEC EXTS INC Table A.
REJ09B0216-0300 Rev. 3.00 Sep. 10, 2007 Page 476 of 528 DIVXS 3 BSET 7Faa7 * 2 BNOT BNOT BCLR BCLR Notes: 1. r is the register designation field. 2. aa is the absolute address field.
Appendix A.3 Number of Execution States The status of execution for each instruction of the H8/300H CPU and the method of calculating the number of states required for instruction execution are shown below. Table A.4 shows the number of cycles of each type occurring in each instruction, such as instruction fetch and data read/write. Table A.3 shows the number of states required for each cycle.
Appendix Table A.3 Number of Cycles in Each Instruction Access Location Execution Status (Instruction Cycle) On-Chip Memory On-Chip Peripheral Module 2 — Instruction fetch SI Branch address read SJ Stack operation SK Byte data access SL 2 or 3* Word data access SM 2 or 3* Internal operation SN Note: * 1 Depends on which on-chip peripheral module is accessed. See section 21.1, Register Addresses (Address Order). Rev. 3.00 Sep.
Appendix Table A.4 Number of Cycles in Each Instruction Instruction Branch Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic I J L M N ADD ADD.B #xx:8, Rd 1 ADD.B Rs, Rd 1 ADD.W #xx:16, Rd 2 ADD.W Rs, Rd 1 ADD.L #xx:32, ERd 3 ADD.L ERs, ERd 1 ADDS ADDS #1/2/4, ERd 1 ADDX ADDX #xx:8, Rd 1 ADDX Rs, Rd 1 AND.B #xx:8, Rd 1 AND.B Rs, Rd 1 AND.W #xx:16, Rd 2 AND.W Rs, Rd 1 AND.L #xx:32, ERd 3 AND.
Appendix Instruction Branch Byte Data Word Data Internal Fetch Addr.
Appendix Instruction Branch Byte Data Word Data Internal Fetch Addr.
Appendix Instruction Branch Byte Data Word Data Internal Fetch Addr.
Appendix Instruction Branch Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic I J L M N DEC DEC.B Rd 1 DEC.W #1/2, Rd 1 DEC.L #1/2, ERd 1 DIVXS.B Rs, Rd 2 12 DIVXS.W Rs, ERd 2 20 DIVXU DIVXU.B Rs, Rd 1 12 DIVXU.W Rs, ERd 1 EEPMOV EEPMOV.B 2 2n+2*1 EEPMOV.W 2 2n+2* EXTS.W Rd 1 EXTS.L ERd 1 EXTU.W Rd 1 EXTU.L ERd 1 INC.B Rd 1 INC.W #1/2, Rd 1 INC.
Appendix Instruction Branch Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic I J L M N MOV MOV.B #xx:8, Rd 1 MOV.B Rs, Rd 1 MOV.B @ERs, Rd 1 1 MOV.B @(d:16, ERs), Rd 2 1 MOV.B @(d:24, ERs), Rd 4 1 MOV.B @ERs+, Rd 1 1 MOV.B @aa:8, Rd 1 1 MOV.B @aa:16, Rd 2 1 MOV.B @aa:24, Rd 3 1 MOV.B Rs, @Erd 1 1 MOV.B Rs, @(d:16, ERd) 2 1 MOV.B Rs, @(d:24, ERd) 4 1 MOV.B Rs, @-ERd 1 1 MOV Stack K 2 2 MOV.
Appendix Instruction Branch Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic I J L M N MOV MOV.W Rs, @-ERd 1 1 2 MOV.W Rs, @aa:16 2 1 MOV.W Rs, @aa:24 3 1 MOV.L #xx:32, ERd 3 MOV.L ERs, ERd 1 MOV.L @ERs, ERd 2 2 MOV.L @(d:16,ERs), ERd 3 2 MOV.L @(d:24,ERs), ERd 5 2 MOV.L @ERs+, ERd 2 2 MOV.L @aa:16, ERd 3 2 MOV.L @aa:24, ERd 4 2 MOV.L ERs,@ERd 2 2 MOV.L ERs, @(d:16,ERd) 3 2 MOV.
Appendix Instruction Branch Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic I J L M N OR OR.B #xx:8, Rd 1 OR.B Rs, Rd 1 OR.W #xx:16, Rd 2 OR.W Rs, Rd 1 OR.L #xx:32, ERd 3 Stack K OR.L ERs, ERd 2 ORC ORC #xx:8, CCR 1 POP POP.W Rn 1 1 2 POP.L ERn 2 2 2 PUSH.W Rn 1 1 2 PUSH.L ERn 2 2 2 PUSH ROTL ROTR ROTXL ROTXR ROTL.B Rd 1 ROTL.W Rd 1 ROTL.L ERd 1 ROTR.B Rd 1 ROTR.W Rd 1 ROTR.L ERd 1 ROTXL.
Appendix Instruction Branch Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic I J L M N SHLL SHLL.B Rd 1 SHLL.W Rd 1 SHLL.L ERd 1 SHLR.B Rd 1 SHLR.W Rd 1 SHLR.L ERd 1 SLEEP SLEEP 1 STC STC CCR, Rd 1 STC CCR, @ERd 2 1 STC CCR, @(d:16,ERd) 3 1 STC CCR, @(d:24,ERd) 5 1 STC CCR,@-ERd 2 1 STC CCR, @aa:16 3 1 STC CCR, @aa:24 4 1 SUB.B Rs, Rd 1 SUB.W #xx:16, Rd 2 SUB.W Rs, Rd 1 SUB.L #xx:32, ERd 3 SUB.
Appendix A.4 Combinations of Instructions and Addressing Modes Table A.
Appendix Appendix B I/O Port Block Diagrams B.1 I/O Port Block Diagrams RES goes low in a reset, and SBY goes low at reset and in standby mode. Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR IRQ TRGV [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.1 Port 1 Block Diagram (P17) Rev. 3.00 Sep.
Appendix Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR IRQ [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.2 Port 1 Block Diagram (P14, P16) Rev. 3.00 Sep.
Appendix Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR IRQ TMIB1 [Legend] PUCR : Port pull-up control register PMR : Port mode register PDR : Port data register PCR : Port control register Figure B.3 Port 1 Block Diagram (P15) Rev. 3.00 Sep.
Appendix Internal data bus RES SBY PUCR Pull-up MOS PDR PCR [Legend] PUCR : Port pull-up control register PDR : Port data register PCR : Port control register Figure B.4 Port 1 Block Diagram (P12) Rev. 3.00 Sep.
Appendix Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR 14-bit PWM PWM [Legend] PUCR : Port pull-up control register PMR : Port mode register PDR : Port data register PCR : Port control register Figure B.5 Port 2 Block Diagram (P11) Rev. 3.00 Sep.
Appendix Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR RTC TMOW [Legend] PUCR : Port pull-up control register PMR : Port mode register PDR : Port data register PCR : Port control register Figure B.6 Port 1 Block Diagram (P10) Rev. 3.00 Sep.
Appendix Internal data bus SBY PMR PDR PCR [Legend] PMR : Port mode register PDR : Port data register PCR : Port control register Figure B.7 Port 2 Block Diagram (P24, P23) Rev. 3.00 Sep.
Appendix Internal data bus SBY PMR PDR PCR SCI3 TxD [Legend] PMR : Port mode register PDR : Port data register PCR : Port control register Figure B.8 Port 2 Block Diagram (P22) Rev. 3.00 Sep.
Appendix SBY Internal data bus PDR PCR SCI3 RE RxD [Legend] PDR: Port data register PCR: Port control register Figure B.9 Port 2 Block Diagram (P21) Rev. 3.00 Sep.
Appendix SBY SCI3 SCKIE SCKOE Internal data bus PDR PCR SCKO SCKI [Legend] PDR: Port data register PCR: Port control register Figure B.10 Port 2 Block Diagram (P20) Rev. 3.00 Sep.
Appendix Internal data bus SBY PDR PCR [Legend] PDR : Port data register PCR : Port control register Figure B.11 Port 3 Block Diagram (P37 to P30) Rev. 3.00 Sep.
Appendix Internal data bus SBY PMR PDR PCR IIC2 ICE SDAO/SCLO SDAI/SCLI [Legend] PMR : Port mode register PDR : Port data register PCR : Port control register Figure B.12 Port 5 Block Diagram (P57, P56) Rev. 3.00 Sep.
Appendix Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR WKP ADTRG [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.13 Port 5 Block Diagram (P55) Rev. 3.00 Sep.
Appendix Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR WKP [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.14 Port 5 Block Diagram (P54 to P50) Rev. 3.00 Sep.
Appendix Internal data bus SBY Timer Z Output control signals A to D PDR PCR FTIOA to FTIOD [Legend] PDR : Port data register PCR : Port control register Figure B.15 Port 6 Block Diagram (P67 to P60) Rev. 3.00 Sep.
Appendix Internal data bus SBY Timer V OS3 OS2 OS1 OS0 PDR PCR TMOV [Legend] PDR: Port data register PCR: Port control register Figure B.16 Port 7 Block Diagram (P76) Rev. 3.00 Sep.
Appendix Internal data bus SBY PDR PCR Timer V TMCIV [Legend] PDR: Port data register PCR: Port control register Figure B.17 Port 7 Block Diagram (P75) Rev. 3.00 Sep.
Appendix Internal data bus SBY PDR PCR Timer V TMRIV [Legend] PDR: Port data register PCR: Port control register Figure B.18 Port 7 Block Diagram (P74) Rev. 3.00 Sep.
Appendix Internal data bus SBY PMR PDR PCR SCI3_2 TxD [Legend] PMR : Port mode register PDR : Port data register PCR : Port control register Figure B.19 Port 7 Block Diagram (P72) Rev. 3.00 Sep.
Appendix SBY Internal data bus PDR PCR SCI3_2 RE RxD [Legend] PDR : Port data register PCR : Port control register Figure B.20 Port 7 Block Diagram (P71) SBY SCI3_2 SCKIE SCKOE Internal data bus PDR PCR SCKO SCKI [Legend] PDR : Port data register PCR : Port control register Figure B.21 Port 7 Block Diagram (P70) Rev. 3.00 Sep.
Appendix Internal data bus SBY PDR PCR [Legend] PDR: Port data register PCR: Port control register Figure B.22 Port 8 Block Diagram (P87 to P85) Rev. 3.00 Sep.
Appendix Internal data bus A/D converter CH3 to CH0 SCAN VIN DEC Low voltage detection circuit VDDII ExtD, ExtU Figure B.23 Port B Block Diagram (PB7 and PB6) Internal data bus A/D converter SCAN CH3 to CH0 DEC VIN Figure B.24 Port B Block Diagram (PB5 to PB0) Rev. 3.00 Sep.
Appendix SBY Internal data bus CPG PDR φ PCR PMRC1 PMRC0 XTALI [Legend] PDR: Port data register PCR: Port control register Figure B.25 Port B Block Diagram (PC1) Rev. 3.00 Sep.
Appendix SBY Internal data bus PDR PCR CPG PMRC0 EXTALI [Legend] PDR: Port data register PCR: Port control register Figure B.26 Port B Block Diagram (PC0) Rev. 3.00 Sep.
Appendix B.
Appendix Appendix C Product Code Lineup Product Classification Package Temperature Voltage 1 (Package 2 Product Group Specification* Specification* Product Code*3 Model Marking Code) Flash 5.
Appendix Product Classification Package Temperature Voltage 1 (Package 2 Product Group Specification* Specification* Product Code* Flash 5.0 V Regular H8/36077 H8/36077GF memory Group version H8/36077LF H8/36074GF H8/36074LF 3.3 V 5.0 V 3.
Figure D.1 FP-64K Package Dimensions *1 HD 64 49 ZD 1 48 e y Index mark D 16 33 *3 bp 17 32 x F ZE PLQP0064KB-A Detail F Terminal cross section b1 bp 0.3g MASS[Typ.] L1 c Previous Code 64P6Q-A / FP-64K / FP-64KV A RENESAS Code A2 JEITA Package Code E *2 Rev. 3.00 Sep. 10, 2007 Page 516 of 528 A1 REJ09B0216-0300 c1 P-LQFP64-10x10-0.50 L 11.8 c 0.5 L 1.0 1.25 ZE L1 1.25 ZD 0.65 0.08 8° 0.08 0.5 0.20 0.25 0.15 1.7 12.2 12.2 10.1 x 0.35 0° 0.125 0.
64 e 1 ZD D y *3 bp 16 33 x F M 17 32 MASS[Typ.] 1.2g Detail F L1 L Terminal cross section b1 bp θ 3.05 0.8 L 1.6 1.0 ZE L1 1.0 ZD 1.1 0.10 8° 0.22 0.45 0.25 0.15 0.8 0.15 0.17 0.35 0.37 0.10 17.5 17.5 y 0.5 0° 0.12 0.29 17.2 17.2 Max x e θ c1 c b1 bp A1 0.00 16.9 HE A 16.9 HD 14 2.70 A2 14 Nom Dimension in Millimeters Min E D Reference Symbol NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2.
Appendix Rev. 3.00 Sep.
Main Revisions and Additions in this Edition Item Page Revision (See Manual for Details) Section 7 ROM 127 Amended 7.6 Programmer Mode Section 16 Serial Communication Interface 3 (SCI3) In programmer mode, a PROM programmer can be used to perform programming/erasing via a socket adapter, just as a discrete flash memory. Use a PROM programmer that supports the MCU device type with the on-chip 128-kbyte flash memory (FZTAT64V5). 299 Operating Frequency ø (MHz) 12.288 Table 16.
Item Page Revision (See Manual for Details) Section 21 List of Registers 408 Added H8/3609G,H8/36079L Register Module Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Name EBR1 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 ROM H8/36078G,H8/36078L,H8/36077G,H8/36077L Register Module Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Name EBR1 – EB6 EB5 EB4 EB3 EB2 EB1 EB0 ROM H8/36074G,H8/36074L Register Module Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Name EBR1 – –
Item Page Revision (See Manual for Details) Table 22.6 A/D Converter Characteristics 431 Amended Values Item Min Typ Max Conversion time 134 — — (Single mode) Table 22.9 Power-SupplyVoltage Detection Circuit Characteristics 434 Nonlinearity error – — ±3.5 Offset error – — ±3.5 Full-scale error – — ±3.5 Quantization error – — ±0.5 Absolute accuracy – — ±4.0 Amended Values Item Reset detection voltage 2* Table 22.12 DC Characteristics (1) 440 2 Min Typ Max 3.3 3.
Item Page Revision (See Manual for Details) Table 22.13 AC Characteristics 446 Amended Table 22.19 Power-SupplyVoltage Detection Circuit Characteristics Values 453 REJ09B0216-0300 Typ. Min. 19.70 20.00 20.30 FSEL = 1, Ta = -20 to +75°C, VCLSEL = 0 19.40 20.00 20.60 FSEL = 1, Ta = -40 to +85°C, VCLSEL = 0 19.2 20.0 20.8 Vcc = 3.3 V, Ta = 25°C, FSEL = 0, VCLSEL = 0 15.76 16.00 16.24 FSEL = 0, Ta = -20 to +75°C, VCLSEL = 0 15.36 16.0 16.
Item Page Revision (See Manual for Details) Appendix C Product Code Lineup 515 Amended Product Classification Product Code*3 Model Marking Package (Package Product Group Voltage Temperature Specificat Specification ion*1 *2 5.0 V Regular HD64F36079GH HD64F36079GH Wide range HD64F36079GHW HD64F36079GHW Code) H8/36079 H8/36079GF Group QFP-64 (FP-64A) Regular HD64F36079GFZ HD64F36079GFZ Wide range HD64F36079GFZW HD64F36079GFZW LQFP-64 (FP-64K) H8/36079LF 3.
Item Page Revision (See Manual for Details) Appendix C Product Code Lineup 516 Amended Product Classification Product Code*3 Model Marking Package (Package Product Voltage Group Specification Code) *1 H8/36077 H8/36077GF 5.0 V Regular HD64F36077GH HD64F36077GH Wide range HD64F36077GHW HD64F36077GHW Group QFP-64 (FP-64A) Regular HD64F36077GFZ HD64F36077GFZ Wide range HD64F36077GFZW HD64F36077GFZW LQFP-64 (FP-64K) H8/36077LF 3.
Index Numerics D 14-bit PWM ............................................ 281 Data reading procedure ........................... 177 Data transfer instructions .......................... 20 A A/D converter ......................................... 367 Absolute address....................................... 31 Acknowledge .......................................... 346 Address break ........................................... 63 Addressing modes.....................................
Internal interrupts ..................................... 58 Internal power supply step-down circuit .................................... 393 Interrupt mask bit...................................... 15 Interrupt response time ............................. 60 Interval timer operation .......................... 182 IRQ3 to IRQ0 interrupts ........................... 56 L Large current ports...................................... 3 Logic operations instructions....................
BARL............................ 67, 400, 406, 412 BDRH ........................... 67, 400, 406, 412 BDRL............................ 67, 400, 406, 412 BRR ............................ 296, 399, 405, 411 CKCSR ......................... 76, 397, 404, 410 EBR1 .......................... 114, 399, 405, 411 FENR .......................... 116, 399, 405, 411 FLMCR1..................... 112, 398, 405, 411 FLMCR2..................... 113, 398, 405, 411 FLPWCR .................... 116, 398, 405, 411 GRA...........
TCNTV........................187, 399, 405, 411 TCORA........................188, 399, 405, 411 TCORB........................188, 399, 405, 411 TCR .............................214, 396, 403, 409 TCRV0 ........................188, 399, 405, 411 TCRV1 ........................191, 399, 405, 411 TCSRV ........................189, 399, 405, 411 TCSRWD ....................276, 400, 406, 411 TCWD .........................278, 400, 406, 411 TDR .............................290, 399, 406, 411 TFCR .................
Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8/36079 Group, H8/36077 Group Publication Date: Rev.1.00, Sep. 16, 2005 Rev.3.00, Sep. 10, 2007 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. 2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES http://www.renesas.com Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
H8/36079 Group, H8/36077 Group Hardware Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0216-0300
