Datasheet

Section 5 Clock Pulse Generator
CPG0200A_000020020200 Rev. 3.00 Sep. 10, 2007 Page 71 of 528
REJ09B0216-0300
Section 5 Clock Pulse Generator
The clock pulse generator (CPG) consists of a system clock generating circuitry, a subclock
generating circuitry, and two prescalers. The system clock generating circuitry includes an
external clock oscillator, a duty correction circuit, an on-chip oscillator, an RC clock divider, a
clock select circuit, and a system clock divider. The subclock generating circuitry includes a
subclock oscillator, and a subclock divider. The CPG can function as a clock generating circuitry
itself or in combination with an external oscillator. Figure 5.1 shows a block diagram of the clock
pulse generator.
External
clock
oscillator
Duty
correction
circuit
System
clock
divider
Prescaler S
(13 bits)
OSC1
OSC2
φ
OSC
φ
OSC
φ/2
to
φ/8192
φ
φ/8
φ
φ/16
φ/32
φ/64
On-chip
oscillator
Clock
select
circuit
RC clock
divider
R
OSC
R
OSC
φ
φ
RC
R
OSC
/2
R
OSC
/4
Subclock
oscillator
Subclock
divider
Prescaler W
(5 bits)
X
1
X
2
System clock generating circuitry
φ
W
(f
W
)
φ
W
/2
φ
W
/4
φ
SUB
φ
W
/8
φ
W
/8
to
φ
W
/128
Subclock generating circuitry
Figure 5.1 Block Diagram of Clock Pulse Generator
The system clock (φ) and subclock (φ
SUB
) are basic clocks on which the CPU and on-chip
peripheral modules operate. The system clock is divided into from φ/2 to φ/8192 by prescaler S.
The subclock is divided into from φ
W
/8 to φ
W
/128 by prescaler W. These divided clocks are
supplied to respective peripheral modules.