Datasheet

Section 5 Clock Pulse Generator
Rev. 3.00 Sep. 10, 2007 Page 84 of 528
REJ09B0216-0300
[Legend]
φOSC: External clock
φRC: On-chip oscillator clock
φ: System clock
OSCSEL: Bit 4 in CKCSR
PHISTOP: System clock stop control signal
CKSTA: Bit 0 in CKCSR
CKSWIF: Bit 2 in CKCSR
φ halt*
On-chip oscillator
clock operation
Note: * The φ halt duration is the duration from the timing when the φ clock stops to the
seventh rising edge of the φ
RC
clock.
φOSC
φRC
PHISTOP
(Internal signal)
φ
OSCSEL
CKSTA
External RC clock operation
CKSWIF
Figure 5.7 Timing Chart to Switch from External Clock to On-Chip Oscillator Clock