Datasheet

Section 13 Timer Z
Rev. 3.00 Sep. 10, 2007 Page 210 of 528
REJ09B0216-0300
TCNT_0
Normal phase
Counter phase
Normal phase
Counter phase
Active level
Active level
Active level
Active level
Complementary PWM mode
Note: Write H'00 to TOCR to start initial outputs after stopping the counter.
Reset synchronous PWM mode
Initial
output
Initial
output
TCNT_1
Figure 13.4 Example of Outputs in Reset Synchronous PWM Mode
and Complementary PWM Mode
13.3.5 Timer Output Master Enable Register (TOER)
TOER enables/disables the outputs for channel 0 and channel 1. When WKP4 is selected for
inputs, if a low level signal is input to WKP4, the bits in TOER are set to 1 to disable the output
for timer Z.
Bit Bit Name
Initial
Value
R/W Description
7 ED1 1 R/W Master Enable D1
0: FTIOD1 pin output is enabled according to the TPMR,
TFCR, and TIORC_1 settings
1: FTIOD1 pin output is disabled regardless of the TPMR,
TFCR, and TIORC_1 settings (FTIOD1 pin is operated
as an I/O port).
6 EC1 1 R/W Master Enable C1
0: FTIOC1 pin output is enabled according to the TPMR,
TFCR, and TIORC_1 settings
1: FTIOC1 pin output is disabled regardless of the TPMR,
TFCR, and TIORC_1 settings (FTIOC1 pin is operated
as an I/O port).