Datasheet

Section 17 I
2
C Bus Interface 2 (IIC2)
Rev. 3.00 Sep. 10, 2007 Page 340 of 528
REJ09B0216-0300
Bit Bit Name
Initial
Value
R/W Description
2 ACKE 0 R/W Acknowledge Bit Judgment Select
0: The value of the receive acknowledge bit is ignored,
and continuous transfer is performed.
1: If the receive acknowledge bit is 1, continuous transfer
is halted.
1 ACKBR 0 R Receive Acknowledge
In transmit mode, this bit stores the acknowledge data
that are returned by the receive device. This bit cannot be
modified.
0: Receive acknowledge = 0
1: Receive acknowledge = 1
0 ACKBT 0 R/W Transmit Acknowledge
In receive mode, this bit specifies the bit to be sent at the
acknowledge timing.
0: 0 is sent at the acknowledge timing.
1: 1 is sent at the acknowledge timing.
17.3.5 I
2
C Bus Status Register (ICSR)
ICSR performs confirmation of interrupt request flags and status.
Bit Bit Name
Initial
Value
R/W Description
7 TDRE 0 R/W Transmit Data Register Empty
[Setting conditions]
• When data is transferred from ICDRT to ICDRS and
ICDRT becomes empty
• When TRS is set
• When a start condition (including re-transfer) has
been issued
• When transmit mode is entered from receive mode in
slave mode
[Clearing conditions]
• When 0 is written in TDRE after reading TDRE = 1
• When data is written to ICDRT with an instruction