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To our customers,

Old Company Name in Catalogs and Other Documents

On April 1

, 2010, NEC Electronics Corporation merged with Renesas Technology

Corporation, and Renesas

Electronics Corporation took over all the business of both

companies.

Therefore, although the old company name remains in this document, it is a valid

Renesas Electronics document. We appreciate your understanding.

Renesas Electronics website: http://www.renesas.com

April 1

, 2010

Renesas Electronics Corporation

Issued by: Renesas Electronics Corporation (http://www.renesas.com)

Send any inquiries to http://www.renesas.com/inquiry

Summary of content (508 pages)

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To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.
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Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office.
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User’s Manual The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8/36087 Group 16 Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series H8/36087F H8/36087 H8/36086 H8/36085 H8/36084 H8/36083 H8/36082 HD64F36087 HD64336087 HD64336086 HD64336085 HD64336084 HD64336083 HD64336082 Rev.2.00 2005.
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Rev. 2.00 Sep.
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
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General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins.
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Configuration of This Manual This manual comprises the following items: 1. 2. 3. 4. 5. 6. General Precautions on Handling of Product Configuration of This Manual Preface Contents Overview Description of Functional Modules • CPU and System-Control Modules • On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module.
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Preface The H8/36087 Group are single-chip microcomputers made up of the high-speed H8/300H CPU employing Renesas Technology original architecture as their cores, and the peripheral functions required to configure a system. The H8/300H CPU has an instruction set that is compatible with the H8/300 CPU. Target Users: This manual was written for users who will be using the H8/36087 Group in the design of application systems.
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1. The NMI pin is reserved for the E7 or E8, and cannot be used. 2. Pins P85, P86, and P87 cannot be used. In order to use these pins, additional hardware must be provided on the user board. 3. Area H’D000 to H’DFFF is used by the E7 or E8, and is not available to the user. 4. Area H’F780 to H’FB7F must on no account be accessed. 5. When the E7 or E8 is used, address breaks can be set as either available to the user or for use by the E7 or E8.
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Application notes: Document Title Document No. H8S, H8/300 Series C/C++ Compiler Package Application Note TM Single Power Supply F-ZTAT On-Board Programming Rev. 2.00 Sep.
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Contents Section 1 Overview................................................................................................1 1.1 1.2 1.3 1.4 Features.................................................................................................................................. 1 Internal Block Diagram.......................................................................................................... 3 Pin Arrangement ..................................................................................
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3.3 3.4 3.5 3.2.4 Interrupt Enable Register 2 (IENR2) ...................................................................... 51 3.2.5 Interrupt Flag Register 1 (IRR1)............................................................................. 51 3.2.6 Interrupt Flag Register 2 (IRR2)............................................................................. 53 3.2.7 Wakeup Interrupt Flag Register (IWPR) ................................................................ 53 Reset Exception Handling........
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Section 6 Power-Down Modes ............................................................................73 6.1 6.2 6.3 6.4 6.5 Register Descriptions ........................................................................................................... 74 6.1.1 System Control Register 1 (SYSCR1) .................................................................... 74 6.1.2 System Control Register 2 (SYSCR2) .................................................................... 76 6.1.
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Section 8 RAM .................................................................................................. 107 Section 9 I/O Ports............................................................................................. 109 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 Port 1.................................................................................................................................. 109 9.1.1 Port Mode Register 1 (PMR1) ...............................................................
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Section 10 Realtime Clock (RTC) .....................................................................141 10.1 Features.............................................................................................................................. 141 10.2 Input/Output Pin................................................................................................................. 143 10.3 Register Descriptions .................................................................................................
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12.4 Operation ........................................................................................................................... 166 12.4.1 Timer V Operation................................................................................................ 166 12.5 Timer V Application Examples ......................................................................................... 169 12.5.1 Pulse Output with Arbitrary Duty Cycle............................................................... 169 12.
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Section 14 Watchdog Timer ..............................................................................251 14.1 Features.............................................................................................................................. 251 14.2 Register Descriptions ......................................................................................................... 252 14.2.1 Timer Control/Status Register WD (TCSRWD)................................................... 252 14.2.
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16.6.1 Multiprocessor Serial Data Transmission ............................................................. 298 16.6.2 Multiprocessor Serial Data Reception .................................................................. 300 16.7 Interrupts............................................................................................................................ 304 16.8 Usage Notes .......................................................................................................................
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Section 18 A/D Converter..................................................................................345 18.1 Features.............................................................................................................................. 345 18.2 Input/Output Pins ............................................................................................................... 347 18.3 Register Descriptions ............................................................................................
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Appendix A Instruction Set ............................................................................... 407 A.1 A.2 A.3 A.4 Instruction List................................................................................................................... 407 Operation Code Map.......................................................................................................... 422 Number of Execution States ............................................................................................
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Figures Section 1 Overview Figure 1.1 Internal Block Diagram of H8/36087 Group of F-ZTAT TM and Mask-ROM Versions......................................................................................................................... 3 Figure 1.2 Pin Arrangement of H8/36087 Group of F-ZTATTM and Mask-ROM Versions (FP-64E, FP-64A).......................................................................................................... 4 Section 2 CPU Figure 2.1 Memory Map (1) ...............................
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Figure 5.4 Equivalent Circuit of Crystal Resonator...................................................................... 68 Figure 5.5 Typical Connection to Ceramic Resonator.................................................................. 69 Figure 5.6 Example of External Clock Input ................................................................................ 69 Figure 5.7 Block Diagram of Subclock Generator ....................................................................... 70 Figure 5.
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Figure 12.6 TMOV Output Timing ............................................................................................ 168 Figure 12.7 Clear Timing by Compare Match............................................................................ 168 Figure 12.8 Clear Timing by TMRIV Input ............................................................................... 169 Figure 12.9 Pulse Output Example .............................................................................................
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Figure 13.31 Example of Complementary PWM Mode Operation (1) ...................................... 222 Figure 13.32 (1) Example of Complementary PWM Mode Operation (TPSC2 = TPSC1 = TPSC0 = 0) (2) ................................................................ 224 Figure 13.32 (2) Example of Complementary PWM Mode Operation (TPSC2 = TPSC1 = TPSC0 ≠ 0) (3) ................................................................ 225 Figure 13.33 Timing of Overshooting ................................................
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Section 14 Watchdog Timer Figure 14.1 Block Diagram of Watchdog Timer ........................................................................ 251 Figure 14.2 Watchdog Timer Operation Example...................................................................... 255 Section 15 14-Bit PWM Figure 15.1 Block Diagram of 14-Bit PWM .............................................................................. 257 Figure 15.2 Waveform Output by 14-Bit PWM ...........................................................
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Figure 17.4 I2C Bus Timing........................................................................................................ 324 Figure 17.5 Master Transmit Mode Operation Timing (1)......................................................... 326 Figure 17.6 Master Transmit Mode Operation Timing (2)......................................................... 326 Figure 17.7 Master Receive Mode Operation Timing (1) .......................................................... 328 Figure 17.
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Figure B.6 Port 1 Block Diagram (P10) ..................................................................................... 443 Figure B.7 Port 2 Block Diagram (P24, P23) ............................................................................. 444 Figure B.8 Port 2 Block Diagram (P22) ..................................................................................... 445 Figure B.9 Port 2 Block Diagram (P21) .....................................................................................
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Rev. 2.00 Sep.
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Tables Section 1 Overview Table 1.1 Pin Functions ............................................................................................................ 5 Section 2 CPU Table 2.1 Operation Notation ................................................................................................. 19 Table 2.2 Data Transfer Instructions....................................................................................... 20 Table 2.3 Arithmetic Operations Instructions (1) ...............................
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Table 7.3 Table 7.4 Table 7.5 Table 7.6 Table 7.7 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible................................................................................................................... 96 Reprogram Data Computation Table .................................................................... 100 Additional-Program Data Computation Table ...................................................... 100 Programming Time ...................................
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Table 16.6 Table 16.7 SSR Status Flags and Receive Data Handling ...................................................... 285 SCI3 Interrupt Requests........................................................................................ 304 Section 17 I2C Bus Interface 2 (IIC2) Table 17.1 I2C Bus Interface Pins........................................................................................... 310 Table 17.2 Transfer Rate ..............................................................................
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Rev. 2.00 Sep.
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Section 1 Overview Section 1 Overview 1.
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Section 1 Overview • On-chip memory Model Product Classification Standard Version ROM RAM Flash memory version TM (F-ZTAT version) H8/36087F HD64F36087 56 kbytes 4 kbytes Mask-ROM version H8/36087 HD64336087 56 kbytes 3 kbytes H8/36086 HD64336086 48 kbytes 3 kbytes H8/36085 HD64336085 40 kbytes 3 kbytes H8/36084 HD64336084 32 kbytes 3 kbytes H8/36083 HD64336083 24 kbytes 3 kbytes H8/36082 HD64336082 16 kbytes 3 kbytes • General I/O ports  I/O pins: 45 I/O pins including 8
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Section 1 Overview P57/SCL P56/SDA P55/WKP5/ADTRG P54/WKP4 P53/WKP3 P52/WKP2 P51/WKP1 P50/WKP0 NMI TEST RES VSS VCC VCC OSC1 OSC2 CPU H8/300H Port 6 Port 7 P76/TMOV P75/TMCIV P74/TMRIV P72/TXD_2 P71/RXD_2 P70/SCK3_2 Port 1 P67/FTIOD1 P66/FTIOC1 P65/FTIOB1 P64/FTIOA1 P63/FTIOD0 P62/FTIOC0 P61/FTIOB0 P60/FTIOA0 RAM ROM IIC2 RTC SCI3 14-bit PWM SCI3_2 Timer Z Watchdog timer Timer V Port 8 P30 P31 P32 P33 P34 P35 P36 P37 System clock generator Port 2 P20/SCK3 P21/RXD P22/TXD P23 P24 S
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Section 1 Overview P62/FTIOC0 P61/FTIOB0 NMI P60/FTIOA0 P64/FTIOA1 P65/FTIOB1 P66/FTIOC1 P67/FTIOD1 P85 P86 P87 P20/SCK3 P21/RXD P22/TXD P23 Pin Arrangement P70/SCK3_2 1.
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Section 1 Overview 1.4 Pin Functions Table 1.1 Pin Functions Pin No. Type FP-64E FP-64A I/O Functions 6, 12 Input Power supply pin. Be sure to connect both two pins to the system power supply. VSS 9 Input Ground pin. Connect this pin to the system power supply (0V). AVCC 3 Input Analog power supply pin for the A/D converter. When the A/D converter is not used, connect this pin to the system power supply.
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Section 1 Overview Pin No.
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Section 1 Overview Pin No. Type Symbol I/O ports FP-64E FP-64A I/O Functions PB7 to PB0 1, 2, 59 to 64 Input 8-bit input port. P17 to P14, 51 to 54, P12 to P10 23 to 25 I/O 7-bit I/O port. P24 to P20 31, 44 to 47 I/O 5-bit I/O port.
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Section 1 Overview Rev. 2.00 Sep.
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Section 2 CPU Section 2 CPU This LSI has an H8/300H CPU with an internal 32-bit architecture that is upward-compatible with the H8/300CPU, and supports only normal mode, which has a 64-kbyte address space. • Upward-compatible with H8/300 CPUs  Can execute H8/300 CPUs object programs  Additional eight 16-bit extended registers  32-bit transfer and arithmetic and logic instructions are added  Signed multiply and divide instructions are added.
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Section 2 CPU • Power-down state  Transition to power-down state by SLEEP instruction 2.1 Address Space and Memory Map The address space of this LSI is 64 kbytes, which includes the program area and the data area. Figures 2.1 show the memory map.
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Section 2 CPU HD64336084 (Mask-ROM version) H'0000 H'0041 H'0042 Interrupt vector HD64336086 (Mask-ROM version) HD64336085 (Mask-ROM version) H'0000 H'0041 H'0042 On-chip ROM (32 kbytes) Interrupt vector H'0000 H'0041 H'0042 On-chip ROM (40 kbytes) Interrupt vector HD64336087 (Mask-ROM version) H'0000 H'0041 H'0042 Interrupt vector On-chip ROM (48 kbytes) H'7FFF H'9FFF On-chip ROM (56 kbytes) H'BFFF Not used Not used Not used H'DFFF Not used H'E800 H'E800 H'EFFF H'EFFF Internal I/O regi
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Section 2 CPU 2.2 Register Configuration The H8/300H CPU has the internal registers shown in figure 2.2. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), and an 8-bit condition-code register (CCR).
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Section 2 CPU 2.2.1 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.3 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).
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Section 2 CPU Empty area SP (ER7) Stack area Figure 2.4 Relationship between Stack Pointer and Stack Area 2.2.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0).
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Section 2 CPU Bit Bit Name Initial Value R/W Description 7 I 1 R/W Interrupt Mask Bit Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence. 6 UI Undefined R/W User Bit Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. 5 H Undefined R/W Half-Carry Flag When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.
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Section 2 CPU 2.3 Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.3.1 General Register Data Formats Figure 2.5 shows the data formats in general registers.
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Section 2 CPU Data Type General Register Word data Rn Data Format 15 Word data MSB En 15 MSB Longword data 0 LSB 0 LSB ERn 31 16 15 MSB 0 LSB Legend ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2.5 General Register Data Formats (2) Rev. 2.00 Sep.
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Section 2 CPU 2.3.2 Memory Data Formats Figure 2.6 shows the data formats in memory. The H8/300H CPU can access word data and longword data in memory, however word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, an address error does not occur, however the least significant bit of the address is regarded as 0, so access begins the preceding address. This also applies to instruction fetches.
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Section 2 CPU 2.4 Instruction Set 2.4.1 Table of Instructions Classified by Function The H8/300H CPU has 62 instructions. Tables 2.2 to 2.9 summarize the instructions in each functional category. The notation used in tables 2.2 to 2.9 is defined below. Table 2.
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Section 2 CPU Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers/address register (ER0 to ER7). Table 2.2 Data Transfer Instructions Instruction Size* Function MOV B/W/L (EAs) → Rd, Rs → (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B (EAs) → Rd Cannot be used in this LSI.
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Section 2 CPU Table 2.3 Arithmetic Operations Instructions (1) Instruction Size* Function ADD SUB B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.
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Section 2 CPU Table 2.3 Arithmetic Operations Instructions (2) Instruction Size* Function DIVXS B/W Rd ÷ Rs → Rd Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder. CMP B/W/L Rd – Rs, Rd – #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result.
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Section 2 CPU Table 2.4 Logic Operations Instructions Instruction Size* Function AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd Performs a logical OR operation on a general register and another general register or immediate data.
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Section 2 CPU Table 2.6 Bit Manipulation Instructions (1) Instruction Size* Function BSET B 1 → ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 → ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
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Section 2 CPU Table 2.6 Bit Manipulation Instructions (2) Instruction Size* Function BXOR B C ⊕ ( of ) → C XORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B C ⊕ ¬ ( of ) → C XORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BLD B (
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Section 2 CPU Table 2.7 Branch Instructions Instruction Size Function Bcc*  Branches to a specified address if a specified condition is true. The branching conditions are listed below.
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Section 2 CPU Table 2.8 System Control Instructions Instruction Size* Function TRAPA  Starts trap-instruction exception handling. RTE  Returns from an exception-handling routine. SLEEP  Causes a transition to a power-down state. LDC B/W (EAs) → CCR Moves the source operand contents to the CCR. The CCR size is one byte, but in transfer from memory, data is read by word access. STC B/W CCR → (EAd) Transfers the CCR contents to a destination location.
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Section 2 CPU Table 2.9 Block Data Transfer Instructions Instruction Size Function EEPMOV.B  if R4L ≠ 0 then Repeat @ER5+ → @ER6+, R4L–1 → R4L Until R4L = 0 else next; EEPMOV.W  if R4 ≠ 0 then Repeat @ER5+ → @ER6+, R4–1 → R4 Until R4 = 0 else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed. Rev. 2.00 Sep.
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Section 2 CPU 2.4.2 Basic Instruction Formats H8/300H CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op), a register field (r), an effective address extension (EA), and a condition field (cc). Figure 2.7 shows examples of instruction formats. • Operation Field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction.
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Section 2 CPU 2.5 Addressing Modes and Effective Address Calculation The following describes the H8/300H CPU. In this LSI, the upper eight bits are ignored in the generated 24-bit address, so the effective address is 16 bits. 2.5.1 Addressing Modes The H8/300H CPU supports the eight addressing modes listed in table 2.10. Each instruction uses a subset of these addressing modes. Addressing modes that can be used differ depending on the instruction. For details, refer to Appendix A.
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Section 2 CPU (1) Register DirectRn The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. (2) Register Indirect@ERn The register field of the instruction code specifies an address register (ERn), the lower 24 bits of which contain the address of the operand on memory.
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Section 2 CPU The access ranges of absolute addresses for the group of this LSI are those shown in table 2.11, because the upper 8 bits are ignored. Table 2.11 Absolute Address Access Ranges Absolute Address Access Range 8 bits (@aa:8) H'FF00 to H'FFFF 16 bits (@aa:16) H'0000 to H'FFFF 24 bits (@aa:24) H'0000 to H'FFFF (6) Immediate#xx:8, #xx:16, or #xx:32 The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand.
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Section 2 CPU Specified by @aa:8 Dummy Branch address Figure 2.8 Branch Address Specification in Memory Indirect Mode Rev. 2.00 Sep.
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Section 2 CPU 2.5.2 Effective Address Calculation Table 2.12 indicates how effective addresses are calculated in each addressing mode. In this LSI the upper 8 bits of the effective address are ignored in order to generate a 16-bit effective address. Table 2.12 Effective Address Calculation (1) No 1 Addressing Mode and Instruction Format op 2 Effective Address Calculation Effective Address (EA) Register direct(Rn) rm Operand is general register contents.
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Section 2 CPU Table 2.12 Effective Address Calculation (2) No 5 Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Absolute address @aa:8 8 7 23 op abs 0 H'FFFF @aa:16 23 op abs 16 15 0 Sign extension @aa:24 op 0 23 abs 6 Immediate #xx:8/#xx:16/#xx:32 op 7 Operand is immediate data.
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Section 2 CPU 2.6 Basic Bus Cycle CPU operation is synchronized by a system clock (φ) or a subclock (φSUB). The period from a rising edge of φ or φSUB to the next rising edge is called one state. A bus cycle consists of two states or three states. The cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules. 2.6.1 Access to On-Chip Memory (RAM, ROM) Access to on-chip memory takes place in two states.
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Section 2 CPU 2.6.2 On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits or 16 bits depending on the register. For description on the data bus width and number of accessing states of each register, refer to section 19.1, Register Addresses (Address Order). Registers with 16-bit data bus width can be accessed by word size only. Registers with 8-bit data bus width can be accessed by byte or word size.
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Section 2 CPU 2.7 CPU States There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active mode and subactive mode. For the program halt state, there are a sleep mode, standby mode, and sub-sleep mode. These states are shown in figure 2.11. Figure 2.12 shows the state transitions. For details on program execution state and program halt state, refer to section 6, Power-Down Modes.
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Section 2 CPU Reset cleared Reset state Exception-handling state Reset occurs Reset occurs Reset occurs Interrupt source Program halt state Interrupt source Exceptionhandling complete Program execution state SLEEP instruction executed Figure 2.12 State Transitions 2.8 Usage Notes 2.8.1 Notes on Data Access to Empty Areas The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip I/O registers areas available to the user.
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Section 2 CPU (1) Bit manipulation for two registers assigned to the same address • Example 1: Bit manipulation for the timer load register and timer counter (Applicable for timer B1 in the H8/36087 Group.) Figure 2.13 shows an example of a timer in which two timer registers are assigned to the same address. When a bit-manipulation instruction accesses the timer load register and timer counter of a reloadable timer, since these two registers share the same address, the following operations takes place.
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Section 2 CPU  Prior to executing BSET instruction P57 P56 P55 P54 P53 P52 P51 P50 Input/output Input Input Output Output Output Output Output Output Pin state Low level High level Low level Low level Low level Low level Low level Low level PCR5 0 0 1 1 1 1 1 1 PDR5 1 0 0 0 0 0 0 0  BSET instruction executed instruction BSET #0, @PDR5 The BSET instruction is executed for port 5.
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Section 2 CPU  Prior to executing BSET instruction MOV.B MOV.B MOV.B #80, R0L, R0L, R0L @RAM0 @PDR5 The PDR5 value (H'80) is written to a work area in memory (RAM0) as well as to PDR5.
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Section 2 CPU (2) Bit Manipulation in a Register Containing a Write-Only Bit • Example 3: BCLR instruction executed designating port 5 control register PCR5 P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at P56. P55 to P50 are output pins that output low-level signals. An example of setting the P50 pin as an input pin by the BCLR instruction is shown below. It is assumed that a high-level signal will be input to this input pin.
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Section 2 CPU  Prior to executing BCLR instruction MOV.B MOV.B MOV.B #3F, R0L, R0L, R0L @RAM0 @PCR5 The PCR5 value (H'3F) is written to a work area in memory (RAM0) as well as to PCR5.
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Section 3 Exception Handling Section 3 Exception Handling Exception handling may be caused by a reset, a trap instruction (TRAPA), or interrupts. • Reset A reset has the highest exception priority. Exception handling starts as soon as the reset is cleared by the RES pin. The chip is also reset when the watchdog timer overflows, and exception handling starts. Exception handling is the same as exception handling by the RES pin.
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Section 3 Exception Handling 3.1 Exception Sources and Vector Address Table 3.1 shows the vector addresses and priority of each exception handling. When more than one interrupt is requested, handling is performed from the interrupt with the highest priority. Table 3.
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Section 3 Exception Handling Vector Number Vector Address Priority Transmit data empty Transmit end Receive data full Arbitration lost/Overrun error NACK detection Stop conditions detected 24 H'0030 to H'0031 High A/D converter A/D conversion end 25 H'0032 to H'0033 Timer Z Compare match/input capture A0 to D0 Timer Z overflow 26 H'0034 to H'0035 Compare match/input capture A1 to D1 Timer Z overflow Timer Z underflow 27 H'0036 to H'0037 Timer B1 Timer B1 overflow 29 H'003A to H'003B S
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Section 3 Exception Handling 3.2.1 Interrupt Edge Select Register 1 (IEGR1) IEGR1 selects the direction of an edge that generates interrupt requests of pins NMI and IRQ3 to IRQ0. Bit Bit Name Initial Value R/W Description 7 NMIEG 0 R/W NMI Edge Select 0: Falling edge of NMI pin input is detected 1: Rising edge of NMI pin input is detected 6 to 4  All 1  Reserved These bits are always read as 1.
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Section 3 Exception Handling 3.2.2 Interrupt Edge Select Register 2 (IEGR2) IEGR2 selects the direction of an edge that generates interrupt requests of the pins ADTRG and WKP5 to WKP0. Bit Bit Name Initial Value R/W Description 7, 6  All 1  Reserved 5 WPEG5 0 R/W WKP5 Edge Select These bits are always read as 1.
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Section 3 Exception Handling 3.2.3 Interrupt Enable Register 1 (IENR1) IENR1 enables direct transition interrupts, RTC interrupts, and external pin interrupts. Bit Bit Name Initial Value R/W Description 7 IENDT 0 R/W Direct Transfer Interrupt Enable When this bit is set to 1, direct transition interrupt requests are enabled. 6 IENTA 0 R/W RTC Interrupt Enable When this bit is set to 1, RTC interrupt requests are enabled.
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Section 3 Exception Handling 3.2.4 Interrupt Enable Register 2 (IENR2) IENR2 enables, timer B1 overflow interrupts. Bit Bit Name Initial Value R/W 7, 6  All 0  Description Reserved These bits are always read as 0. 5 IENTB1 0 R/W 4 to 0  All 1  Timer B1 Interrupt Enable When this bit is set to 1, timer B1 overflow interrupt requests are enabled. Reserved These bits are always read as 1.
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Section 3 Exception Handling Bit Bit Name Initial Value R/W Description 6 IRRTA 0 R/W RTC Interrupt Request Flag [Setting condition] When the RTC counter value overflows [Clearing condition] When IRRTA is cleared by writing 0 5, 4  All 1  Reserved These bits are always read as 1. 3 IRRI3 0 R/W IRQ3 Interrupt Request Flag [Setting condition] When IRQ3 pin is designated for interrupt input and the designated signal edge is detected.
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Section 3 Exception Handling 3.2.6 Interrupt Flag Register 2 (IRR2) IRR2 is a status flag register for timer B1 overflow interrupts. Bit Bit Name Initial Value R/W 7, 6  All 0  Description Reserved These bits are always read as 0. 5 IRRTB1 0 R/W Timer B1 Interrupt Request flag [Setting condition] When the timer B1 counter value overflows [Clearing condition] When IRRTB1 is cleared by writing 0 4 to 0  All 1  Reserved These bits are always read as 1. 3.2.
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Section 3 Exception Handling Bit Bit Name Initial Value R/W Description 3 IWPF3 0 R/W WKP3 Interrupt Request Flag [Setting condition] When WKP3 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IWPF3 is cleared by writing 0. 2 IWPF2 0 R/W WKP2 Interrupt Request Flag [Setting condition] When WKP2 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IWPF2 is cleared by writing 0.
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Section 3 Exception Handling 3.3 Reset Exception Handling When the RES pin goes low, all processing halts and this LSI enters the reset. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized by the reset. To ensure that this LSI is reset at power-up, hold the RES pin low until the clock pulse generator output stabilizes. To reset the chip during operation, hold the RES pin low for at least 10 system clock cycles.
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Section 3 Exception Handling (3) WKP5 to WKP0 Interrupts WKP5 to WKP0 interrupts are requested by input signals to pins WKP5 to WKP0. These six interrupts have the same vector addresses, and are detected individually by either rising edge sensing or falling edge sensing, depending on the settings of bits WPEG5 to WPEG0 in IEGR2.
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Section 3 Exception Handling 3.4.2 Internal Interrupts Each on-chip peripheral module has a flag to show the interrupt request status and the enable bit to enable or disable the interrupt. For RTC interrupt requests and direct transfer interrupt requests generated by execution of a SLEEP instruction, this function is included in IRR1, IRR2, IENR1, and IENR2.
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Section 3 Exception Handling SP – 4 SP (R7) CCR SP – 3 SP + 1 CCR*3 SP – 2 SP + 2 PCH SP – 1 SP + 3 PCL SP (R7) SP + 4 Even address Stack area Prior to start of interrupt exception handling PC and CCR saved to stack After completion of interrupt exception handling [Legend] PCH : Upper 8 bits of program counter (PC) PCL : Lower 8 bits of program counter (PC) CCR: Condition code register SP: Stack pointer Notes: 1.
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(2) (1) (4) Instruction prefetch (3) Internal processing (5) (1) Stack access (6) (7) (9) Vector fetch (8) (1) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.) (2)(4) Instruction code (not executed) (3) Instruction prefetch address (Instruction is not executed.
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Section 3 Exception Handling 3.5 Usage Notes 3.5.1 Interrupts after Reset If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset.
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Section 4 Address Break Section 4 Address Break The address break simplifies on-board program debugging. It requests an address break interrupt when the set break condition is satisfied. The interrupt request is not affected by the I bit of CCR. Break conditions that can be set include instruction execution at a specific address and a combination of access and data at a specific address.
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Section 4 Address Break 4.1 Register Descriptions Address break has the following registers. • • • • Address break control register (ABRKCR) Address break status register (ABRKSR) Break address register (BARH, BARL) Break data register (BDRH, BDRL) 4.1.1 Address Break Control Register (ABRKCR) ABRKCR sets address break conditions.
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Section 4 Address Break Bit Bit Name Initial Value R/W Description 1 DCMP1 0 R/W Data Compare Condition Select 1 and 0 0 DCMP0 0 R/W These bits set the comparison condition between the data set in BDR and the internal data bus. 00: No data comparison 01: Compares lower 8-bit data between BDRL and data bus 10: Compares upper 8-bit data between BDRH and data bus 11: Compares 16-bit data between BDR and data bus [Legend] X: Don't care.
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Section 4 Address Break 4.1.2 Address Break Status Register (ABRKSR) ABRKSR consists of the address break interrupt flag and the address break interrupt enable bit. Bit Bit Name Initial Value R/W Description 7 ABIF 0 R/W Address Break Interrupt Flag [Setting condition] When the condition set in ABRKCR is satisfied [Clearing condition] When 0 is written after ABIF=1 is read 6 ABIE 0 R/W Address Break Interrupt Enable When this bit is 1, an address break interrupt request is enabled.
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Section 4 Address Break 4.2 Operation When the ABIF and ABIE bits in ABRKSR are set to 1, the address break function generates an interrupt request to the CPU. The ABIF bit in ABRKSR is set to 1 by the combination of the address set in BAR, the data set in BDR, and the conditions set in ABRKCR. When the interrupt request is accepted, interrupt exception handling starts after the instruction being executed ends. The address break interrupt is not masked by the I bit in CCR of the CPU. Figures 4.
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Section 4 Address Break When the address break is specified in the data read cycle Register setting • ABRKCR = H'A0 • BAR = H'025A Program 0258 025A * 025C 0260 0262 : NOP NOP MOV.W @H'025A,R0 NOP Underline indicates the address NOP to be stacked.
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Section 5 Clock Pulse Generators Section 5 Clock Pulse Generators Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator, a duty correction circuit, and system clock dividers. The subclock pulse generator consists of a subclock oscillator circuit and a subclock divider. Figure 5.1 shows a block diagram of the clock pulse generators.
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Section 5 Clock Pulse Generators 5.1 System Clock Generator Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic resonator, or by providing external clock input. Figure 5.2 shows a block diagram of the system clock generator. OSC 2 LPM OSC 1 LPM: Low-power mode (standby mode, subactive mode, subsleep mode) Figure 5.2 Block Diagram of System Clock Generator 5.1.1 Connecting Crystal Resonator Figure 5.
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Section 5 Clock Pulse Generators Table 5.1 Crystal Resonator Parameters Frequency (MHz) 4 8 10 16 18 RS (max) 120 Ω 80 Ω 60 Ω 50 Ω 50 Ω C0 (max) 7 pF 7 pF 7 pF 7 pF 7 pF 5.1.2 Connecting Ceramic Resonator Figure 5.5 shows a typical method of connecting a ceramic resonator. C1 OSC1 C2 OSC2 C1 = 30 pF ±10% C2 = 30 pF ±10% Figure 5.5 Typical Connection to Ceramic Resonator 5.1.3 External Clock Input Method Connect an external clock signal to pin OSC1, and leave pin OSC2 open.
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Section 5 Clock Pulse Generators 5.2 Subclock Generator Figure 5.7 shows a block diagram of the subclock generator. X2 8MΩ X1 Note : Registance is a reference value. Figure 5.7 Block Diagram of Subclock Generator 5.2.1 Connecting 32.768-kHz Crystal Resonator Clock pulses can be supplied to the subclock divider by connecting a 32.768-kHz crystal resonator, as shown in figure 5.8. Figure 5.9 shows the equivalent circuit of the 32.768-kHz crystal resonator. C1 X1 C2 X2 C1 = C 2 = 15 pF (typ.
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Section 5 Clock Pulse Generators 5.2.2 Pin Connection when Not Using Subclock When the subclock is not used, connect pin X1 to VSS and leave pin X2 open, as shown in figure 5.10. X1 X2 VSS Open Figure 5.10 Pin Connection when not Using Subclock 5.3 Prescalers 5.3.1 Prescaler S Prescaler S is a 13-bit counter using the system clock (ø) as its input clock. It is incremented once per clock period. Prescaler S is initialized to H'0000 by a reset, and starts counting on exit from the reset state.
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Section 5 Clock Pulse Generators 5.4 Usage Notes 5.4.1 Note on Resonators Resonator characteristics are closely related to board design and should be carefully evaluated by the user, referring to the examples shown in this section. Resonator circuit constants will differ depending on the resonator element, stray capacitance in its interconnecting circuit, and other factors. Suitable constants should be determined in consultation with the resonator element manufacturer.
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Section 6 Power-Down Modes Section 6 Power-Down Modes This LSI has six modes of operation after a reset. These include a normal active mode and four power-down modes, in which power consumption is significantly reduced. Module standby mode reduces power consumption by selectively halting on-chip module functions. • Active mode The CPU and all on-chip peripheral modules are operable on the system clock. The system clock frequency can be selected from φosc, φosc/8, φosc/16, φosc/32, and φosc/64.
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Section 6 Power-Down Modes 6.1 Register Descriptions The registers related to power-down modes are listed below. • • • • System control register 1 (SYSCR1) System control register 2 (SYSCR2) Module standby control register 1 (MSTCR1) Module standby control register 2 (MSTCR2) 6.1.1 System Control Register 1 (SYSCR1) SYSCR1 controls the power-down modes, as well as SYSCR2.
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Section 6 Power-Down Modes Bit Bit Name Initial Value R/W Description 3 NESEL 0 R/W Noise Elimination Sampling Frequency Select The subclock pulse generator generates the watch clock signal (φW) and the system clock pulse generator generates the oscillator clock (φOSC). This bit selects the sampling frequency of the oscillator clock when the watch clock signal (φW) is sampled. When φOSC = 4 to 18 MHz, clear NESEL to 0.
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Section 6 Power-Down Modes 6.1.2 System Control Register 2 (SYSCR2) SYSCR2 controls the power-down modes, as well as SYSCR1. Bit Bit Name Initial Value R/W Description 7 SMSEL 0 R/W Sleep Mode Selection 6 LSON 0 R/W Low Speed on Flag 5 DTON 0 R/W Direct Transfer on Flag These bits select the mode to enter after the execution of a SLEEP instruction, as well as bit SSBY of SYSCR1. For details, see table 6.2.
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Section 6 Power-Down Modes 6.1.3 Module Standby Control Register 1 (MSTCR1) MSTCR1 allows the on-chip peripheral modules to enter a standby state in module units. Bit Bit Name Initial Value R/W 7  0  Description Reserved This bit is always read as 0.
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Section 6 Power-Down Modes 6.1.4 Module Standby Control Register 2 (MSTCR2) MSTCR2 allows the on-chip peripheral modules to enter a standby state in module units. Bit Bit Name Initial Value R/W Description 7 MSTS3_2 0 R/W SCI3_2 Module Standby SCI3_2 enters standby mode when this bit is set to1 6, 5  All 0  Reserved These bits are always read as 0.
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Section 6 Power-Down Modes 6.2 Mode Transitions and States of LSI Figure 6.1 shows the possible transitions among these operating modes. A transition is made from the program execution state to the program halt state by executing a SLEEP instruction. Interrupts allow for returning from the program halt state to the program execution state. A direct transition between active mode and subactive mode, which are both program execution states, can be made without halting the program.
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Section 6 Power-Down Modes Table 6.2 Transition Mode after SLEEP Instruction Execution and Transition Mode due to Interrupt DTON SSBY SMSEL LSON Transition Mode after SLEEP Instruction Execution 0 0 0 0 Sleep mode 1 1 0 Active mode Subactive mode Subsleep mode 1 1 Transition Mode due to Interrupt Active mode Subactive mode 1 X X Standby mode Active mode X 0* 0 Active mode (direct transition)  X X 1 Subactive mode (direct transition)  [Legend] X: Don’t care.
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Section 6 Power-Down Modes Table 6.
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Section 6 Power-Down Modes 6.2.1 Sleep Mode In sleep mode, CPU operation is halted but the on-chip peripheral modules function at the clock frequency set by the MA2, MA1, and MA0 bits in SYSCR2. CPU register contents are retained. When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts. Sleep mode is not cleared if the I bit of the condition code register (CCR) is set to 1 or the requested interrupt is disabled in the interrupt enable register.
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Section 6 Power-Down Modes cleared, a transition is made to active mode when the LSON bit in SYSCR2 is 0, and a transition is made to subactive mode when the bit is 1. After the time set in bits STS2 to STS0 in SYSCR1 has elapsed, a transition is made to active mode. When the RES pin goes low, the system clock pulse generator starts.
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Section 6 Power-Down Modes 6.4 Direct Transition The CPU can execute programs in two modes: active and subactive modes. A direct transition is a transition between these two modes without stopping program execution. A direct transition can be made by executing a SLEEP instruction while the DTON bit in SYSCR2 is set to 1. The direct transition also enables operating frequency modification in active or subactive mode. After the mode transition, direct transition interrupt exception handling starts.
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Section 6 Power-Down Modes 6.4.2 Direct Transition from Subactive Mode to Active Mode The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (2).
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Section 6 Power-Down Modes Rev. 2.00 Sep.
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Section 7 ROM Section 7 ROM The features of the 56-kbyte flash memories built into the flash memory (F-ZTAT) version are summarized below. • Programming/erase methods The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units. The flash memory is configured as follows: 1 kbyte × 4 blocks, 28 kbytes × 1 block, 16 kbytes × 1 block, and 8 kbytes × 1 block for H8/36087F. To erase the entire flash memory, each block must be erased in turn.
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Section 7 ROM Erase unit H'0000 H'0001 H'0002 H'0080 H'0081 H'0082 H'0380 H'0381 H'0382 H'0400 H'0401 H'0402 H'0480 H'0481 H'0481 H'0780 H'0781 H'0782 H'0800 H'0801 H'0802 H'0880 H'0881 H'0882 H'0B80 H'0B81 H'0B82 H'0C00 H'0C01 H'0C02 H'0C80 H'0C81 H'0C82 H'0F80 H'0F81 H'0F82 H'1000 H'1001 H'1002 H'1080 H'1081 H'1082 Programming unit: 128 bytes H'007F H'00FF 1 kbyte Erase unit H'03FF Programming unit: 128 bytes H'047F H'04FF 1 kbyte Erase unit H'07FF Progr
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Section 7 ROM 7.2 Register Descriptions The flash memory has the following registers. • • • • • Flash memory control register 1 (FLMCR1) Flash memory control register 2 (FLMCR2) Erase block register 1 (EBR1) Flash memory power control register (FLPWCR) Flash memory enable register (FENR) 7.2.1 Flash Memory Control Register 1 (FLMCR1) FLMCR1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode.
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Section 7 ROM Bit Bit Name Initial Value R/W Description 2 PV 0 R/W Program-Verify When this bit is set to 1, the flash memory changes to program-verify mode. When it is cleared to 0, programverify mode is cancelled. 1 E 0 R/W Erase When this bit is set to 1 while SWE=1 and ESU=1, the flash memory changes to erase mode. When it is cleared to 0, erase mode is cancelled. 0 P 0 R/W Program When this bit is set to 1 while SWE=1 and PSU=1, the flash memory changes to program mode.
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Section 7 ROM 7.2.3 Erase Block Register 1 (EBR1) EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 to be automatically cleared to 0. Bit Bit Name Initial Value R/W Description 7  0  Reserved This bit is always read as 0. 6 EB6 0 R/W When this bit is set to 1, 8 bytes of H'C000 to H'DFFF will be erased.
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Section 7 ROM 7.2.4 Flash Memory Power Control Register (FLPWCR) FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI switches to subactive mode. There are two modes: mode in which operation of the power supply circuit of flash memory is partly halted in power-down mode and flash memory can be read, and mode in which even if a transition is made to subactive mode, operation of the power supply circuit of flash memory is retained and flash memory can be read.
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Section 7 ROM 7.3 On-Board Programming Modes There are two modes for programming/erasing of the flash memory; boot mode, which enables onboard programming/erasing, and programmer mode, in which programming/erasing is performed with a PROM programmer. On-board programming/erasing can also be performed in user program mode. At reset-start in reset mode, this LSI changes to a mode depending on the TEST pin settings, NMI pin settings, and input level of each port, as shown in table 7.1.
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Section 7 ROM 7.3.1 Boot Mode Table 7.2 shows the boot mode operations between reset end and branching to the programming control program. 1. When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. Prepare a programming control program in accordance with the description in section 7.4, Flash Memory Programming/Erasing. 2. SCI3 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop bit, and no parity. 3.
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Section 7 ROM Boot Mode Operation Host Operation Communication Contents Processing Contents Transfer of number of bytes of programming control program Flash memory erase Bit rate adjustment Boot mode initiation Item Table 7.2 LSI Operation Processing Contents Branches to boot program at reset-start. Boot program initiation Continuously transmits data H'00 at specified bit rate. Transmits data H'55 when data H'00 is received error-free. H'00, H'00 . . .
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Section 7 ROM Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible Host Bit Rate System Clock Frequency Range of LSI 19,200 bps 16 to 18 MHz 9,600 bps 8 to 16 MHz 4,800 bps 4 to 16 MHz 2,400 bps 4 to 16 MHz 7.3.2 Programming/Erasing in User Program Mode On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program.
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Section 7 ROM Reset-start No Program/erase? Yes Transfer user program/erase control program to RAM Branch to flash memory application program Branch to user program/erase control program in RAM Execute user program/erase control program (flash memory rewrite) Branch to flash memory application program Figure 7.2 Programming/Erasing Flowchart Example in User Program Mode Rev. 2.00 Sep.
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Section 7 ROM 7.4 Flash Memory Programming/Erasing A software method using the CPU is employed to program and erase flash memory in the onboard programming modes. Depending on the FLMCR1 setting, the flash memory operates in one of the following four modes: Program mode, program-verify mode, erase mode, and erase-verify mode. The programming control program in boot mode and the user program/erase control program in user program mode use these operating modes in combination to perform programming/erasing.
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Section 7 ROM 8. The maximum number of repetitions of the program/program-verify sequence of the same bit is 1,000.
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Section 7 ROM Table 7.4 Reprogram Data Computation Table Program Data Verify Data Reprogram Data Comments 0 0 1 Programming completed 0 1 0 Reprogram bit 1 0 1  1 1 1 Remains in erased state Table 7.5 Additional-Program Data Computation Table Reprogram Data Verify Data Additional-Program Data Comments 0 0 0 Additional-program bit 0 1 1 No additional programming 1 0 1 No additional programming 1 1 1 No additional programming Comments Table 7.
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Section 7 ROM 7.4.2 Erase/Erase-Verify When erasing flash memory, the erase/erase-verify flowchart shown in figure 7.4 should be followed. 1. Prewriting (setting erase block data to all 0s) is not necessary. 2. Erasing is performed in block units. Make only a single-bit specification in the erase block register (EBR1). To erase multiple blocks, each block must be erased in turn. 3. The time during which the E bit is set to 1 is the flash memory erase time. 4.
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Section 7 ROM Erase start SWE bit ← 1 Wait 1 µs n←1 Set EBR1 Enable WDT ESU bit ← 1 Wait 100 µs E bit ← 1 Wait 10 ms E bit ← 0 Wait 10 µs ESU bit ← 0 10 µs Disable WDT EV bit ← 1 Wait 20 µs Set block start address as verify address H'FF dummy write to verify address Wait 2 µs * n←n+1 Read verify data No Verify data + all 1s ? Increment address Yes No Last address of block ? Yes No EV bit ← 0 EV bit ← 0 Wait 4 µs Wait 4µs All erase block erased ? n ≤100 ? Yes Yes No Yes SWE bit ← 0 SWE bi
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Section 7 ROM 7.5 Program/Erase Protection There are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 7.5.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset, subactive mode, subsleep mode, or standby mode.
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Section 7 ROM The FLMCR1, FLMCR2, and EBR1 settings are retained, however program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be reentered by re-setting the P or E bit. However, PV and EV bit settings are retained, and a transition can be made to verify mode. Error protection can be cleared only by a reset. 7.
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Section 7 ROM Table 7.7 Flash Memory Operating States Flash Memory Operating State LSI Operating State PDWND = 0 (Initial Value) PDWND = 1 Active mode Normal operating mode Normal operating mode Subactive mode Power-down mode Normal operating mode Sleep mode Normal operating mode Normal operating mode Subsleep mode Standby mode Standby mode Standby mode Standby mode Standby mode Rev. 2.00 Sep.
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Section 7 ROM Rev. 2.00 Sep.
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Section 8 RAM Section 8 RAM This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling two-state access by the CPU to both byte data and word data.
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Section 8 RAM Rev. 2.00 Sep.
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Section 9 I/O Ports Section 9 I/O Ports The group of this LSI has forty-five general I/O ports and eight general input-only ports. Port 6 is a large current port, which can drive 10 mA (@VOL = 1.0 V) when a low level signal is output. Any of these ports can become an input port immediately after a reset. They can also be used as I/O pins of the on-chip peripheral modules or external interrupt input pins, and these functions can be switched depending on the register settings.
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Section 9 I/O Ports 9.1.1 Port Mode Register 1 (PMR1) PMR1 switches the functions of pins in port 1 and port 2. Bit Bit Name Initial Value R/W Description 7 IRQ3 0 R/W This bit selects the function of pin P17/IRQ3/TRGV. 0: General I/O port 1: IRQ3/TRGV input pin 6 IRQ2 0 R/W This bit selects the function of pin P16/IRQ2. 0: General I/O port 1: IRQ2 input pin 5 IRQ1 0 R/W This bit selects the function of pin P15/IRQ1/TMIB1.
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Section 9 I/O Ports 9.1.2 Port Control Register 1 (PCR1) PCR1 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 1. Bit Bit Name Initial Value R/W Description 7 PCR17 0 W 6 PCR16 0 W 5 PCR15 0 W When the corresponding pin is designated in PMR1 as a general I/O pin, setting a PCR1 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. 4 PCR14 0 W Bit 3 is a reserved bit.
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Section 9 I/O Ports 9.1.4 Port Pull-Up Control Register 1 (PUCR1) PUCR1 controls the pull-up MOS in bit units of the pins set as the input ports. Bit Bit Name Initial Value R/W Description 7 PUCR17 0 R/W 6 PUCR16 0 R/W 5 PUCR15 0 R/W Only bits for which PCR1 is cleared are valid. The pull-up MOS of P17 to P14 and P12 to P10 pins enter the onstate when these bits are set to 1, while they enter the off-state when these bits are cleared to 0. 4 PUCR14 0 R/W Bit 3 is a reserved bit.
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Section 9 I/O Ports • P16/IRQ2 pin Register PMR1 PCR1 Bit Name IRQ2 PCR16 Pin Function Setting value 0 0 P16 input pin 1 P16 output pin X IRQ2 input pin 1 [Legend] X: Don't care. • P15/IRQ1/TMIB1 pin Register PMR1 PCR1 Bit Name IRQ1 PCR15 Pin Function Setting value 0 0 P15 input pin 1 P15 output pin X IRQ1 input/TMIB1 input pin 1 [Legend] X: Don't care.
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Section 9 I/O Ports • P11/PWM pin Register PMR1 PCR1 Bit Name PWM PCR11 Pin Function Setting value 0 0 P11 input pin 1 P11 output pin X PWM output pin 1 [Legend] X: Don't care. • P10/TMOW pin Register PMR1 PCR1 Bit Name TMOW PCR10 Pin Function Setting value 0 0 P10 input pin 1 P10 output pin X TMOW output pin 1 [Legend] X: Don't care. Rev. 2.00 Sep.
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Section 9 I/O Ports 9.2 Port 2 Port 2 is a general I/O port also functioning as SCI3 I/O pins. Each pin of the port 2 is shown in figure 9.2. The register settings of PMR1and SCI3 have priority for functions of the pins for both uses. P24 P23 Port 2 P22/TXD P21/RXD P20/SCK3 Figure 9.2 Port 2 Pin Configuration Port 2 has the following registers. • Port control register 2 (PCR2) • Port data register 2 (PDR2) • Port mode register 3 (PMR3) 9.2.
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Section 9 I/O Ports 9.2.2 Port Data Register 2 (PDR2) PDR2 is a general I/O port data register of port 2. Bit Bit Name Initial Value R/W Description 7 to 5  All 1  Reserved These bits are always read as 1. 4 P24 0 R/W PDR2 stores output data for port 2 pins. 3 P23 0 R/W 2 P22 0 R/W 1 P21 0 R/W If PDR2 is read while PCR2 bits are set to 1, the value stored in PDR2 is read.
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Section 9 I/O Ports 9.2.4 Pin Functions The correspondence between the register specification and the port functions is shown below.
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Section 9 I/O Ports • P20/SCK3 pin Register SCR3 Bit Name CKE1 Setting Value 0 SMR PCR2 CKE0 COM PCR20 Pin Function 0 0 0 P20 input pin 1 P20 output pin 0 0 1 X SCK3 output pin 0 1 X X SCK3 output pin 1 X X X SCK3 input pin [Legend] X: Don't care. 9.3 Port 3 Port 3 is a general I/O port. Each pin of the port 3 is shown in figure 9.3. P37 P36 P35 Port 3 P34 P33 P32 P31 P30 Figure 9.3 Port 3 Pin Configuration Port 3 has the following registers.
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Section 9 I/O Ports 9.3.1 Port Control Register 3 (PCR3) PCR3 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 3. Bit Bit Name Initial Value R/W Description 7 PCR37 0 W 6 PCR36 0 W 5 PCR35 0 W Setting a PCR3 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. 4 PCR34 0 W 3 PCR33 0 W 2 PCR32 0 W 1 PCR31 0 W 0 PCR30 0 W 9.3.
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Section 9 I/O Ports 9.3.3 Pin Functions The correspondence between the register specification and the port functions is shown below.
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Section 9 I/O Ports • P32 pin Register PCR3 Bit Name PCR32 Pin Function Setting Value 0 P32 input pin 1 P32 output pin • P31 pin Register PCR3 Bit Name PCR31 Pin Function Setting Value 0 P31 input pin 1 P31 output pin • P30 pin Register PCR3 Bit Name PCR30 Pin Function Setting Value 0 P30 input pin 1 P30 output pin Rev. 2.00 Sep.
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Section 9 I/O Ports 9.4 Port 5 Port 5 is a general I/O port also functioning as an I2C bus interface I/O pin, an A/D trigger input pin, and wakeup interrupt input pin. Each pin of the port 5 is shown in figure 9.4. The register setting of the I2C bus interface register has priority for functions of the pins P57/SCL and P56/SDA.
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Section 9 I/O Ports 9.4.1 Port Mode Register 5 (PMR5) PMR5 switches the functions of pins in port 5. Bit Bit Name Initial Value R/W Description 7 POF57 0 R/W 6 POF56 0 R/W When the bit is set to 1, the corresponding pin is cut off by PMOS and it functions as the NMOS open-drain output. When cleared to 0, the pin functions as the CMOS output. 5 WKP5 0 R/W This bit selects the function of pin P55/WKP5/ADTRG.
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Section 9 I/O Ports 9.4.2 Port Control Register 5 (PCR5) PCR5 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 5. Bit Bit Name Initial Value R/W Description 7 PCR57 0 W 6 PCR56 0 W 5 PCR55 0 W When each of the port 5 pins P57 to P50 functions as a general I/O port, setting a PCR5 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port.
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Section 9 I/O Ports 9.4.4 Port Pull-Up Control Register 5 (PUCR5) PUCR5 controls the pull-up MOS in bit units of the pins set as the input ports. Bit Bit Name Initial Value R/W 7, 6  All 0  Description Reserved These bits are always read as 0. 5 PUCR55 0 R/W 4 PUCR54 0 R/W 3 PUCR53 0 R/W 2 PUCR52 0 R/W 1 PUCR51 0 R/W 0 PUCR50 0 R/W 9.4.5 Pin Functions Only bits for which PCR5 is cleared are valid.
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Section 9 I/O Ports • P56/SDA pin Register ICCR1 PCR5 Bit Name ICE PCR56 Pin Function Setting Value 0 0 P56 input pin 1 P56 output pin X SDA I/O pin 1 [Legend] X: Don't care. SDA performs the NMOS open-drain output, that enables a direct bus drive. • P55/WKP5/ADTRG pin Register PMR5 PCR5 Bit Name WKP5 PCR55 Pin Function Setting Value 0 0 P55 input pin 1 P55 output pin X WKP5/ADTRG input pin 1 [Legend] X: Don't care.
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Section 9 I/O Ports • P53/WKP3 pin Register PMR5 PCR5 Bit Name WKP3 PCR53 Pin Function Setting Value 0 0 P53 input pin 1 P53 output pin X WKP3 input pin 1 [Legend] X: Don't care. • P52/WKP2 pin Register PMR5 PCR5 Bit Name WKP2 PCR52 Pin Function Setting Value 0 0 P52 input pin 1 P52 output pin X WKP2 input pin 1 [Legend] X: Don't care.
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Section 9 I/O Ports • P50/WKP0 pin Register PMR5 PCR5 Bit Name WKP0 PCR50 Pin Function Setting Value 0 0 P50 input pin 1 P50 output pin X WKP0 input pin 1 [Legend] X: Don't care. 9.5 Port 6 Port 6 is a general I/O port also functioning as a timer Z I/O pin. Each pin of the port 6 is shown in figure 9.5. The register setting of the timer Z has priority for functions of the pins for both uses.
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Section 9 I/O Ports 9.5.1 Port Control Register 6 (PCR6) PCR6 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 6. Bit Bit Name Initial Value R/W Description 7 PCR67 0 W 6 PCR66 0 W 5 PCR65 0 W When each of the port 6 pins P67 to P60 functions as a general I/O port, setting a PCR6 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port.
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Section 9 I/O Ports 9.5.3 Pin Functions The correspondence between the register specification and the port functions is shown below. • P67/FTIOD1 pin Register Bit Name TOER TFCR TPMR ED1 CMD1 and CMD0 IOD2 to PWMD1 IOD0 PCR67 Pin Function 00 0 0 P67 input/FTIOD1 input pin 1 P67 output pin X FTIOD1 output pin Setting Value 1 0 00 Other than 00 TIORC1 000 or 1XX 0 001 or 01X 1 XXX X XXX PCR6 [Legend] X: Don't care.
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Section 9 I/O Ports • P65/FTIOB1 pin Register TOER TFCR Bit Name EB1 Setting Value 1 0 TPMR TIORA1 PCR6 CMD1 to CMD0 PWMB1 IOB2 to IOB0 PCR65 Pin Function 00 000 or 1XX 0 P65 input/FTIOB1 input pin 1 P65 output pin X FTIOB1 output pin 0 00 Other than 00 0 001 or 01X 1 XXX X XXX [Legend] X: Don't care.
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Section 9 I/O Ports • P63/FTIOD0 pin Register TOER TFCR Bit Name ED0 Setting Value 1 0 TIORC0 PCR6 CMD1 to CMD0 PWMD0 IOD2 to IOD0 PCR63 Pin Function 00 000 or 1XX 0 P63 input/FTIOD0 input pin 1 P63 output pin X FTIOD0 output pin 00 TPMR 0 0 001 or 01X 1 XXX Other than 00 X XXX TPMR TIORC0 PCR6 [Legend] X: Don't care.
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Section 9 I/O Ports • P61/FTIOB0 pin Register TOER TFCR Bit Name EB0 CMD1 to IOB2 to CMD0 PWMB0 IOB0 PCR61 Pin Function 00 0 P61 input/FTIOB0 input pin 1 P61 output pin X FTIOB0 output pin Setting Value 1 0 00 TPMR 0 TIORA0 000 or 1XX PCR6 0 001 or 01X 1 XXX Other than 00 X XXX TFCR TIORA0 PCR6 PCR60 Pin Function [Legend] X: Don't care.
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Section 9 I/O Ports 9.6 Port 7 Port 7 is a general I/O port also functioning as a timer V I/O pin and SCI3_2 I/O pin. Each pin of the port 7 is shown in figure 9.6. The register settings of the timer V and SCI3_2 have priority for functions of the pins for both uses. P76/TMOV P75/TMCIV P74/TMRIV Port 7 P72/TXD_2 P71/RXD_2 P70/SCK3_2 Figure 9.6 Port 7 Pin Configuration Port 7 has the following registers. • Port control register 7 (PCR7) • Port data register 7 (PDR7) 9.6.
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Section 9 I/O Ports 9.6.2 Port Data Register 7 (PDR7) PDR7 is a general I/O port data register of port 7. Bit Bit Name Initial Value R/W Description 7  1  Stores output data for port 7 pins. 6 P76 0 R/W 5 P75 0 R/W 4 P74 0 R/W If PDR7 is read while PCR7 bits are set to 1, the value stored in PDR7 are read. If PDR7 is read while PCR7 bits are cleared to 0, the pin states are read regardless of the value stored in PDR7. 3  1  2 P72 0 R/W 1 P71 0 R/W 0 P70 0 R/W 9.
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Section 9 I/O Ports • P74/TMRIV pin Register PCR7 Bit Name PCR74 Pin Function Setting Value 0 P74 input/TMRIV input pin 1 P74 output/TMRIV input pin • P72/TXD_2 pin Register PMR1 PCR7 Bit Name TXD2 PCR72 Pin Function Setting Value 0 0 P72 input pin 1 P72 output pin X TXD_2 output pin 1 [Legend] X: Don't care.
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Section 9 I/O Ports 9.7 Port 8 Port 8 is a general I/O port. Each pin of the port 8 is shown in figure 9.7. P87 Port 8 P86 P85 Figure 9.7 Port 8 Pin Configuration Port 8 has the following registers. • Port control register 8 (PCR8) • Port data register 8 (PDR8) 9.7.1 Port Control Register 8 (PCR8) PCR8 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 8.
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Section 9 I/O Ports 9.7.2 Port Data Register 8 (PDR8) PDR8 is a general I/O port data register of port 8. Bit Bit Name Initial Value R/W Description 7 P87 0 R/W PDR8 stores output data for port 8 pins. 6 P86 0 R/W 5 P85 0 R/W If PDR8 is read while PCR8 bits are set to 1, the value stored in PDR8 is read. If PDR8 is read while PCR8 bits are cleared to 0, the pin states are read regardless of the value stored in PDR8. 4 to 0  All 1  Reserved These bits are always read as 1. 9.7.
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Section 9 I/O Ports 9.8 Port B Port B is an input port also functioning as an A/D converter analog input pin. Each pin of the port B is shown in figure 9.8. PB7/AN7 PB6/AN6 PB5/AN5 Port B PB4/AN4 PB3/AN3 PB2/AN2 PB1/AN1 PB0/AN0 Figure 9.8 Port B Pin Configuration Port B has the following register. • Port data register B (PDRB) 9.8.1 Port Data Register B (PDRB) PDRB is a general input-only port data register of port B.
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Section 9 I/O Ports Rev. 2.00 Sep.
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Section 10 Realtime Clock (RTC) Section 10 Realtime Clock (RTC) The realtime clock (RTC) is a timer used to count time ranging from a second to a week. Figure 10.1 shows the block diagram of the RTC. 10.
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Section 10 Realtime Clock (RTC) RTCCSR PSS RSECDR 1/4 RMINDR RHRDR TMOW Clock count control circuit RWKDR Internal data bus 32-kHz oscillator circuit RTCCR1 RTCCR2 Interrupt control circuit [Legend] RTCCSR: Clock source select register RSECDR: Second date register/free running counter data register RMINDR: Minute date register RHRDR: Hour date register RWKDR: Day-of-week date register RTCCR1: RTC control register 1 RTCCR2: RTC control register 2 PSS: Prescaler S Figure 10.
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Section 10 Realtime Clock (RTC) 10.2 Input/Output Pin Table 10.1 shows the RTC input/output pin. Table 10.1 Pin Configuration Name Abbreviation I/O Function Clock output TMOW RTC divided clock output 10.3 Output Register Descriptions The RTC has the following registers.
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Section 10 Realtime Clock (RTC) Bit Bit Name Initial Value R/W Description 3 SC03 — R/W Counting one’s position of seconds 2 SC02 — R/W 1 SC01 — R/W Counts on 0 to 9 once per second. When a carry is generated, 1 is added to the ten’s position. 0 SC00 — R/W 10.3.2 Minute Data Register (RMINDR) RMINDR counts the BCD-coded minute value on the carry generated once per minute by the RSECDR counting. The setting range is decimal 00 to 59.
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Section 10 Realtime Clock (RTC) 10.3.3 Hour Data Register (RHRDR) RHRDR counts the BCD-coded hour value on the carry generated once per hour by RMINDR. The setting range is either decimal 00 to 11 or 00 to 23 by the selection of the 12/24 bit in RTCCR1. Bit Bit Name Initial Value R/W Description 7 BSY — R RTC busy This bit is set to 1 when the RTC is updating (operating) the values of second, minute, hour, and day-of-week data registers.
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Section 10 Realtime Clock (RTC) 10.3.4 Day-of-Week Data Register (RWKDR) RWKDR counts the BCD-coded day-of-week value on the carry generated once per day by RHRDR. The setting range is decimal 0 to 6 using bits WK2 to WK0. Bit Bit Name Initial Value R/W Description 7 BSY — R RTC busy This bit is set to 1 when the RTC is updating (operating) the values of second, minute, hour, and day-of-week data registers.
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Section 10 Realtime Clock (RTC) 10.3.5 RTC Control Register 1 (RTCCR1) RTCCR1 controls start/stop and reset of the clock timer. For the definition of time expression, see figure 10.2. Bit Bit Name Initial Value R/W Description 7 RUN — R/W RTC operation start 0: Stops RTC operation 1: Starts RTC operation 6 12/24 — R/W Operating mode 0: RTC operates in 12-hour mode. RHRDR counts on 0 to 11. 1: RTC operates in 24-hour mode. RHRDR counts on 0 to 23. 5 PM — R/W A.m./p.m. 0: Indicates a.m.
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Section 10 Realtime Clock (RTC) 10.3.6 RTC Control Register 2 (RTCCR2) RTCCR2 controls RTC periodic interrupts of weeks, days, hours, minutes, and seconds. Enabling interrupts of weeks, days, hours, minutes, and seconds sets the IRRTA flag to 1 in the interrupt flag register 1 (IRR1) when an interrupt occurs. It also controls an overflow interrupt of a free running counter when RTC operates as a free running counter.
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Section 10 Realtime Clock (RTC) 10.3.7 Clock Source Select Register (RTCCSR) RTCCSR selects clock source. A free running counter controls start/stop of counter operation by the RUN bit in RTCCR1. When a clock other than 32.768 kHz is selected, the RTC is disabled and operates as an 8-bit free running counter. When the RTC operates as an 8-bit free running counter, RSECDR enables counter values to be read.
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Section 10 Realtime Clock (RTC) 10.4 Operation 10.4.1 Initial Settings of Registers after Power-On The RTC registers that store second, minute, hour, and day-of week data are not reset by a RES input. Therefore, all registers must be set to their initial values after power-on. Once the register setting are made, the RTC provides an accurate time as long as power is supplied regardless of a RES input. 10.4.2 Initial Setting Procedure Figure 10.3 shows the procedure for the initial setting of the RTC.
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Section 10 Realtime Clock (RTC) 10.4.3 Data Reading Procedure When the seconds, minutes, hours, or day-of-week datum is updated while time data is being read, the data obtained may not be correct, and so the time data must be read again. Figure 10.4 shows an example in which correct data is not obtained. In this example, since only RSECDR is read after data update, about 1-minute inconsistency occurs. To avoid reading in this timing, the following processing must be performed. 1.
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Section 10 Realtime Clock (RTC) 10.5 Interrupt Source There are five kinds of RTC interrupts: week interrupts, day interrupts, hour interrupts, minute interrupts, and second interrupts. When using an interrupt, initiate the RTC last after other registers are set. Do not set multiple interrupt enable bits in RTCCR2 simultaneously to 1. When an interrupt request of the RTC occurs, the IRRTA flag in IRR1 is set to 1. When clearing the flag, write 0. Table 10.
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Section 11 Timer B1 Section 11 Timer B1 Timer B1 is an 8-bit timer that increments each time a clock pulse is input. This timer has two operating modes, interval and auto reload. Figure 11.1 shows a block diagram of timer B1. 11.1 Features • Selection of seven internal clock sources (φ/8192, φ/2048, φ/512, φ/256, φ/64, φ/16, and φ/4) or an external clock (can be used to count external events). • An interrupt is generated when the counter overflows.
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Section 11 Timer B1 11.2 Input/Output Pin Table 11.1 shows the timer B1 pin configuration. Table 11.1 Pin Configuration Name Abbreviation I/O Function Timer B1 event input TMIB1 Input Event input to TCB1 11.3 Register Descriptions The timer B1 has the following registers. • Timer mode register B1 (TMB1) • Timer counter B1 (TCB1) • Timer load register B1 (TLB1) 11.3.1 Timer Mode Register B1 (TMB1) TMB1 selects the auto-reload function and input clock.
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Section 11 Timer B1 Bit Bit Name Initial Value R/W Description 2 TMB12 0 R/W Clock select 1 TMB11 0 R/W 000: Internal clock: φ/8192 0 TMB10 0 R/W 001: Internal clock: φ/2048 010: Internal clock: φ/512 011: Internal clock: φ/256 100: Internal clock: φ/64 101: Internal clock: φ/16 110: Internal clock: φ/4 111: External event (TMIB1): rising or falling edge* Note: * The edge of the external event signal is selected by bit IEG1 in the interrupt edge select register 1 (IEGR1). See section 3.
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Section 11 Timer B1 11.4 Operation 11.4.1 Interval Timer Operation When bit TMB17 in TMB1 is cleared to 0, timer B1 functions as an 8-bit interval timer. Upon reset, TCB1 is cleared to H'00 and bit TMB17 is cleared to 0, so up-counting and interval timing resume immediately. The operating clock of timer B1 is selected from seven internal clock signals output by prescaler S, or an external clock input at pin TMB1. The selection is made by bits TMB12 to TMB10 in TMB1.
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Section 11 Timer B1 11.5 Timer B1 Operating Modes Table 11.2 shows the timer B1 operating modes. Table 11.2 Timer B1 Operating Modes Operating Mode Reset Active TCB1 TMB1 Interval Sleep Subactive Subsleep Standby Reset Functions Functions Halted Halted Halted Auto-reload Reset Functions Functions Halted Halted Halted Reset Functions Retained Retained Retained Retained Rev. 2.00 Sep.
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Section 11 Timer B1 Rev. 2.00 Sep.
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Section 12 Timer V Section 12 Timer V Timer V is an 8-bit timer based on an 8-bit counter. Timer V counts external events. Comparematch signals with two registers can also be used to reset the counter, request an interrupt, or output a pulse signal with an arbitrary duty cycle. Counting can be initiated by a trigger input at the TRGV pin, enabling pulse output control to be synchronized to the trigger, with an arbitrary delay from the trigger input. Figure 12.1 shows a block diagram of timer V. 12.
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Section 12 Timer V TCRV1 TCORB Trigger control TRGV Comparator TCNTV Internal data bus Clock select TMCIV Comparator φ PSS TCORA TMRIV Clear control TCRV0 Interrupt request control TMOV Output control TCSRV [Legend] TCORA: Time constant register A TCORB: Time constant register B TCNTV: Timer counter V TCSRV: Timer control/status register V TCRV0: Timer control register V0 TCRV1: Timer control register V1 PSS: Prescaler S CMIA: Compare-match interrupt A CMIB: Compare-match interrupt B OVI: O
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Section 12 Timer V 12.2 Input/Output Pins Table 12.1 shows the timer V pin configuration. Table 12.1 Pin Configuration Name Abbreviation I/O Function Timer V output TMOV Output Timer V waveform output Timer V clock input TMCIV Input Clock input to TCNTV Timer V reset input TMRIV Input External input to reset TCNTV Trigger input TRGV Input Trigger input to initiate counting 12.3 Register Descriptions Time V has the following registers.
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Section 12 Timer V 12.3.2 Time Constant Registers A and B (TCORA, TCORB) TCORA and TCORB have the same function. TCORA and TCORB are 8-bit read/write registers. TCORA and TCNTV are compared at all times. When the TCORA and TCNTV contents match, CMFA is set to 1 in TCSRV. If CMIEA is also set to 1 in TCRV0, a CPU interrupt is requested. Note that they must not be compared during the T3 state of a TCORA write cycle.
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Section 12 Timer V Bit Bit Name Initial Value R/W Description 4 CCLR1 0 R/W Counter Clear 1 and 0 3 CCLR0 0 R/W These bits specify the clearing conditions of TCNTV. 00: Clearing is disabled 01: Cleared by compare match A 10: Cleared by compare match B 11: Cleared on the rising edge of the TMRIV pin. The operation of TCNTV after clearing depends on TRGE in TCRV1.
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Section 12 Timer V 12.3.4 Timer Control/Status Register V (TCSRV) TCSRV indicates the status flag and controls outputs by using a compare match.
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Section 12 Timer V Bit Bit Name Initial Value R/W Description 1 OS1 0 R/W Output Select 1 and 0 0 OS0 0 R/W These bits select an output method for the TMOV pin by the compare match of TCORA and TCNTV. 00: No change 01: 0 output 10: 1 output 11: Output toggles OS3 and OS2 select the output level for compare match B. OS1 and OS0 select the output level for compare match A. The two output levels can be controlled independently. After a reset, the timer output is 0 until the first compare match.
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Section 12 Timer V Bit Bit Name Initial Value R/W Description 1  1  Reserved This bit is always read as 1. 0 ICKS0 0 R/W Internal Clock Select 0 This bit selects clock signals to input to TCNTV in combination with CKS2 to CKS0 in TCRV0. Refer to table 12.2. 12.4 Operation 12.4.1 Timer V Operation 1. According to table 12.2, six internal/external clock signals output by prescaler S can be selected as the timer V operating clock signals.
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Section 12 Timer V φ Internal clock TCNTV input clock TCNTV N–1 N N+1 Figure 12.2 Increment Timing with Internal Clock φ TMCIV (External clock input pin) TCNTV input clock TCNTV N–1 N N+1 Figure 12.3 Increment Timing with External Clock φ TCNTV H'FF H'00 Overflow signal OVF Figure 12.4 OVF Set Timing Rev. 2.00 Sep.
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Section 12 Timer V φ TCNTV N TCORA or TCORB N N+1 Compare match signal CMFA or CMFB Figure 12.5 CMFA and CMFB Set Timing φ Compare match A signal Timer V output pin Figure 12.6 TMOV Output Timing φ Compare match A signal TCNTV N H'00 Figure 12.7 Clear Timing by Compare Match Rev. 2.00 Sep.
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Section 12 Timer V φ TMRIV (External counter reset input pin) TCNTV reset signal N–1 TCNTV N H'00 Figure 12.8 Clear Timing by TMRIV Input 12.5 Timer V Application Examples 12.5.1 Pulse Output with Arbitrary Duty Cycle Figure 12.9 shows an example of output of pulses with an arbitrary duty cycle. 1. Set bits CCLR1 and CCLR0 in TCRV0 so that TCNTV will be cleared by compare match with TCORA. 2.
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Section 12 Timer V 12.5.2 Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input The trigger function can be used to output a pulse with an arbitrary pulse width at an arbitrary delay from the TRGV input, as shown in figure 12.10. To set up this output: 1. Set bits CCLR1 and CCLR0 in TCRV0 so that TCNTV will be cleared by compare match with TCORB. 2. Set bits OS3 to OS0 in TCSRV so that the output will go to 1 at compare match with TCORA and to 0 at compare match with TCORB. 3.
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Section 12 Timer V 12.6 Usage Notes The following types of contention or operation can occur in timer V operation. 1. 2. 3. 4. Writing to registers is performed in the T3 state of a TCNTV write cycle. If a TCNTV clear signal is generated in the T3 state of a TCNTV write cycle, as shown in figure 12.11, clearing takes precedence and the write to the counter is not carried out. If counting-up is generated in the T3 state of a TCNTV write cycle, writing takes precedence.
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Section 12 Timer V TCORA write cycle by CPU T2 T1 T3 φ Address TCORA address Internal write signal TCNTV N N+1 TCORA N M TCORA write data Compare match signal Inhibited Figure 12.12 Contention between TCORA Write and Compare Match Clock before switching Clock after switching Count clock TCNTV N N+1 N+2 Write to CKS1 and CKS0 Figure 12.13 Internal Clock Switching and TCNTV Operation Rev. 2.00 Sep.
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Section 13 Timer Z Section 13 Timer Z The timer Z has a 16-bit timer with two channels. Figures 13.1, 13.2, and 13.3 show the block diagrams of entire timer Z, its channel 0, and its channel 1, respectively. For details on the timer Z functions, refer to table 13.1. 13.
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Section 13 Timer Z • Eleven interrupt sources  Four compare match/input capture interrupts and an overflow interrupt are available for each channel. An underflow interrupt can be set for channel 1. Table 13.
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Section 13 Timer Z ITMZ0 FTIOA0 ITMZ1 FTIOB0 FTIOC0 FTIOD0 Control logic FTIOA1 FTIOB1 FTIOC1 FTIOD1 φ, φ/2, φ/4, φ/8 ADTRG Channel 0 timer Channel 1 timer TSTR TMDR TPMR TFCR TOER TOCR Module data bus [Legend] TSTR: Timer start register (8 bits) TMDR: Timer mode register (8 bits) TPMR: Timer PWM mode register (8 bits) TFCR: Timer function control register (8 bits) TOER: Timer output master enable register (8 bits) TOCR: Timer output control register (8 bits) ADTRG: A/D conversion star
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Section 13 Timer Z FTIOA0 FTIOB0 φ, φ/2, φ/4, φ/8 FTIOC0 Clock select FTIOD0 Control logic ITMZ0 Module data bus [Legend] TCNT_0: Timer counter_0 (16 bits) GRA_0, GRB_0: General registers A_0, B_0, C_0, and D_0 (input capture/output compare registers: GRC_0, GRD_0 : 16 bits × 4) TCR_0: Timer control register_0 (8 bits) TIORA_0: Timer I/O control register A_0 (8 bits) TIORC_0: Timer I/O control register C_0 (8 bits) TSR_0: Timer status register_0 (8 bits) TIER_0: Timer interrupt enable register_0 (8
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Section 13 Timer Z FTIOA1 FTIOB1 φ, φ/2, φ/4, φ/8 FTIOC1 Clock select FTIOD1 Control logic ITMZ1 POCR_1 TIER_1 TSR_1 TIORC_1 TIORA_1 TCR_1 GRD_1 GRC_1 GRB_1 GRA_1 TCNT_1 Comparator Module data bus [Legend] TCNT_1: GRA_1, GRB_1: GRC_1, GRD_1: TCR_1: TIORA_1: TIORC_1: TSR_1: TIER_1: POCR_1: ITMZ1: Timer counter_1 (16 bits) General registers A_1, B_1, C_1, and D_1 (input capture/output compare registers: 16 bits × 4) Timer control register_1 (8 bits) Timer I/O control register A_1 (8 bits
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Section 13 Timer Z 13.2 Input/Output Pins Table 13.2 summarizes the timer Z pins. Table 13.
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Section 13 Timer Z 13.3 Register Descriptions The timer Z has the following registers.
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Section 13 Timer Z • General register C_1 (GRC_1) • General register D_1 (GRD_1) 13.3.1 Timer Start Register (TSTR) TSTR selects the operation/stop for the TCNT counter. Bit Bit Name Initial Value R/W Description 7 to 2  All 1  Reserved These bits are always read as 1, and cannot be modified. 1 STR1 0 R/W Channel 1 Counter Start 0: TCNT_1 halts counting 1: TCNT_1 starts counting 0 STR0 0 R/W Channel 0 Counter Start 0: TCNT_0 halts counting 1: TCNT_0 starts counting 13.3.
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Section 13 Timer Z Bit Bit Name Initial Value R/W Description 4 BFC0 0 R/W Buffer Operation C0 0: GRC_0 operates normally 1: GRA_0 and GRC_0 are used together for buffer operation 3 to 1  All 1  Reserved These bits are always read as 1, and cannot be modified. 0 SYNC 0 R/W Timer Synchronization 0: TCNT_1 and TCNT_0 operate as a different timer 1: TCNT_1 and TCNT_0 are synchronized TCNT_1 and TCNT_0 can be pre-set or cleared synchronously 13.3.
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Section 13 Timer Z Bit Bit Name Initial Value R/W Description 2 PWMD0 0 R/W PWM Mode D0 0: FTIOD0 operates normally 1: FTIOD0 operates in PWM mode 1 PWMC0 0 R/W PWM Mode C0 0: FTIOC0 operates normally 1: FTIOC0 operates in PWM mode 0 PWMB0 0 R/W PWM Mode B0 0: FTIOB0 operates normally 1: FTIOB0 operates in PWM mode 13.3.4 Timer Function Control Register (TFCR) TFCR selects the settings and output levels for each operating mode.
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Section 13 Timer Z Bit Bit Name Initial Value R/W Description 3 OLS1 0 R/W Output Level Select 1 Selects the counter-phase output levels in reset synchronous PWM mode or complementary PWM mode. 0: Initial output is high and the active level is low. 1: Initial output is low and the active level is high. 2 OLS0 0 R/W Output Level Select 0 Selects the normal-phase output levels in reset synchronous PWM mode or complementary PWM mode. 0: Initial output is high and the active level is low.
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Section 13 Timer Z TCNT_0 TCNT_1 Normal phase Normal phase Active level Active level Counter phase Counter phase Initial output Active level Reset synchronous PWM mode Initial output Active level Complementary PWM mode Note: Write H'00 to TOCR to start initial outputs after stopping the counter. Figure 13.4 Example of Outputs in Reset Synchronous PWM Mode and Complementary PWM Mode Rev. 2.00 Sep.
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Section 13 Timer Z 13.3.5 Timer Output Master Enable Register (TOER) TOER enables/disables the outputs for channel 0 and channel 1. When WKP4 is selected for inputs, if a low level signal is input to WKP4, the bits in TOER are set to 1 to disable the output for timer Z.
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Section 13 Timer Z Bit Bit Name Initial Value R/W Description 2 EC0 1 R/W Master Enable C0 0: FTIOC0 pin output is enabled according to the TPMR, TFCR, and TIORC_0 settings 1: FTIOC0 pin output is disabled regardless of the TPMR, TFCR, and TIORC_0 settings (FTIOC0 pin is operated as an I/O port).
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Section 13 Timer Z Bit Bit Name Initial Value R/W Description 5 TOB1 0 R/W Output Level Select B1 0: 0 output at the FTIOB1 pin* 1: 1 output at the FTIOB1 pin* 4 TOA1 0 R/W Output Level Select A1 0: 0 output at the FTIOA1 pin* 1: 1 output at the FTIOA1 pin* 3 TOD0 0 R/W Output Level Select D0 0: 0 output at the FTIOD0 pin* 1: 1 output at the FTIOD0 pin* 2 TOC0 0 R/W Output Level Select C0 0: 0 output at the FTIOC0 pin* 1: 1 output at the FTIOC0 pin* 1 TOB0 0 R/W Output Level Se
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Section 13 Timer Z 13.3.8 General Registers A, B, C, and D (GRA, GRB, GRC, and GRD) GR are 16-bit registers. Timer Z has eight general registers (GR), four for each channel. The GR registers are dual function 16-bit readable/writable registers, functioning as either output compare or input capture registers. Functions can be switched by TIORA and TIORC. The values in GR and TCNT are constantly compared with each other when the GR registers are used as output compare registers.
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Section 13 Timer Z 13.3.9 Timer Control Register (TCR) The TCR registers select a TCNT counter clock, an edge when an external clock is selected, and counter clearing sources. Timer Z has a total of two TCR registers, one for each channel.
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Section 13 Timer Z 13.3.10 Timer I/O Control Register (TIORA and TIORC) The TIOR registers control the general registers (GR). Timer Z has four TIOR registers (TIORA_0, TIORA_1, TIORC_0, and TIORC_1), two for each channel. In PWM mode including complementary PWM mode and reset synchronous PWM mode, the settings of TIOR are invalid. • TIORA TIORA selects whether GRA or GRB is used as an output compare register or an input capture register.
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Section 13 Timer Z Bit Bit Name Initial value R/W Description 2 IOA2 0 R/W I/O Control A2 to A0 1 IOA1 0 R/W GRA is an output compare register: 0 IOA0 0 R/W 000: Disables pin output by compare match 001: 0 output by GRA compare match 010: 1 output by GRA compare match 011: Toggle output by GRA compare match GRA is an input capture register: 100: Input capture to GRA at the rising edge 101: Input capture to GRA at the falling edge 11X: Input capture to GRA at both rising and falling edges
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Section 13 Timer Z Bit Bit Name Initial value R/W Description 3  1  Reserved 2 IOC2 0 R/W I/O Control C2 to C0 1 IOC1 0 R/W GRC is an output compare register: 0 IOC0 0 R/W 000: Disables pin output by compare match This bit is always read as 1.
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Section 13 Timer Z Bit Bit Name Initial value R/W Description 4 OVF 0 R/W Overflow Flag [Setting condition] • When the TCNT value underflows [Clearing condition] • 3 IMFD 0 R/W When 0 is written to OVF after reading OVF = 1 Input Capture/Compare Match Flag D [Setting conditions] • When TCNT = GRD and GRD is functioning as output compare register • When TCNT value is transferred to GRD by input capture signal and GRD is functioning as input capture register [Clearing condition] • 2 IMFC
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Section 13 Timer Z Bit Bit Name Initial value R/W Description 0 IMFA 0 R/W Input Capture/Compare Match Flag A [Setting conditions] • When TCNT = GRA and GRA is functioning as output compare register • When TCNT value is transferred to GRA by input capture signal and GRA is functioning as input capture register [Clearing condition] • When 0 is written to IMFA after reading IMFA = 1 Note: Bit 5 is not the UDF flag in TSR_0. It is a reserved bit. It is always read as 1. 13.3.
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Section 13 Timer Z Bit Bit Name Initial value R/W Description 1 IMIEB 0 R/W Input Capture/Compare Match Interrupt Enable B 0: Interrupt requests (IMIB) by IMFB flag are disabled 1: Interrupt requests (IMIB) by IMFB flag are enabled 0 IMIEA 0 R/W Input Capture/Compare Match Interrupt Enable A 0: Interrupt requests (IMIA) by IMFA flag are disabled 1: Interrupt requests (IMIA) by IMFA flag are enabled 13.3.
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Section 13 Timer Z 13.3.14 Interface with CPU 1. 16-bit register TCNT and GR are 16-bit registers. Reading/writing in a 16-bit unit is enabled but disabled in an 8-bit unit since the data bus with the CPU is 16-bit width. These registers must always be accessed in a 16-bit unit. Figure 13.5 shows an example of accessing the 16-bit registers. Internal data bus H C P L Module data bus Bus interface U TCNTH TCNTL Figure 13.5 Accessing Operation of 16-Bit Register (between CPU and TCNT (16 bits)) 2.
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Section 13 Timer Z 13.4 Operation 13.4.1 Counter Operation When one of bits STR0 and STR1 in TSTR is set to 1, the TCNT counter for the corresponding channel begins counting. TCNT can operate as a free-running counter, periodic counter, for example. Figure 13.7 shows an example of the counter operation setting procedure.
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Section 13 Timer Z 1. Free-running count operation and periodic count operation Immediately after a reset, the TCNT counters for channels 0 and 1 are all designated as freerunning counters. When the relevant bit in TSTR is set to 1, the corresponding TCNT counter starts an increment operation as a free-running counter. When TCNT overflows, the OVF flag in TSR is set to 1. If the value of the OVIE bit in the corresponding TIER is 1 at this point, timer Z requests an interrupt.
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Section 13 Timer Z TCNT value Counter cleared by GR compare match GR value H'0000 Time STR IMF Figure 13.9 Periodic Counter Operation 2. TCNT count timing A. Internal clock operation A system clock (φ) or three types of clocks (φ/2, φ/4, or φ/8) that divides the system clock can be selected by bits TPSC2 to TPSC0 in TCR. Figure 13.10 illustrates this timing. φ Internal clock TCNT input TCNT N-1 N N+1 Figure 13.10 Count Timing at Internal Clock Operation Rev. 2.00 Sep.
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Section 13 Timer Z B. External clock operation An external clock input pin (TCLK) can be selected by bits TPSC2 to TPSC0 in TCR, and a detection edge can be selected by bits CKEG1 and CKEG0. To detect an external clock, the rising edge, falling edge, or both edges can be selected. The pulse width of the external clock needs two or more system clocks. Note that an external clock does not operate correctly with the lower pulse width. Figure 13.
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Section 13 Timer Z 13.4.2 Waveform Output by Compare Match Timer Z can perform 0, 1, or toggle output from the corresponding FTIOA, FTIOB, FTIOC, or FTIOD output pin using compare match A, B, C, or D. Figure 13.12 shows an example of the setting procedure for waveform output by compare match.
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Section 13 Timer Z 1. Examples of waveform output operation Figure 13.13 shows an example of 0 output/1 output. In this example, TCNT has been designated as a free-running counter, and settings have been made such that 0 is output by compare match A, and 1 is output by compare match B. When the set level and the pin level coincide, the pin level does not change. TCNT value H'FFFF Time H'0000 FTIOB No change FTIOA No change No change No change Figure 13.
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Section 13 Timer Z TCNT value GRB GRA Time H'0000 Toggle output FTIOB FTIOA Toggle output Figure 13.14 Example of Toggle Output Operation 2. Output compare timing The compare match signal is generated in the last state in which TCNT and GR match (when TCNT changes from the matching value to the next value). When the compare match signal is generated, the output value selected in TIOR is output at the compare match output pin (FTIOA, FTIOB, FTIOC, or FTIOD).
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Section 13 Timer Z φ TCNT input TCNT N GR N N+1 Compare match signal FTIOA to FTIOD Figure 13.15 Output Compare Timing 13.4.3 Input Capture Function The TCNT value can be transferred to GR on detection of the input edge of the input capture/output compare pin (FTIOA, FTIOB, FTIOC, or FTIOD). Rising edge, falling edge, or both edges can be selected as the detected edge. When the input capture function is used, the pulse width or period can be measured. Figure 13.
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Section 13 Timer Z Input selection Select input edge of input capture [1] Start counter operation [2] [1] Designate GR as an input capture register by means of TIOR, and select rising edge, falling edge, or both edges as the input edge of the input capture signal. [2] Set the STR bit in TSTR to 1 to start the TCNT counter operation. Figure 13.16 Example of Input Capture Operation Setting Procedure 1. Example of input capture operation Figure 13.
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Section 13 Timer Z Counter cleared by FTIOB input (rising edge) TCNT value H'0180 H'0160 H'0005 H'0000 Time FTIOB FTIOA GRA H'0005 GRB H'0160 H'0180 Figure 13.17 Example of Input Capture Operation 2. Input capture signal timing Input capture on the rising edge, falling edge, or both edges can be selected through settings in TIOR. Figure 13.18 shows the timing when the rising edge is selected. The pulse width of the input capture signal must be at least two system clock (φ) cycles. Rev. 2.
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Section 13 Timer Z φ Input capture input Input capture signal TCNT N GR N Figure 13.18 Input Capture Signal Timing 13.4.4 Synchronous Operation In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables GR to be increased with respect to a single time base. Figure 13.
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Section 13 Timer Z Synchronous operation selection Set synchronous operation [1] Synchronous presetting Set TCNT Synchronous clearing [2] Clearing source generation channel? No Yes Select counter clearing source [3] Select counter clearing source [4] Start counter operation [5] Start counter operation [5] [1] Set the SYNC bits in TMDR to 1.
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Section 13 Timer Z TCNT values Synchronous clearing by GRA_0 compare match GRA_0 GRA_1 GRB_0 GRB_1 H'0000 Time FTIOB0 FTIOB1 Figure 13.20 Example of Synchronous Operation 13.4.5 PWM Mode In PWM mode, PWM waveforms are output from the FTIOB, FTIOC, and FTIOD output pins with GRA as a cycle register and GRB, GRC, and GRD as duty registers. The initial output level of the corresponding pin depends on the setting values of TOCR and POCR. Table 13.
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Section 13 Timer Z Table 13.3 Initial Output Level of FTIOB0 Pin TOB0 POLB Initial Output Level 0 0 1 0 1 0 1 0 0 1 1 1 PWM mode Select counter clock [1] Select counter clearing source [2] Set PWM mode [3] Set initial output level [4] Select output level [5] Set GR [6] Enable waveform output [7] Start counter operation [8] [1] Select the counter clock with bits TPSC2 to TOSC0 in TCR.
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Section 13 Timer Z Figure 13.22 shows an example of operation in PWM mode. The output signals go to 1 and TCNT is reset at compare match A, and the output signals go to 0 at compare match B, C, and D (TOB, TOC, and TOD = 0, POLB, POLC, and POLD = 0). Counter cleared by GRA compare match TCNT value GRA GRB GRC GRD H'0000 Time FTIOB FTIOC FTIOD Figure 13.22 Example of PWM Mode Operation (1) Figure 13.23 shows another example of operation in PWM mode.
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Section 13 Timer Z Counter cleared by GRA compare match TCNT value GRA GRB GRC GRD H'0000 Time FTIOB FTIOC FTIOD Figure 13.23 Example of PWM Mode Operation (2) Figures 13.24 (when TOB, TOC, and TOD = 0, POLB, POLC, and POLD = 0) and 13.25 (when TOB, TOC, and TOD = 0, POLB, POLC, and POLD = 1) show examples of the output of PWM waveforms with duty cycles of 0% and 100% in PWM mode. Rev. 2.00 Sep.
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Section 13 Timer Z TCNT value GRB rewritten GRA GRB GRB rewritten Time H'0000 0% duty FTIOB TCNT value GRB rewritten When cycle register and duty register compare matches occur simultaneously, duty register compare match has priority. GRA GRB rewritten GRB rewritten GRB H'0000 Time FTIOB 100% duty When cycle register and duty register compare matches occur simultaneously, duty register compare match has priority.
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Section 13 Timer Z TCNT value GRB rewritten GRA GRB GRB rewritten H'0000 Time FTIOB 0% duty TCNT value GRB rewritten When cycle register and duty register compare matches occur simultaneously, duty register compare match has priority. GRA GRB rewritten GRB rewritten GRB Time H'0000 100% duty FTIOB When cycle register and duty register compare matches occur simultaneously, duty register compare match has priority.
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Section 13 Timer Z 13.4.6 Reset Synchronous PWM Mode Three normal- and counter-phase PWM waveforms are output by combining channels 0 and 1 that one of changing points of waveforms will be common. In reset synchronous PWM mode, the FTIOB0 to FTIOD0 and FTIOA1 to FTIOD1 pins become PWM-output pins automatically. TCNT_0 performs an increment operation. Tables 13.4 and 13.5 show the PWM-output pins used and the register settings, respectively. Figure 13.
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Section 13 Timer Z Reset synchronous PWM mode Stop counter operation [1] Select counter clock [2] Select counter clearing source [3] Set reset synchronous PWM mode [4] Initialize the output pin [5] Set TCNT [6] Set GR [7] Enable waveform output [8] Start counter operation [9] [1] Clear bit STR0 in TSTR to 0 and stop the counter operation of TCNT_0. Set reset synchronous PWM mode after TCNT_0 stops. [2] Select the counter clock with bits TPSC2 to TOSC0 in TCR.
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Section 13 Timer Z Figures 13.27 and 13.28 show examples of operation in reset synchronous PWM mode. Counter cleared by GRA compare match TCNT value GRA_0 GRB_0 GRA_1 GRB_1 H'0000 Time FTIOB0 FTIOD0 FTIOA1 FTIOC1 FTIOB1 FTIOD1 FTIOC0 Figure 13.27 Example of Reset Synchronous PWM Mode Operation (OLS0 = OLS1 = 1) Rev. 2.00 Sep.
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Section 13 Timer Z Counter cleared by GRA compare match TCNT value GRA_0 GRB_0 GRA_1 GRB_1 H'0000 Time FTIOB0 FTIOD0 FTIOA1 FTIOC1 FTIOB1 FTIOD1 FTIOC0 Figure 13.28 Example of Reset Synchronous PWM Mode Operation (OLS0 = OLS1 = 0) In reset synchronous PWM mode, TCNT_0 and TCNT_1 perform increment and independent operations, respectively. However, GRA_1 and GRB_1 are separated from TCNT_1.
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Section 13 Timer Z 13.4.7 Complementary PWM Mode Three PWM waveforms for non-overlapped normal and counter phases are output by combining channels 0 and 1. In complementary PWM mode, the FTIOB0 to FTIOD0 and FTIOA1 to FTIOD1 pins become PWM-output pins automatically. TCNT_0 and TCNT_1 perform an increment or decrement operation. Tables 13.6 and 13.7 show the output pins and register settings in complementary PWM mode, respectively. Figure 13.
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Section 13 Timer Z Complementary PWM mode Stop counter operation [1] Initialize output pin [2] Select counter clock [3] Set complementary PWM mode [4] Initialize output pin [5] Set TCNT [6] Set GR [7] Enable waveform output [8] Start counter operation [9] [1] Clear bits STR0 and STR1 in TSTR to 0, and stop the counter operation of TCNT_0. Stop TCNT_0 and TCNT_1 and set complementary PWM mode. [2] Write H'00 to TOCR.
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Section 13 Timer Z 1. Canceling Procedure of Complementary PWM Mode: Figure 13.30 shows the complementary PWM mode canceling procedure. Complementary PWM mode Stop counter operation [1] Cancel complementary PWM mode [2] [1] Clear bit CMD1 in TFCR to 0, and set channels 0 and 1 to normal operation. [2] After setting channels 0 and 1 to normal operation, clear bits STR0 and STR1 in TSTR to 0 and stop TCNT0 and TCNT1. Figure 13.30 Canceling Procedure of Complementary PWM Mode 2.
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Section 13 Timer Z TCNT_0 and GRA_0 are compared and their contents match TCNT values GRA_0 GRB_0 GRA_1 GRB_1 H'0000 Time FTIOB0 FTIOD0 FTIOA1 FTIOC1 FTIOB1 FTIOD1 FTIOC0 Figure 13.31 Example of Complementary PWM Mode Operation (1) Rev. 2.00 Sep.
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Section 13 Timer Z Figure 13.32 (1) and (2) show examples of PWM waveform output with 0% duty and 100% duty in complementary PWM mode (for one phase). • TPSC2 = TPSC1 = TPSC0 = 0 Set GRB_0 to H'0000 or a value equal to or more than GRA_0. The waveform with a duty cycle of 0% and 100% can be output. When buffer operation is used together, the duty cycles can easily be changed, including the above settings, during operation. For details on buffer operation, refer to section 13.4.8, Buffer Operation.
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Section 13 Timer Z TCNT values GRA0 GRB0 H'0000 Time FTIOB0 FTIOD0 0% duty (a) When duty is 0% TCNT values GRA0 GRB0 H'0000 Time FTIOB0 FTIOD0 100% duty (b) When duty is 100% Figure 13.32 (1) Example of Complementary PWM Mode Operation (TPSC2 = TPSC1 = TPSC0 = 0) (2) Rev. 2.00 Sep.
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Section 13 Timer Z TCNT values GRA0 GRB0 H'0000 Time FTIOB0 FTIOD0 0% duty (a) When duty is 0% TCNT values GRA0 GRB0 H'0000 Time FTIOB0 FTIOD0 100% duty (b) When duty is 100% Figure 13.32 (2) Example of Complementary PWM Mode Operation (TPSC2 = TPSC1 = TPSC0 ≠ 0) (3) Rev. 2.00 Sep.
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Section 13 Timer Z In complementary PWM mode, when the counter switches from up-counter to down-counter or vice versa, TCNT_0 and TCNT_1 overshoots or undershoots, respectively. In this case, the conditions to set the IMFA flag in channel 0 and the UDF flag in channel 1 differ from usual settings. Also, the transfer conditions in buffer operation differ from usual settings. Such timings are shown in figures 13.33 and 13.34.
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Section 13 Timer Z When the counter is incremented or decremented, the IMFA flag of channel 0 is set to 1, and when the register is underflowed, the UDF flag of channel 0 is set to 1. After buffer operation has been designated for BR, BR is transferred to GR when the counter is incremented by compare match A0 or when TCNT_1 is underflowed. If the φ or φ/2 clock is selected by TPSC2 to TPSC0 bits, the OVF flag is not set to 1 at the timing that the counter value changes from H'FFFF to H'0000.
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Section 13 Timer Z • • b. • • c. • • To change duty cycles while a waveform with a duty cycle of 0% or 100% is being output, make sure the following procedure.
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Section 13 Timer Z 13.4.8 Buffer Operation Buffer operation differs depending on whether GR has been designated for an input capture register or an output compare register, or in reset synchronous PWM mode or complementary PWM mode. Table 13.8 shows the register combinations used in buffer operation. Table 13.8 Register Combinations in Buffer Operation General Register Buffer Register GRA GRC GRB GRD 1.
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Section 13 Timer Z Input capture signal General register Buffer register TCNT Figure 13.36 Input Capture Buffer Operation 3. Complementary PWM Mode When the counter switches from counting up to counting down or vice versa, the value of the buffer register is transferred to the general register. Here, the value of the buffer register is transferred to the general register in the following timing: A. When TCNT_0 and GRA_0 are compared and their contents match B. When TCNT_1 underflows 4.
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Section 13 Timer Z 6. Examples of Buffer Operation Figure 13.38 shows an operation example in which GRA has been designated as an output compare register, and buffer operation has been designated for GRA and GRC. This is an example of TCNT operating as a periodic counter cleared by compare match B. Pins FTIOA and FTIOB are set for toggle output by compare match A and B.
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Section 13 Timer Z φ n TCNT n+1 Compare match signal Buffer transfer signal GRC N GRA n N Figure 13.39 Example of Compare Match Timing for Buffer Operation Figure 13.40 shows an operation example in which GRA has been designated as an input capture register, and buffer operation has been designated for GRA and GRC. Counter clearing by input capture B has been set for TCNT, and falling edges have been selected as the FIOCB pin input capture input edge.
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Section 13 Timer Z Counter is cleared by the input capture B TCNT value H'0180 H'0160 H'0005 H'0000 Time FTIOB FTIOA GRA H'0005 H'0160 GRC H'0005 GRB H'0160 H'0180 Input capture A Figure 13.40 Example of Buffer Operation (2) (Buffer Operation for Input Capture Register) Rev. 2.00 Sep.
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Section 13 Timer Z φ FTIO pin Input capture signal TCNT n n+1 N N+1 GRA M n n N GRC m M M n Figure 13.41 Input Capture Timing of Buffer Operation Figures 13.42 and 13.43 show the operation examples when buffer operation has been designated for GRB_0 and GRD_0 in complementary PWM mode. These are examples when a PWM waveform of 0% duty is created by using the buffer operation and performing GRD_0 ≥ GRA_0.
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Section 13 Timer Z TCNT values GRB_0 (When restored, data will be transferred to the saved location regardless of the CMD1 and CMD0 values) TCNT_0 GRA_0 TCNT_1 H'0999 H'0000 Time GRD_0 H'0999 GRB_0 H'0999 H'1FFF H'0999 H'1FFF H'0999 H'0999 FTIOB0 FTIOD0 Figure 13.42 Buffer Operation (3) (Buffer Operation in Complementary PWM Mode CMD1 = CMD0 = 1) Rev. 2.00 Sep.
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Section 13 Timer Z GRB_0 (When restored, data will be transferred to the saved location regardless of the CMD1 and CMD0 values) TCNT values TCNT_0 GRA_0 TCNT_1 H'0999 H'0000 Time GRB_0 GRD_0 H'0999 GRB_0 H'0999 H'0000 H'0999 H'0000 H'0999 FTIOC0 FTIOD0 Figure 13.43 Buffer Operation (4) (Buffer Operation in Complementary PWM Mode CMD1 = CMD0 = 1) 13.4.9 Timer Z Output Timing The outputs of channels 0 and 1 can be disabled or inverted by the settings of TOER and TOCR and the external level.
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Section 13 Timer Z T1 T2 φ Address bus TOER address TOER Timer Z output pin I/O port Timer output Timer Z output I/O port Figure 13.44 Example of Output Disable Timing of Timer Z by Writing to TOER 2. Output Disable Timing of Timer Z by External Trigger: When P54/WKP4 is set as a WKP4 input pin, and low level is input to WKP4, the master enable bit in TOER is set to 1 and the output of timer Z will be disabled.
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Section 13 Timer Z 3. Output Inverse Timing by TFCR: The output level can be inverted by inverting the OLS1 and OLS0 bits in TFCR in reset synchronous PWM mode or complementary PWM mode. Figure 13.46 shows the timing. T1 T2 φ Address bus TOER address TFCR Timer Z output pin Inverted Figure 13.46 Example of Output Inverse Timing of Timer Z by Writing to TFCR 4. Output Inverse Timing by POCR: The output level can be inverted by inverting the POLD, POLC, and POLB bits in POCR in PWM mode. Figure 13.
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Section 13 Timer Z 13.5 Interrupts There are three kinds of timer Z interrupt sources; input capture/compare match, overflow, and underflow. An interrupt is requested when the corresponding interrupt request flag is set to 1 while the corresponding interrupt enable bit is set to 1. 13.5.1 Status Flag Set Timing 1. IMF Flag Set Timing: The IMF flag is set to 1 by the compare match signal that is generated when the GR matches with the TCNT.
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Section 13 Timer Z 2. IMF Flag Set Timing at Input Capture: When an input capture signal is generated, the IMF flag is set to 1 and the value of TCNT is simultaneously transferred to corresponding GR. Figure 13.49 shows the timing. φ Input capture signal IMF TCNT N GR N ITMZ Figure 13.49 IMF Flag Set Timing at Input Capture 3. Overflow Flag (OVF) Set Timing: The overflow flag is set to 1 when the TCNT overflows. Figure 13.50 shows the timing.
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Section 13 Timer Z 13.5.2 Status Flag Clearing Timing The status flag can be cleared by writing 0 after reading 1 from the CPU. Figure 13.51 shows the timing in this case. φ Address TSR address WTSR (internal write signal) IMF, OVF ITMZ Figure 13.51 Status Flag Clearing Timing Rev. 2.00 Sep.
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Section 13 Timer Z 13.6 Usage Notes 1. Contention between TCNT Write and Clear Operations: If a counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing has priority and the TCNT write is not performed. Figure 13.52 shows the timing in this case. TCNT write cycle T1 T2 φ TCNT address WTCNT (internal write signal) Counter clear signal TCNT N H'0000 Clearing has priority. Figure 13.52 Contention between TCNT Write and Clear Operations Rev. 2.00 Sep.
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Section 13 Timer Z 2. Contention between TCNT Write and Increment Operations: If incrementation is done in T2 state of a TCNT write cycle, TCNT writing has priority. Figure 13.53 shows the timing in this case. TCNT write cycle T1 T2 φ TCNT address WTCNT (internal write signal) TCNT input clock TCNT M N TCNT write data Figure 13.53 Contention between TCNT Write and Increment Operations Rev. 2.00 Sep.
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Section 13 Timer Z 3. Contention between GR Write and Compare Match: If a compare match occurs in the T2 state of a GR write cycle, GR write has priority and the compare match signal is disabled. Figure 13.54 shows the timing in this case. GR write cycle T1 T2 φ GR address WGR (internal write signal) TCNT N GR N N+1 M GR write data Compare match signal Disabled Figure 13.54 Contention between GR Write and Compare Match Rev. 2.00 Sep.
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Section 13 Timer Z 4. Contention between TCNT Write and Overflow/Underflow: If overflow/underflow occurs in the T2 state of a TCNT write cycle, TCNT write has priority without an increment operation. At this time, the OVF flag is set to 1. Figure 13.55 shows the timing in this case. TCNT write cycle T1 T2 φ TCNT address WTCNT (internal write signal) TCNT input clock Overflow signal TCNT H'FFFF M TCNT write data OVF Figure 13.55 Contention between TCNT Write and Overflow Rev. 2.00 Sep.
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Section 13 Timer Z 5. Contention between GR Read and Input Capture: If an input capture signal is generated in the T1 state of a GR read cycle, the data that is read will be transferred before input capture transfer. Figure 13.56 shows the timing in this case. GR read cycle T1 T2 φ GR address Internal read signal Input capture signal GR X Internal data bus M X Figure 13.56 Contention between GR Read and Input Capture Rev. 2.00 Sep.
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Section 13 Timer Z 6. Contention between Count Clearing and Increment Operations by Input Capture: If an input capture and increment signals are simultaneously generated, count clearing by the input capture operation has priority without an increment operation. The TCNT contents before clearing counter are transferred to GR. Figure 13.57 shows the timing in this case. φ Input capture signal Counter clear signal TCNT input clock TCNT GR N H'0000 N Clearing has priority. Figure 13.
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Section 13 Timer Z 7. Contention between GR Write and Input Capture: If an input capture signal is generated in the T2 state of a GR write cycle, the input capture operation has priority and the write to GR is not performed. Figure 13.58 shows the timing in this case. GR write cycle T1 T2 φ Address bus GR address WGR (internal write signal) Input capture signal TCNT N M GR GR write data Figure 13.58 Contention between GR Write and Input Capture 8.
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Section 13 Timer Z MOV.B #B'11101111, R0L Only the bit to be cleared is 0 and the other bits are all set to 1. MOV.B R0L,@TSR 10. Note on Writing to the TOA0 to TOD0 Bits and the TOA1 to TOD1 Bits in TOCR: The TOA0 to TOD0 bits and the TOA1 to TOD1 bits in TOCR decide the value of the FTIO pin, which is output until the first compare match occurs.
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Section 13 Timer Z TOCR has been set to H'06. Compare match B0 and compare match C0 are used. The FTIOB0 pin is in the 1 output state, and is set to the toggle output or the 0 output by compare match B0. When BCLR#2, @TOCR is executed to clear the TOC0 bit (the FTIOC0 signal is low) and compare match B0 occurs at the same timing as shown below, the H'02 writing to TOCR has priority and compare match B0 does not drive the FTIOB0 signal low; the FTIOB0 signal remains high.
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Section 14 Watchdog Timer Section 14 Watchdog Timer The watchdog timer is an 8-bit timer that can generate an internal reset signal for this LSI if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. The block diagram of the watchdog timer is shown in figure 14.1.
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Section 14 Watchdog Timer 14.2 Register Descriptions The watchdog timer has the following registers. • Timer control/status register WD (TCSRWD) • Timer counter WD (TCWD) • Timer mode register WD (TMWD) 14.2.1 Timer Control/Status Register WD (TCSRWD) TCSRWD performs the TCSRWD and TCWD write control. TCSRWD also controls the watchdog timer operation and indicates the operating state. TCSRWD must be rewritten by using the MOV instruction.
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Section 14 Watchdog Timer Bit Bit Name Initial Value R/W Description 2 WDON 0 R/W Watchdog Timer On TCWD starts counting up when WDON is set to 1 and halts when WDON is cleared to 0.
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Section 14 Watchdog Timer 14.2.3 Timer Mode Register WD (TMWD) TMWD selects the input clock. Bit Bit Name 7 to 4  Initial Value R/W Description All 1  Reserved These bits are always read as 1. 3 CKS3 1 R/W Clock Select 3 to 0 2 CKS2 1 R/W Select the clock to be input to TCWD.
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Section 14 Watchdog Timer 14.3 Operation The watchdog timer is provided with an 8-bit counter. If 1 is written to WDON while writing 0 to B2WI when the TCSRWE bit in TCSRWD is set to 1, TCWD begins counting up. (To operate the watchdog timer, two write accesses to TCSRWD are required.) When a clock pulse is input after the TCWD count value has reached H'FF, the watchdog timer overflows and an internal reset signal is generated. The internal reset signal is output for a period of 256 φosc clock cycles.
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Section 14 Watchdog Timer Rev. 2.00 Sep.
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Section 15 14-Bit PWM Section 15 14-Bit PWM The 14-bit PWM is a pulse division type PWM that can be used for electronic tuner control, etc. Figure 15.1 shows a block diagram of the 14-bit PWM. 15.1 Features • Choice of two conversion periods A conversion period of 32768/φ with a minimum modulation width of 2/φ, or a conversion period of 16384/φ with a minimum modulation width of 1/φ, can be selected.
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Section 15 14-Bit PWM 15.2 Input/Output Pin Table 15.1 shows the 14-bit PWM pin configuration. Table 15.1 Pin Configuration Name Abbreviation I/O Function 14-bit PWM square-wave output PWM 14-bit PWM square-wave output pin 15.3 Output Register Descriptions The 14-bit PWM has the following registers. • PWM control register (PWCR) • PWM data register U (PWDRU) • PWM data register L (PWDRL) 15.3.1 PWM Control Register (PWCR) PWCR selects the conversion period.
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Section 15 14-Bit PWM 15.3.2 PWM Data Registers U and L (PWDRU, PWDRL) PWDRU and PWDRL indicate high level width in one PWM waveform cycle. PWDRU and PWDRL are 14-bit write-only registers, with the upper 6 bits assigned to PWDRU and the lower 8 bits to PWDRL. When read, all bits are always read as 1. Both PWDRU and PWDRL are accessible only in bytes. Note that the operation is not guaranteed if word access is performed.
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Section 15 14-Bit PWM Conversion period t f1 t H1 t f2 t H2 t f63 t H3 t H63 t f64 t H64 T H = t H1 + t H2 + t H3 + ... + t H64 t f1 = t f2 = t f3 = ... = t f64 Figure 15.2 Waveform Output by 14-Bit PWM Rev. 2.00 Sep.
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Section 16 Serial Communication Interface 3 (SCI3) Section 16 Serial Communication Interface 3 (SCI3) This LSI includes a serial communication interface 3 (SCI3), which has independent two channels. The SCI3 can handle both asynchronous and clocked synchronous serial communication.
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Section 16 Serial Communication Interface 3 (SCI3) Clocked synchronous mode • Data length: 8 bits • Receive error detection: Overrun errors Table 16.
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Section 16 Serial Communication Interface 3 (SCI3) SCK3 External clock Internal clock (ø/64, ø/16, ø/4, ø) Baud rate generator BRC BRR Clock Transmit/receive control circuit Internal data bus SMR SCR3 SSR TXD TSR TDR RXD RSR RDR Interrupt request (TEI, TXI, RXI, ERI) [Legend] RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register SCR3: Serial control register 3 SSR: Serial status register BRR: Bit rate registe
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Section 16 Serial Communication Interface 3 (SCI3) 16.2 Input/Output Pins Table 16.2 shows the SCI3 pin configuration. Table 16.2 Pin Configuration Pin Name Abbreviation I/O Function SCI3 clock SCK3 I/O SCI3 clock input/output SCI3 receive data input RXD Input SCI3 receive data input SCI3 transmit data output TXD Output SCI3 transmit data output 16.3 Register Descriptions The SCI3 has the following registers for each channel.
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Section 16 Serial Communication Interface 3 (SCI3) 16.3.1 Receive Shift Register (RSR) RSR is a shift register that is used to receive serial data input from the RxD pin and convert it into parallel data. When one frame of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU. 16.3.2 Receive Data Register (RDR) RDR is an 8-bit register that stores received data.
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Section 16 Serial Communication Interface 3 (SCI3) 16.3.5 Serial Mode Register (SMR) SMR is used to set the SCI3’s serial transfer format and select the baud rate generator clock source. Bit Bit Name Initial Value R/W Description 7 COM 0 R/W Communication Mode 0: Asynchronous mode 1: Clocked synchronous mode 6 CHR 0 R/W Character Length (enabled only in asynchronous mode) 0: Selects 8 bits as the data length. 1: Selects 7 bits as the data length.
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Section 16 Serial Communication Interface 3 (SCI3) Bit Bit Name Initial Value R/W Description 1 CKS1 0 R/W Clock Select 0 and 1 0 CKS0 0 R/W These bits select the clock source for the baud rate generator. 00: φ clock (n = 0) 01: φ/4 clock (n = 1) 10: φ/16 clock (n = 2) 11: φ/64 clock (n = 3) For the relationship between the bit rate register setting and the baud rate, see section 16.3.8, Bit Rate Register (BRR). n is the decimal representation of the value of n in BRR (see section 16.3.
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Section 16 Serial Communication Interface 3 (SCI3) Bit Bit Name Initial Value R/W Description 3 MPIE 0 R/W Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and OER status flags in SSR is disabled. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed.
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Section 16 Serial Communication Interface 3 (SCI3) 16.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI3 and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, OER, PER, and FER; they can only be cleared. Bit Bit Name Initial Value R/W Description 7 TDRE 1 R/W Transmit Data Register Empty Indicates whether TDR contains transmit data.
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Section 16 Serial Communication Interface 3 (SCI3) Bit Bit Name Initial Value R/W Description 3 PER 0 R/W Parity Error [Setting condition] • When a parity error is detected during reception [Clearing condition] • 2 TEND 1 R When 0 is written to PER after reading PER = 1 Transmit End [Setting conditions] • When the TE bit in SCR3 is 0 • When TDRE = 1 at transmission of the last bit of a 1frame serial transmit character [Clearing conditions] 1 MPBR 0 R • When 0 is written to TDRE af
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Section 16 Serial Communication Interface 3 (SCI3) 16.3.8 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. The initial value of BRR is H'FF. Table 16.3 shows the relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0 of SMR in asynchronous mode. Table 16.4 shows the maximum bit rate for each frequency in asynchronous mode. The values shown in both tables 16.3 and 16.4 are values in active (highspeed) mode. Table 16.
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Section 16 Serial Communication Interface 3 (SCI3) Table 16.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) Operating Frequency φ (MHz) 4 4.9152 5 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) 110 2 70 0.03 2 86 0.31 2 88 –0.25 150 1 207 0.16 1 255 0.00 2 64 0.16 300 1 103 0.16 1 127 0.00 1 129 0.16 600 0 207 0.16 0 255 0.00 1 64 0.16 1200 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 51 0.16 0 63 0.
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Section 16 Serial Communication Interface 3 (SCI3) Table 16.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) Operating Frequency φ (MHz) 6 6.144 7.3728 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) 110 2 106 –0.44 2 108 0.08 2 130 –0.07 150 2 77 0.16 2 79 0.00 2 95 0.00 300 1 155 0.16 1 159 0.00 1 191 0.00 600 1 77 0.16 1 79 0.00 1 95 0.00 1200 0 155 0.16 0 159 0.00 0 191 0.00 2400 0 77 0.16 0 79 0.
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Section 16 Serial Communication Interface 3 (SCI3) Operating Frequency φ (MHz) 8 9.8304 10 12 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 141 0.03 2 174 –0.26 2 177 –0.25 2 212 0.03 150 2 103 0.16 2 127 0.00 2 129 0.16 2 155 0.16 300 1 207 0.16 1 255 0.00 2 64 0.16 2 77 0.16 600 1 103 0.16 1 127 0.00 1 129 0.16 1 155 0.16 1200 0 207 0.16 0 255 0.00 1 64 0.16 1 77 0.16 2400 0 103 0.
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Section 16 Serial Communication Interface 3 (SCI3) Table 16.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (3) Operating Frequency φ (MHz) 12.888 14 14.7456 16 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 217 0.08 2 248 –0.17 3 64 0.70 3 70 0.03 150 2 159 0.00 2 181 0.16 2 191 0.00 2 207 0.16 300 2 79 0.00 2 90 0.16 2 95 0.00 2 103 0.16 600 1 159 0.00 1 181 0.16 1 191 0.00 1 207 0.
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Section 16 Serial Communication Interface 3 (SCI3) Operating Frequency φ (MHz) 18 Bit Rate (bit/s) n N Error (%) 110 3 79 –0.12 150 2 233 0.16 300 2 116 0.16 600 1 233 0.16 1200 1 116 0.16 2400 0 233 0.16 4800 0 116 0.16 9600 0 58 –0.96 19200 0 28 1.02 31250 0 17 0.00 38400 0 14 –2.34 [Legend] —: A setting is available but error occurs. Rev. 2.00 Sep.
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Section 16 Serial Communication Interface 3 (SCI3) Table 16.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) φ (MHz) Maximum Bit Rate (bit/s) n N 4 125000 0 0 4.9152 153600 0 0 5 156250 0 0 6 187500 0 0 6.144 192000 0 0 7.3728 230400 0 0 8 250000 0 0 9.8304 307200 0 0 10 312500 0 0 12 375000 0 0 12.288 384000 0 0 14 437500 0 0 14.7456 460800 0 0 16 500000 0 0 17.2032 537600 0 0 18 562500 0 0 Rev. 2.00 Sep.
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Section 16 Serial Communication Interface 3 (SCI3) Table 16.5 Examples of BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (1) Operating Frequency φ (MHz) 4 8 10 Bit Rate (bit/s) n N n N n N 110 — — — — — — 250 2 249 3 124 — — 16 n N 3 249 500 2 124 2 249 — — 3 124 1k 1 249 2 124 — — 2 249 2.
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Section 16 Serial Communication Interface 3 (SCI3) Table 16.5 Examples of BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (2) Operating Frequency φ (MHz) 18 Bit Rate (bit/s) n N 110 — — 250 — — 500 3 140 1k 3 69 2.5k 2 112 5k 1 224 10k 1 112 25k 0 179 50k 0 89 100k 0 44 250k 0 17 500k 0 8 1M 0 4 2M — — 2.5M — — 4M — — [Legend] Blank: No setting is available. —: A setting is available but error occurs. *: Continuous transfer is not possible.
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Section 16 Serial Communication Interface 3 (SCI3) 16.4 Operation in Asynchronous Mode Figure 16.2 shows the general format for asynchronous serial communication. One character (or frame) consists of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and finally stop bits (high level). Inside the SCI3, the transmitter and receiver are independent units, enabling full-duplex.
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Section 16 Serial Communication Interface 3 (SCI3) 16.4.2 SCI3 Initialization Before transmitting and receiving data, you should first clear the TE and RE bits in SCR3 to 0, then initialize the SCI3 as described below. When the operating mode, or transfer format, is changed for example, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1.
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Section 16 Serial Communication Interface 3 (SCI3) 16.4.3 Data Transmission Figure 16.5 shows an example of operation for transmission in asynchronous mode. In transmission, the SCI3 operates as described below. 1. The SCI3 monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI3 recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI3 sets the TDRE flag to 1 and starts transmission.
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Section 16 Serial Communication Interface 3 (SCI3) Start transmission [1] Read TDRE flag in SSR No TDRE = 1 Yes Write transmit data to TDR [2] Yes All data transmitted? [1] Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automaticaly cleared to 0. [2] To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR.
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Section 16 Serial Communication Interface 3 (SCI3) 16.4.4 Serial Data Reception Figure 16.7 shows an example of operation for reception in asynchronous mode. In serial reception, the SCI3 operates as described below. 1. The SCI3 monitors the communication line. If a start bit is detected, the SCI3 performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit. 2.
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Section 16 Serial Communication Interface 3 (SCI3) Table 16.6 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 16.8 shows a sample flow chart for serial data reception. Table 16.
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Section 16 Serial Communication Interface 3 (SCI3) Start reception Read OER, PER, and FER flags in SSR [1] Yes OER+PER+FER = 1 [4] No Error processing (Continued on next page) Read RDRF flag in SSR [2] No RDRF = 1 Yes Read receive data in RDR [1] Read the OER, PER, and FER flags in SSR to identify the error. If a receive error occurs, performs the appropriate error processing. [2] Read SSR and check that RDRF = 1, then read the receive data in RDR. The RDRF flag is cleared automatically.
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Section 16 Serial Communication Interface 3 (SCI3) [4] Error processing No OER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No Framing error processing No PER = 1 Yes Parity error processing (A) Clear OER, PER, and FER flags in SSR to 0 Figure 16.8 Sample Serial Reception Data Flowchart (Asynchronous Mode)(2) Rev. 2.00 Sep.
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Section 16 Serial Communication Interface 3 (SCI3) 16.5 Operation in Clocked Synchronous Mode Figure 16.9 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received synchronous with clock pulses. A single character in the transmit data consists of the 8-bit data starting from the LSB. In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the synchronization clock to the next.
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Section 16 Serial Communication Interface 3 (SCI3) 16.5.3 Serial Data Transmission Figure 16.10 shows an example of SCI3 operation for transmission in clocked synchronous mode. In serial transmission, the SCI3 operates as described below. 1. The SCI3 monitors the TDRE flag in SSR, and if the flag is 0, the SCI3 recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. The SCI3 sets the TDRE flag to 1 and starts transmission.
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Section 16 Serial Communication Interface 3 (SCI3) Serial clock Serial data Bit 0 Bit 1 1 frame Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 1 frame TDRE TEND LSI TXI interrupt operation request generated TDRE flag cleared to 0 User processing Data written to TDR TXI interrupt request generated TEI interrupt request generated Figure 16.10 Example of SCI3 Transmission in Clocked Synchronous Mode Rev. 2.00 Sep.
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Section 16 Serial Communication Interface 3 (SCI3) Start transmission [1] [1] Read TDRE flag in SSR No TDRE = 1 Yes [2] Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0 and clocks are output to start the data transmission. To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR.
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Section 16 Serial Communication Interface 3 (SCI3) 16.5.4 Serial Data Reception (Clocked Synchronous Mode) Figure 16.12 shows an example of SCI3 operation for reception in clocked synchronous mode. In serial reception, the SCI3 operates as described below. 1. The SCI3 performs internal initialization synchronous with a synchronization clock input or output, starts receiving data. 2. The SCI3 stores the receive data in RSR. 3.
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Section 16 Serial Communication Interface 3 (SCI3) Start reception [1] [1] Read OER flag in SSR [2] Yes OER = 1 [4] No Error processing [3] (Continued below) Read RDRF flag in SSR [2] [4] No RDRF = 1 Yes Read the OER flag in SSR to determine if there is an error. If an overrun error has occurred, execute overrun error processing. Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR. When data is read from RDR, the RDRF flag is automatically cleared to 0.
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Section 16 Serial Communication Interface 3 (SCI3) 16.5.5 Simultaneous Serial Data Transmission and Reception Figure 16.14 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations. To switch from transmit mode to simultaneous transmit and receive mode, after checking that the SCI3 has finished transmission and the TDRE and TEND flags are set to 1, clear TE to 0.
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Section 16 Serial Communication Interface 3 (SCI3) Start transmission/reception Read TDRE flag in SSR [1] [1] No TDRE = 1 Yes Write transmit data to TDR Read OER flag in SSR OER = 1 No Read RDRF flag in SSR Yes [4] Error processing [2] No RDRF = 1 Yes Read receive data in RDR Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0.
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Section 16 Serial Communication Interface 3 (SCI3) 16.6 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer between a number of processors sharing communication lines by asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is performed, each receiving station is addressed by a unique ID code.
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Section 16 Serial Communication Interface 3 (SCI3) Transmitting station Serial transmission line Receiving station A Receiving station B Receiving station C Receiving station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial data H'01 H'AA (MPB = 1) (MPB = 0) ID transmission cycle = Data transmission cycle = receiving station Data transmission to specification receiving station specified by ID Legend MPB: Multiprocessor bit Figure 16.
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Section 16 Serial Communication Interface 3 (SCI3) 16.6.1 Multiprocessor Serial Data Transmission Figure 16.16 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI3 operations are the same as those in asynchronous mode. Rev. 2.00 Sep.
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Section 16 Serial Communication Interface 3 (SCI3) Start transmission [1] [1] Read TDRE flag in SSR No TDRE = 1 [2] Yes Set MPBT bit in SSR [3] Write transmit data to TDR Yes [2] Read SSR and check that the TDRE flag is set to 1, set the MPBT bit in SSR to 0 or 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0. To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR.
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Section 16 Serial Communication Interface 3 (SCI3) 16.6.2 Multiprocessor Serial Data Reception Figure 16.17 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR3 is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI3 operations are the same as those in asynchronous mode. Figure 16.
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Section 16 Serial Communication Interface 3 (SCI3) [1] [2] Start reception Set MPIE bit in SCR3 to 1 [1] Read OER and FER flags in SSR [2] [3] Yes FER+OER = 1 No Read RDRF flag in SSR [3] No [4] [5] RDRF = 1 Yes Read receive data in RDR No This station’s ID? Set the MPIE bit in SCR3 to 1. Read OER and FER in SSR to check for errors. Receive error processing is performed in cases where a receive error occurs.
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Section 16 Serial Communication Interface 3 (SCI3) [5] Error processing No OER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No [A] Framing error processing Clear OER, and FER flags in SSR to 0 Figure 16.17 Sample Multiprocessor Serial Reception Flowchart (2) Rev. 2.00 Sep.
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Section 16 Serial Communication Interface 3 (SCI3) Start bit Serial data 1 0 Receive data (ID1) D0 D1 D7 MPB 1 Stop Start bit bit 1 0 Receive data (Data1) D0 1 frame D1 D7 MPB Stop bit Mark state (idle state) 0 1 1 1 frame MPIE RDRF RDR value ID1 LSI operation RDRF flag cleared to 0 RXI interrupt request MPIE cleared to 0 User processing RXI interrupt request is not generated, and RDR retains its state RDR data read When data is not this station's ID, MPIE is set to 1 again (a
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Section 16 Serial Communication Interface 3 (SCI3) 16.7 Interrupts SCI3 creates the following six interrupt requests: transmission end, transmit data empty, receive data full, and receive errors (overrun error, framing error, and parity error). Table 16.7 shows the interrupt sources. Table 16.
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Section 16 Serial Communication Interface 3 (SCI3) 16.8 Usage Notes 16.8.1 Break Detection and Processing When framing error detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, setting the FER flag, and possibly the PER flag. Note that as the SCI3 continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. 16.8.
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Section 16 Serial Communication Interface 3 (SCI3) 16.8.4 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI3 operates on a basic clock with a frequency of 16 times the transfer rate. In reception, the SCI3 samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the basic clock as shown in figure 16.19.
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2 Section 17 I C Bus Interface 2 (IIC2) Section 17 I2C Bus Interface 2 (IIC2) The I2C bus interface 2 conforms to and provides a subset of the Philips I2C bus (inter-IC bus) interface functions. The register configuration that controls the I2C bus differs partly from the Philips configuration, however. Figure 17.1 shows a block diagram of the I2C bus interface 2. Figure 17.2 shows an example of I/O pin connections to external circuits. 17.
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2 Section 17 I C Bus Interface 2 (IIC2) Transfer clock generation circuit SCL Transmission/ reception control circuit Output control ICCR1 ICCR2 ICMR Internal data bus Noise canceler ICDRT SDA Output control ICDRS SAR Address comparator Noise canceler ICDRR Bus state decision circuit Arbitration decision circuit ICSR ICIER Interrupt generator [Legend] ICCR1: ICCR2: ICMR: ICSR: ICIER: ICDRT: ICDRR: ICDRS: SAR: 2 I C bus control register 1 I2C bus control register 2 I2C bus mode register I2
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2 Section 17 I C Bus Interface 2 (IIC2) Vcc SCL in Vcc SCL SCL SDA SDA SCL out SDA in SCL in SCL out SCL SDA (Master) SCL SDA SDA out SCL in SCL out SDA in SDA in SDA out SDA out (Slave 1) (Slave 2) Figure 17.2 External Circuit Connections of I/O Pins Rev. 2.00 Sep.
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2 Section 17 I C Bus Interface 2 (IIC2) 17.2 Input/Output Pins Table 17.1 summarizes the input/output pins used by the I2C bus interface 2. Table 17.1 I2C Bus Interface Pins Name Abbreviation I/O Function Serial clock SCL I/O IIC serial clock input/output Serial data SDA I/O IIC serial data input/output Note: SCL and SDA pins are NMOS open drains, when the bus drive function is selected.
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2 Section 17 I C Bus Interface 2 (IIC2) 17.3.1 I2C Bus Control Register 1 (ICCR1) ICCR1 enables or disables the I2C bus interface 2, controls transmission or reception, and selects master or slave mode, transmission or reception, and transfer clock frequency in master mode. Bit Bit Name Initial Value R/W Description 7 ICE 0 R/W I2C Bus Interface Enable 0: This module is halted. (SCL and SDA pins are set to port function.) 1: This bit is enabled for transfer operations.
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2 Section 17 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 3 CKS3 0 R/W Transfer Clock Select 3 to 0 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W These bits should be set according to the necessary transfer rate (see table 17.2) in master mode. In slave mode, these bits are used for reservation of the setup time in transmit mode. The time is 10 tcyc when CKS3 = 0 and 20 tcyc when CKS3 = 1. Table 17.
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2 Section 17 I C Bus Interface 2 (IIC2) 17.3.2 I2C Bus Control Register 2 (ICCR2) ICCR1 issues start/stop conditions, manipulates the SDA pin, monitors the SCL pin, and controls reset in the control part of the I2C bus interface 2. Bit Bit Name Initial Value R/W Description 7 BBSY 0 R/W Bus Busy 2 This bit enables to confirm whether the I C bus is occupied or released and to issue start/stop conditions in master mode. With the clocked synchronous serial 2 format, this bit has no meaning.
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2 Section 17 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 4 SDAOP 1 R/W SDAO Write Protect This bit controls change of output level of the SDA pin by modifying the SDAO bit. To change the output level, clear SDAO and SDAOP to 0 or set SDAO to 1 and clear SDAOP to 0 by the MOV instruction. This bit is always read as 1. 3 SCLO 1 R This bit monitors SCL output level. When SCLO is 1, SCL pin outputs high. When SCLO is 0, SCL pin outputs low.
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2 Section 17 I C Bus Interface 2 (IIC2) 17.3.3 I2C Bus Mode Register (ICMR) ICMR selects whether the MSB or LSB is transferred first, performs master mode wait control, and selects the transfer bit count. Bit Bit Name Initial Value R/W 7 MLS 0 R/W Description MSB-First/LSB-First Select 0: MSB-first 1: LSB-first Set this bit to 0 when the I2C bus format is used.
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2 Section 17 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 2 BC2 0 R/W Bit Counter 2 to 0 1 BC1 0 R/W 0 BC0 0 R/W These bits specify the number of bits to be transferred next. When read, the remaining number of transfer bits is indicated. With the I2C bus format, the data is transferred with one addition acknowledge bit. Bit BC2 to BC0 settings should be made during an interval between transfer frames.
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2 Section 17 I C Bus Interface 2 (IIC2) 17.3.4 I2C Bus Interrupt Enable Register (ICIER) ICIER enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be transferred, and confirms acknowledge bits to be received. Bit Bit Name Initial Value R/W Description 7 TIE 0 R/W Transmit Interrupt Enable When the TDRE bit in ICSR is set to 1, this bit enables or disables the transmit data empty interrupt (TXI). 0: Transmit data empty interrupt request (TXI) is disabled.
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2 Section 17 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 4 NAKIE 0 R/W NACK Receive Interrupt Enable This bit enables or disables the NACK receive interrupt request (NAKI) and the overrun error (setting of the OVE bit in ICSR) interrupt request (ERI) with the clocked synchronous format, when the NACKF and AL bits in ICSR are set to 1. NAKI can be canceled by clearing the NACKF, OVE, or NAKIE bit to 0. 0: NACK receive interrupt request (NAKI) is disabled.
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2 Section 17 I C Bus Interface 2 (IIC2) 17.3.5 I2C Bus Status Register (ICSR) ICSR performs confirmation of interrupt request flags and status.
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2 Section 17 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 4 NACKF 0 R/W No Acknowledge Detection Flag [Setting condition] • When no acknowledge is detected from the receive device in transmission while the ACKE bit in ICIER is 1 [Clearing condition] • 3 STOP 0 R/W When 0 is written in NACKF after reading NACKF = 1 Stop Condition Detection Flag [Setting Conditions] • In master mode, when a stop condition is detected after frame transfer • In slave mode, when a st
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2 Section 17 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 2 AL/OVE 0 R/W Arbitration Lost Flag/Overrun Error Flag This flag indicates that arbitration was lost in master 2 mode with the I C bus format and that the final bit has been received while RDRF = 1 with the clocked synchronous format.
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2 Section 17 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 0 ADZ 0 R/W General Call Address Recognition Flag 2 This bit is valid in I C bus format slave receive mode. [Setting condition] • When the general call address is detected in slave receive mode [Clearing conditions] • 17.3.6 When 0 is written in ADZ after reading ADZ=1 Slave Address Register (SAR) SAR selects the communication format and sets the slave address.
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2 Section 17 I C Bus Interface 2 (IIC2) 17.3.7 I2C Bus Transmit Data Register (ICDRT) ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT to ICDRS and starts transferring data. If the next transfer data is written to ICDRT during transferring data of ICDRS, continuous transfer is possible.
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2 Section 17 I C Bus Interface 2 (IIC2) 17.4 Operation The I2C bus interface can communicate either in I2C bus mode or clocked synchronous serial mode by setting FS in SAR. 17.4.1 I2C Bus Format Figure 17.3 shows the I2C bus formats. Figure 17.4 shows the I2C bus timing. The first frame following a start condition always consists of 8 bits.
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2 Section 17 I C Bus Interface 2 (IIC2) [Legend] S: Start condition. The master device drives SDA from high to low while SCL is high. SLA: Slave address R/W: Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0. A: Acknowledge. The receive device drives SDA to low. DATA: Transfer data P: Stop condition. The master device drives SDA from low to high while SCL is high. 17.4.
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2 Section 17 I C Bus Interface 2 (IIC2) SCL (Master output) 1 2 3 4 5 6 SDA (Master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 7 8 Bit 1 Slave address 9 1 Bit 0 Bit 7 2 Bit 6 R/W SDA (Slave output) A TDRE TEND Address + R/W ICDRT ICDRS User processing Data 1 Address + R/W [2] Instruction of start condition issuance Data 2 Data 1 [4] Write data to ICDRT (second byte) [5] Write data to ICDRT (third byte) [3] Write data to ICDRT (first byte) Figure 17.
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2 Section 17 I C Bus Interface 2 (IIC2) 17.4.3 Master Receive Operation In master receive mode, the master device outputs the receive clock, receives data from the slave device, and returns an acknowledge signal. For master receive mode operation timing, refer to figures 17.7 and 17.8. The reception procedure and operations in master receive mode are shown below. 1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCR1 to 0 to switch from master transmit mode to master receive mode.
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2 Section 17 I C Bus Interface 2 (IIC2) Master transmit mode SCL (Master output) Master receive mode 9 1 2 3 4 5 6 7 8 SDA (Master output) 9 1 A SDA (Slave output) A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 TDRE TEND TRS RDRF ICDRS Data 1 ICDRR User processing Data 1 [3] Read ICDRR [1] Clear TDRE after clearing TEND and TRS [2] Read ICDRR (dummy read) Figure 17.7 Master Receive Mode Operation Timing (1) Rev. 2.00 Sep.
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2 Section 17 I C Bus Interface 2 (IIC2) SCL (Master output) 9 SDA (Master output) A SDA (Slave output) 1 2 3 4 5 6 7 8 9 A/A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RDRF RCVD ICDRS Data n Data n-1 ICDRR Data n Data n-1 User processing [5] Read ICDRR after setting RCVD [7] Read ICDRR, and clear RCVD [6] Issue stop condition [8] Set slave receive mode Figure 17.8 Master Receive Mode Operation Timing (2) 17.4.
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2 Section 17 I C Bus Interface 2 (IIC2) Slave receive mode Slave transmit mode SCL (Master output) 9 1 2 3 4 5 6 7 8 9 SDA (Master output) 1 A SCL (Slave output) SDA (Slave output) A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 TDRE TEND TRS Data 1 ICDRT ICDRS Data 2 Data 1 Data 3 Data 2 ICDRR User processing [2] Write data to ICDRT (data 1) [2] Write data to ICDRT (data 2) [2] Write data to ICDRT (data 3) Figure 17.
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2 Section 17 I C Bus Interface 2 (IIC2) Slave receive mode Slave transmit mode SCL (Master output) 9 SDA (Master output) A 1 2 3 4 5 6 7 8 9 A SCL (Slave output) SDA (Slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TDRE TEND TRS ICDRT ICDRS Data n ICDRR User processing [3] Clear TEND [4] Read ICDRR (dummy read) after clearing TRS [5] Clear TDRE Figure 17.10 Slave Transmit Mode Operation Timing (2) Rev. 2.00 Sep.
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2 Section 17 I C Bus Interface 2 (IIC2) 17.4.5 Slave Receive Operation In slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. For slave receive mode operation timing, refer to figures 17.11 and 17.12. The reception procedure and operations in slave receive mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0 bits in ICCR1 to 1.
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2 Section 17 I C Bus Interface 2 (IIC2) SCL (Master output) 9 SDA (Master output) 1 2 3 4 5 6 7 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 SCL (Slave output) SDA (Slave output) A A RDRF ICDRS Data 2 Data 1 ICDRR Data 1 User processing [3] Set ACKBT [3] Read ICDRR [4] Read ICDRR Figure 17.12 Slave Receive Mode Operation Timing (2) 17.4.
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2 Section 17 I C Bus Interface 2 (IIC2) (2) Transmit Operation In transmit mode, transmit data is output from SDA, in synchronization with the fall of the transfer clock. The transfer clock is output when MST in ICCR1 is 1, and is input when MST is 0. For transmit mode operation timing, refer to figure 17.14. The transmission procedure and operations in transmit mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) 2.
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2 Section 17 I C Bus Interface 2 (IIC2) (3) 6Receive Operation In receive mode, data is latched at the rise of the transfer clock. The transfer clock is output when MST in ICCR1 is 1, and is input when MST is 0. For receive mode operation timing, refer to figure 17.15. The reception procedure and operations in receive mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) 2.
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2 Section 17 I C Bus Interface 2 (IIC2) 17.4.7 Noise Canceler The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched internally. Figure 17.16 shows a block diagram of the noise canceler circuit. The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree.
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2 Section 17 I C Bus Interface 2 (IIC2) Start Initialize [1] Test the status of the SCL and SDA lines. [2] Set master transmit mode. [3] Issue the start candition. [2] [4] Set the first byte (slave address + R/W) of transmit data. Write 1 to BBSY and 0 to SCP. [3] [5] Wait for 1 byte to be transmitted. Write transmit data in ICDRT [4] [6] Test the acknowledge transferred from the specified slave device.
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2 Section 17 I C Bus Interface 2 (IIC2) Mater receive mode [1] Clear TEND, select master receive mode, and then clear TDRE.* [2] Set acknowledge to the transmit device.* [3] Dummy-read ICDDR.* [4] Wait for 1 byte to be received [5] Check whether it is the (last receive - 1). [6] Read the receive data last. [7] Set acknowledge of the final byte. Disable continuous reception (RCVD = 1). [8] Read the (final byte - 1) of receive data. [9] Wait for the last byte to be receive.
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2 Section 17 I C Bus Interface 2 (IIC2) [1] Clear the AAS flag. Slave transmit mode Clear AAS in ICSR [1] Write transmit data in ICDRT [2] [3] Wait for ICDRT empty. [4] Set the last byte of transmit data. Read TDRE in ICSR No [5] Wait for the last byte to be transmitted. [3] TDRE=1 ? Yes No [6] Clear the TEND flag . [7] Set slave receive mode. Last byte? Yes [2] Set transmit data for ICDRT (except for the last data). [8] Dummy-read ICDRR to release the SCL line. [4] [9] Clear the TDRE flag.
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2 Section 17 I C Bus Interface 2 (IIC2) Slave receive mode [1] Clear the AAS flag. Clear AAS in ICSR [1] Clear ACKBT in ICIER to 0 [2] Dummy-read ICDRR [3] [2] Set acknowledge to the transmit device. [3] Dummy-read ICDRR. [5] Check whether it is the (last receive - 1). Read RDRF in ICSR No [4] RDRF=1 ? [6] Read the receive data. [7] Set acknowledge of the last byte. Yes Last receive - 1? [4] Wait for 1 byte to be received.
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2 Section 17 I C Bus Interface 2 (IIC2) 17.5 Interrupt Request There are six interrupt requests in this module; transmit data empty, transmit end, receive data full, NACK receive, STOP recognition, and arbitration lost/overrun error. Table 17.3 shows the contents of each interrupt request. Table 17.
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2 Section 17 I C Bus Interface 2 (IIC2) 17.6 Bit Synchronous Circuit In master mode, this module has a possibility that high level period may be short in the two states described below. • When SCL is driven to low by the slave device • When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pullup resistance) Therefore, it monitors SCL and communicates by bit with synchronization. Figure 17.21 shows the timing of the bit synchronous circuit and table 17.
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2 Section 17 I C Bus Interface 2 (IIC2) 17.7 Usage Notes 17.7.1 Issue (Retransmission) of Start/Stop Conditions In master mode, when the start/stop conditions are issued (retransmitted) at the specific timing under the following condition 1 or 2, such conditions may not be output successfully. To avoid this, issue (retransmit) the start/stop conditions after the fall of the ninth clock is confirmed. Check the SCLO bit in the I2C control register 2 (IICR2) to confirm the fall of the ninth clock. 1.
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2 Section 17 I C Bus Interface 2 (IIC2) Rev. 2.00 Sep.
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Section 18 A/D Converter Section 18 A/D Converter This LSI includes a successive approximation type 10-bit A/D converter that allows up to eight analog input channels to be selected. The block diagram of the A/D converter is shown in figure 18.1. 18.1 • • • • • • • • Features 10-bit resolution Eight input channels Conversion time: at least 3.
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Section 18 A/D Converter Module data bus AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Analog multiplexer 10-bit D/A Bus interface Successive approximations register AVCC Internal data bus A D D R A A D D R B A D D R C A D D R D A D C S R A D C R + ø/4 Control circuit Comparator Sample-andhold circuit ADTRG [Legend] ADCR: A/D control register ADCSR: A/D control/status register ADDRA: A/D data register A ADDRB: A/D data register B ADDRC: A/D data register C ADDRD: A/D data register D Figure 18.
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Section 18 A/D Converter 18.2 Input/Output Pins Table 18.1 summarizes the input pins used by the A/D converter. The 8 analog input pins are divided into two groups; analog input pins 0 to 3 (AN0 to AN3) comprising group 0, analog input pins 4 to 7 (AN4 to AN7) comprising group 1. The AVcc pin is the power supply pin for the analog block in the A/D converter. Table 18.
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Section 18 A/D Converter 18.3 Register Descriptions The A/D converter has the following registers. • • • • • • A/D data register A (ADDRA) A/D data register B (ADDRB) A/D data register C (ADDRC) A/D data register D (ADDRD) A/D control/status register (ADCSR) A/D control register (ADCR) 18.3.1 A/D Data Registers A to D (ADDRA to ADDRD) There are four 16-bit read-only ADDR registers; ADDRA to ADDRD, used to store the results of A/D conversion.
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Section 18 A/D Converter 18.3.2 A/D Control/Status Register (ADCSR) ADCSR consists of the control bits and conversion end status bits of the A/D converter.
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Section 18 A/D Converter Bit Bit Name Initial Value R/W Description 2 CH2 0 R/W Channel Select 2 to 0 1 CH1 0 R/W Select analog input channels. 0 CH0 0 R/W When SCAN = 0 When SCAN = 1 000: AN0 000: AN0 001: AN1 001: AN0 and AN1 010: AN2 010: AN0 to AN2 011: AN3 011: AN0 to AN3 100: AN4 100: AN4 101: AN5 101: AN4 and AN5 110: AN6 110: AN4 to AN6 111: AN7 111: AN4 to AN7 18.3.
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Section 18 A/D Converter 18.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes; single mode and scan mode. When changing the operating mode or analog input channel, in order to prevent incorrect operation, first clear the bit ADST in ADCSR to 0. The ADST bit can be set at the same time as the operating mode or analog input channel is changed. 18.4.
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Section 18 A/D Converter 18.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (tD) has passed after the ADST bit is set to 1, then starts conversion. Figure 18.2 shows the A/D conversion timing. Table 18.3 shows the A/D conversion time. As indicated in figure 18.2, the A/D conversion time includes tD and the input sampling time.
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Section 18 A/D Converter Table 18.3 A/D Conversion Time (Single Mode) CKS = 0 Item Symbol Min A/D conversion start delay time tD Input sampling time tSPL A/D conversion time tCONV CKS = 1 Typ Max Min Typ Max 6 — 9 — 31 — 4 — 5 — 15 — 131 — 134 69 — 70 Note: All values represent the number of states. 18.4.4 External Trigger Input Timing A/D conversion can also be started by an external trigger input.
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Section 18 A/D Converter 18.5 A/D Conversion Accuracy Definitions This LSI's A/D conversion accuracy definitions are given below. • Resolution The number of A/D converter digital output codes • Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 18.4). • Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value 0000000000 to 0000000001 (see figure 18.5).
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Section 18 A/D Converter Digital output Ideal A/D conversion characteristic 111 110 101 100 011 010 Quantization error 001 000 1 8 2 8 3 8 4 8 5 8 6 8 7 FS 8 Analog input voltage Figure 18.4 A/D Conversion Accuracy Definitions (1) Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic Offset error FS Analog input voltage Figure 18.5 A/D Conversion Accuracy Definitions (2) Rev. 2.00 Sep.
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Section 18 A/D Converter 18.6 Usage Notes 18.6.1 Permissible Signal Source Impedance This LSI's analog input is designed such that conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 kΩ or less.
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Section 19 List of Registers Section 19 List of Registers The register list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. Register addresses (address order) • Registers are listed from the lower allocation addresses. • The symbol  in the register-name column represents a reserved address or range of reserved addresses. Do not attempt to access reserved addresses.
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Section 19 List of Registers 19.1 Register Addresses (Address Order) The data-bus width column indicates the number of bits. The access-state column shows the number of states of the selected basic clock that is required for access to the register. Note: Access to undefined or reserved addresses should not take place. Correct operation of the access itself or later operations is not guaranteed when such a register is accessed.
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Section 19 List of Registers Bit No Module Address Name Data Bus Width Access State GRA_1 16 H'F718 Timer Z 16 2 General register B_1 GRB_1 16 H'F71A Timer Z 16 2 General register C_1 GRC_1 16 H'F71C Timer Z 16 2 General register D_1 GRD_1 16 H'F71E Timer Z 16 2 Timer start register TSTR 8 H'F720 Timer Z 8 2 Timer mode register TMDR 8 H'F721 Timer Z 8 2 Timer PWM mode register TPMR 8 H'F722 Timer Z 8 2 Timer Z, for common use TFCR 8 H'F723 Timer Z 8
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Section 19 List of Registers Bit No Address Module Name Data Bus Width Access State ICCR1 8 H'F748 IIC2 8 2 I2C bus control register 2 ICCR2 8 H'F749 IIC2 8 2 I2C bus mode register ICMR 8 H'F74A IIC2 8 2 I2C bus interrupt enable register ICIER 8 H'F74B IIC2 8 2 I2C status register ICSR 8 H'F74C IIC2 8 2 Slave address register SAR 8 H'F74D IIC2 8 2 I2C bus transmit data register ICDRT 8 H'F74E IIC2 8 2 I2C bus receive data register ICDRR 8 H'F74F IIC2
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Section 19 List of Registers Bit No Address Module Name Data Bus Access Width State SMR 8 H'FFA8 SCI3 8 3 BRR 8 H'FFA9 SCI3 8 3 Register Abbreviation Serial mode register Bit rate register Serial control register 3 SCR3 8 H'FFAA SCI3 8 3 Transmit data register TDR 8 H'FFAB SCI3 8 3 Serial status register SSR 8 H'FFAC SCI3 8 3 Receive data register RDR 8 H'FFAD SCI3 8 3 — — — H'FFAE, H'FFAF — — — A/D data register ADDRA 16 H'FFB0 A/D converter 8 3 A/
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Section 19 List of Registers Bit No Address Module Name Data Bus Access Width State BDRL 8 H'FFCD Address break 8 2 PUCR1 8 H'FFD0 I/O port 8 2 Register Abbreviation Break data register L Port pull-up control register 1 Port pull-up control register 5 PUCR5 8 H'FFD1 I/O port 8 2 — — — H'FFD2, H'FFD3 — — — Port data register 1 PDR1 8 H'FFD4 I/O port 8 2 Port data register 2 PDR2 8 H'FFD5 I/O port 8 2 Port data register 3 PDR3 8 H'FFD6 I/O port 8 2 — — —
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Section 19 List of Registers Module Name Data Bus Width Access State Register Abbreviation System control register 1 SYSCR1 8 H'FFF0 Low power 8 2 System control register 2 SYSCR2 8 H'FFF1 Low power 8 2 Interrupt edge select register 1 IEGR1 8 H'FFF2 Interrupt 8 2 Interrupt edge select register 2 IEGR2 8 H'FFF3 Interrupt 8 2 Interrupt enable register 1 IENR1 8 H'FFF4 Interrupt 8 2 Interrupt enable register 2 IENR2 8 H'FFF5 Interrupt 8 2 Interrupt flag register 1
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Section 19 List of Registers 19.2 Register Bits The addresses and bit names of the registers in the on-chip peripheral modules are listed below. The 16-bit register is indicated in two rows, 8 bits for each row.
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Section 19 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name GRB_1 GRB1H7 GRB1H6 GRB1H5 GRB1H4 GRB1H3 GRB1H2 GRB1H1 GRB1H0 Timer Z GRB1L7 GRB1L6 GRB1L5 GRB1L4 GRB1L3 GRB1L2 GRB1L1 GRB1L0 GRC1H7 GRC1H6 GRC1H5 GRC1H4 GRC1H3 GRC1H2 GRC1H1 GRC1H0 GRC1L7 GRC1L6 GRC1L5 GRC1L4 GRC1L3 GRC1L2 GRC1L1 GRC1L0 GRD1H7 GRD1H6 GRD1H5 GRD1H4 GRD1H3 GRD1H2 GRD1H1 GRD1H0 GRD1L7 GRD1L6 GRD1L5 GRD1L4 GRD1L3 GRD1L2 GRD1L1 GRD1L0
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Section 19 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name SAR SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 FS IIC2 ICDRT ICDRT7 ICDRT6 ICDRT5 ICDRT4 ICDRT3 ICDRT2 ICDRT1 ICDRT0 ICDRR ICDRR7 ICDRR6 ICDRR5 ICDRR4 ICDRR3 ICDRR2 ICDRR1 ICDRR0 — — — — — — — — — — TMB1 TMB17 — — — — TMB12 TMB11 TMB10 Timer B1 TCB1 TCB17 TCB16 TCB15 TCB14 TCB13 TCB12 TCB11 TCB10 TLB1 TLB17 TLB16 TLB15 TLB14 TLB13 TLB12 TLB
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Section 19 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name ADDRC AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 A/D converter AD1 AD0 — — — — — — AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 — — — — — — ADDRD ADCSR ADF ADIE ADST SCAN CKS CH2 CH1 CH0 ADCR TRGE — — — — — — — — — — — — — — — — — PWDRL PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0 14-bit PWM PWDRU — — PWDRU5 PWDRU4 PWDRU3
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Section 19 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name PMR1 IRQ3 IRQ2 IRQ1 IRQ0 TXD2 PWM TXD TMOW I/O port PMR5 POF57 POF56 WKP5 WKP4 WKP3 WKP2 WKP1 WKP0 PMR3 — — — POF24 POF23 — — — PCR1 PCR17 PCR16 PCR15 PCR14 — PCR12 PCR11 PCR10 PCR2 — — — PCR24 PCR23 PCR22 PCR21 PCR20 PCR3 PCR37 PCR36 PCR35 PCR34 PCR33 PCR32 PCR31 PCR30 PCR5 PCR57*3 PCR56*3 PCR55 PCR54 PCR53 PCR52 PCR51 PCR50 PCR6
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Section 19 List of Registers 19.
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Section 19 List of Registers Register Name Reset Active Sleep Subactive Subsleep Standby Module RSECDR — — — — — — RTC RMINDR — — — — — — RHRDR — — — — — — RWKDR — — — — — — RTCCR1 — — — — — — RTCCR2 — — — — — — RTCCSR Initialized — — — — — SMR_2 Initialized — — Initialized Initialized Initialized BRR_2 Initialized — — Initialized Initialized Initialized SCR3_2 Initialized — — Initialized Initialized Initialized TDR_2 Initialize
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Section 19 List of Registers Register Name Reset Active Sleep Subactive Subsleep Standby Module TCRV0 Initialized — — Initialized Initialized Initialized Timer V TCSRV Initialized — — Initialized Initialized Initialized TCORA Initialized — — Initialized Initialized Initialized TCORB Initialized — — Initialized Initialized Initialized TCNTV Initialized — — Initialized Initialized Initialized TCRV1 Initialized — — Initialized Initialized Initialized SMR Init
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Section 19 List of Registers Register Name Reset Active Sleep Subactive Subsleep Standby Module PUCR1 Initialized — — — — — I/O port PUCR5 Initialized — — — — — PDR1 Initialized — — — — — PDR2 Initialized — — — — — PDR3 Initialized — — — — — PDR5 Initialized — — — — — PDR6 Initialized — — — — — PDR7 Initialized — — — — — PDR8 Initialized — — — — — PDRB Initialized — — — — — PMR1 Initialized — — — — — PMR5 Initialized —
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Section 20 Electrical Characteristics Section 20 Electrical Characteristics 20.1 Absolute Maximum Ratings Table 20.1 Absolute Maximum Ratings Item Symbol Value Unit Note Power supply voltage VCC –0.3 to +4.3 V * Analog power supply voltage AVCC –0.3 to +4.3 V Input voltage VIN –0.3 to VCC +0.3 V Port B –0.3 to AVCC +0.3 V X1 –0.3 to 4.
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Section 20 Electrical Characteristics (2) Power Supply Voltage and Operating Frequency Range φ w(kHz) φ osc(MHz) 18.0 16.384 8.192 4.096 4.0 3.0 3.6 3.0 Vcc(V) AVcc = 3.0 to 3.6V Active mode Sleep mode (When MA2 is SYSCR2 = 0) 3.6 Vcc(V) AVcc = 3.0 to 3.6V Subactive mode Subsleep mode φ (kHz) 2250 78.125 3.0 3.6 Vcc(V) AVcc = 3.0 to 3.6V Active mode Sleep mode (When MA2 is SYSCR2 = 1) (3) Analog Power Supply Voltage and A/D Converter Accuracy Guarantee Range φ osc(MHz) 18.0 4.0 3.0 3.
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Section 20 Electrical Characteristics 20.2.2 DC Characteristics Table 20.2 DC Characteristics (1) VCC = 3.0 to 3.6 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Values Item Symbol Input high VIH voltage Input low voltage VIL Applicable Pins Min. Typ. Max. Unit RES, NMI, WKP0 to WKP5, IRQ0 to IRQ3, ADTRG, TMIB1, TMRIV, TMCIV, FTIOA0 to FTIOD0, FTIOA1 to FTIOD1,SCK3, SCK3_2, TRGV Test Condition VCC × 0.8 — VCC + 0.
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Section 20 Electrical Characteristics Values Item Symbol Applicable Pins Input low voltage VIL Test Condition Min. Typ. Max. Unit RXD, RXD_2, SCL, SDA, P10 to P12, P14 to P17, P20 to P24, P30 to P37, P50 to P57, P60 to P67, P70 to P72, P74 to P76, P85 to P87 –0.3 — VCC × 0.3 V PB0 to PB7 –0.3 — VCC × 0.3 V OSC1 Output high voltage Output low voltage VOH VOL –0.3 — 0.
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Section 20 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition Min. Typ. Max. Unit Input/ output leakage current | IIL | OSC1, TMIB1, NMI, WKP0 to WKP5, IRQ0 to IRQ3, ADTRG, TRGV, TMRIV, TMCIV, FTIOA0 to FTIOD0, FTIOA1 to FTIOD1 RXD, SCK3, RXD_2, SCK3_2, SCL, SDA VIN = 0.5 V to (VCC – 0.5 V) — — 1.0 µA P10 to P12, P14 to P17, P20 to P24, P30 to P37, P50 to P57, P60 to P67, P70 to P72, P74 to P76, P85 to P87, VIN = 0.5 V to (VCC – 0.5 V) — — 1.
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Section 20 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition Min. Typ. Max. Unit Notes Sleep ISLEEP1 mode current consumpti on VCC Sleep mode 1 VCC = 3.3 V, fOSC = 18 MHz — 16.5 21.0 mA * Sleep mode 1 VCC = 3.3 V, fOSC = 10 MHz — 9.0 — ISLEEP2 VCC Sleep mode 2 VCC = 3.3 V, fOSC = 18 MHz — 1.3 2.5 Sleep mode 2 VCC = 3.3 V, fOSC = 10 MHz — 1.1 — VCC = 3.3 V 32-kHz crystal resonator (φSUB = φW/2) — 35.0 60.0 VCC = 3.
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Section 20 Electrical Characteristics Note: * Pin states during current consumption measurement are given below (excluding current in the pull-up MOS transistors and output buffers).
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Section 20 Electrical Characteristics Table 20.2 DC Characteristics (2) VCC = 3.0 to 3.6 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Item Symbol Allowable output low current (per pin) IOL Applicable Pins Output pins except port 6, SCL, and SDA Values Test Condition Min. Typ. Max. Unit — — 2.0 mA Port 6 — — 10.0 SCL, SDA — — 6.0 Output pins except port 6, SCL, and SDA — — 20.0 Port 6, SCL, and SDA — — 40.
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Section 20 Electrical Characteristics 20.2.3 AC Characteristics Table 20.3 AC Characteristics VCC = 3.0 to 3.6 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Item Symbol Applicable Pins System clock oscillation frequency fOSC OSC1, OSC2 System clock (φ) cycle time tcyc Values Test Condition Min. Typ. Max. Unit 4.0 — 18.0 MHz 1 — 64 tOSC — — 12.8 µs Subclock oscillation fW frequency X1, X2 — 32.768 — kHz Watch clock (φW) cycle time tW X1, X2 — 30.
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Section 20 Electrical Characteristics Item Symbol Applicable Pins RES pin low width tREL RES Values Typ. Max. Unit Reference Figure At power-on and in trc modes other than those below — — ms Figure 20.2 In active mode and 200 sleep mode operation — — ns Test Condition Min.
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Section 20 Electrical Characteristics Table 20.4 I2C Bus Interface Timing VCC = 3.6 to 3.6 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Values Max. Unit Reference Figure 12tcyc + 600 — — ns Figure 20.
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Section 20 Electrical Characteristics Table 20.5 Serial Communication Interface (SCI) Timing VCC = 3.0 to 3.6 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Item Input clock cycle Asynchronous Symbol Applicable Pins tScyc SCK3 Values Test Condition Min. Typ. Max. Unit Reference Figure 4 — — Figure 20.5 6 — — tcyc Figure 20.6 Clocked synchronous Input clock pulse width tSCKW SCK3 0.4 — 0.
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Section 20 Electrical Characteristics 20.2.4 A/D Converter Characteristics Table 20.6 A/D Converter Characteristics VCC = 3.0 to 3.6 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Item Symbol Applicable Pins Test Condition Values Min. Typ. Max. Unit Reference Figure V * Analog power supply AVCC voltage AVCC 3.0 VCC 3.6 Analog input voltage AVIN AN0 to AN7 VSS – 0.3 — AVCC + 0.3 V Analog power supply AIOPE current AVCC — 2.0 mA AVCC = 3.
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Section 20 Electrical Characteristics Notes: 1. Set AVCC = VCC when the A/D converter is not used. 2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle. 3. AISTOP2 is the current at reset and in standby, subactive, and subsleep modes while the A/D converter is idle. 20.2.5 Watchdog Timer Characteristics Table 20.7 Watchdog Timer Characteristics VCC = 3.0 to 3.6 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated.
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Section 20 Electrical Characteristics 20.2.6 Flash Memory Characteristics Table 20.8 Flash Memory Characteristics VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Values Test Condition Min. Typ. Max.
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Section 20 Electrical Characteristics Item Erasing Symbol Test Condition Values Min. Typ. Max.
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Section 20 Electrical Characteristics 20.3 Electrical Characteristics (Mask-ROM Version) 20.3.1 Power Supply Voltage and Operating Ranges (1) Power Supply Voltage and Oscillation Frequency Range φ osc(MHz) φ w(kHz) 18.0 32.768 4.0 3.0 3.6 AVcc = 3.0 to 3.6V Active mode Sleep mode Vcc(V) 3.0 3.6 Vcc(V) AVcc = 3.0 to 3.6V All operating modes Rev. 2.00 Sep.
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Section 20 Electrical Characteristics (2) Power Supply Voltage and Operating Frequency Range φ osc(MHz) φ w(kHz) 18.0 16.384 8.192 4.096 4.0 3.0 3.0 3.6 Vcc(V) AVcc = 3.0 to 3.6V Active mode Sleep mode (When MA2 in SYSCR2 = 0) 3.6 Vcc(V) AVcc = 3.0 to 3.6V Subactive mode Subsleep mode φ (kHz) 2250 78.125 3.0 3.6 Vcc(V) AVcc = 3.0 to 3.6V Active mode Sleep mode (When MA2 in SYSCR2 = 1) (3) Analog Power Supply Voltage and A/D Converter Accuracy Guarantee Range φ osc(MHz) 18.0 4.0 3.0 3.
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Section 20 Electrical Characteristics 20.3.2 DC Characteristics Table 20.9 DC Characteristics (1) VCC = 3.0 to 3.6 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Values Item Symbol Input high VIH voltage Applicable Pins Min. Typ. Max. Unit RES, NMI, WKP0 to WKP5, IRQ0 to IRQ3, ADTRG, TMIB1, TMRIV, TMCIV, FTIOA0 to FTIOD0, FTIOA1 to FTIOD1, SCK3, SCK3_2, TRGV Test Condition VCC × 0.8 — VCC + 0.
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Section 20 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition Min. Typ. Max. Unit Input high VIH voltage OSC1 VCC – 0.5 — VCC + 0.3 V Input low voltage RES, NMI, WKP0 to WKP5, IRQ0 to IRQ3, ADTRG, TMIB1, TMRIV, TMCIV, FTIOA0 to FTIOD0, FTIOA1 to FTIOD1, SCK3, SCK3_2, TRGV –0.3 — VCC × 0.2 V RXD, RXD_2, SCL, SDA, P10 to P12, P14 to P17, P20 to P24, P30 to P37, P50 to P57, P60 to P67,. P70 to P72, P74 to P76, P85 to P87 –0.3 — VCC × 0.3 V PB0 to PB7 –0.
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Section 20 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition Min. Typ. Max. Unit Output low voltage VOL P10 to P12, P14 to P17, P20 to P24, P30 to P37, P50 to P57, P70 to P72, P74 to P76, P85 to P87 IOL = 1.6 mA — — 0.6 V IOL = 0.4 mA — — 0.4 P60 to P67 IOL = 10.0 mA — — 1.0 IOL = 1.6 mA — — 0.4 SCL, SDA Input/ output leakage current | IIL | V IOL = 6.0 mA — — 0.6 IOL = 3.0 mA — — 0.
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Section 20 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition Min. Typ. Max. Unit Notes Active IOPE1 mode current consumption VCC Active mode 1 VCC = 3.3 V, fOSC = 18 MHz — 21.0 28.0 mA * Active mode 1 VCC = 3.3 V, fOSC = 10 MHz — 11.6 — IOPE2 VCC Active mode 2 VCC = 3.3 V, fOSC = 18 MHz — 1.4 2.8 Active mode 2 VCC = 3.3 V, fOSC = 10 MHz — 1.2 — Sleep mode 1 VCC = 3.3 V, fOSC = 18 MHz — 16.5 21.0 Sleep mode 1 VCC = 3.3 V, fOSC = 10 MHz — 9.
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Section 20 Electrical Characteristics Values Item Applicable Pins Test Condition Min. Typ. Max. Unit Notes ISTBY Standby mode current consumption VCC 32-kHz crystal resonator not used — — 5.0 µA * RAM data VRAM retaining voltage VCC 2.0 — — V Note: Symbol * Pin states during current consumption measurement are given below (excluding current in the pull-up MOS transistors and output buffers).
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Section 20 Electrical Characteristics Table 20.9 DC Characteristics (2) VCC = 3.0 to 3.6 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Values Item Symbol Applicable Pins Test Condition Min. Typ. Max. Unit Allowable output low current (per pin) IOL Output pins except port 6, SCL, and SDA — — 2.0 mA Port 6 — — 10.0 SCL, SDA — — 6.0 Output pins except port 6, SCL, and SDA — — 20.0 Port 6, SCL, and SDA — — 40.
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Section 20 Electrical Characteristics 20.3.3 AC Characteristics Table 20.10 AC Characteristics VCC = 3.0 to 3.6 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Item Symbol System clock oscillation frequency fOSC System clock (φ) cycle time tcyc Applicable Pins Test Condition OSC1, OSC2 Values Min. Typ. Max. Reference Unit Figure 4.0 — 18.0 MHz 1 — 64 tOSC — — 12.8 µs Subclock oscillation fW frequency X1, X2 — 32.
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Section 20 Electrical Characteristics Item Symbol Applicable Pins RES pin low width tREL RES Values Test Condition Min. Typ. Max. Unit Reference Figure At power-on and in modes other than those below trc — — ms Figure 20.
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Section 20 Electrical Characteristics Table 20.11 I2C Bus Interface Timing VCC = 3.0 V to 3.6 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Values Max. Unit Reference Figure 12tcyc + 600 — — ns Figure 20.
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Section 20 Electrical Characteristics Table 20.12 Serial Communication Interface (SCI) Timing VCC = 3.0 V to 3.6 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Item Input clock cycle Asynchronous Values Symbol Applicable Pins Test Condition Min. Typ. Max. Unit Reference Figure tScyc SCK3 4 — — Figure 20.5 6 — — tcyc Figure 20.6 Clocked synchronous Input clock pulse width tSCKW SCK3 0.4 — 0.
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Section 20 Electrical Characteristics 20.3.4 A/D Converter Characteristics Table 20.13 A/D Converter Characteristics VCC = 3.0 to 3.6 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Item Symbol Applicable Pins Test Condition Values Min. Typ. Max. Unit Reference Figure VCC 3.6 V * Analog power supply AVCC voltage AVCC 3.0 Analog input voltage AVIN AN0 to AN7 VSS – 0.3 — AVCC + 0.3 V Analog power supply AIOPE current AVCC — — 2.0 mA AVCC = 3.
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Section 20 Electrical Characteristics Notes: 1. Set AVCC = VCC when the A/D converter is not used. 2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle. 3. AISTOP2 is the current at reset and in standby, subactive, and subsleep modes while the A/D converter is idle. 20.3.5 Watchdog Timer Characteristics Table 20.14 Watchdog Timer Characteristics VCC = 3.0 to 3.6 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated.
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Section 20 Electrical Characteristics 20.4 Operation Timing t OSC VIH OSC1 VIL t CPH t CPL t CPf t CPr Figure 20.1 System Clock Input Timing VCC VCC × 0.7 OSC1 tREL RES VIL VIL tREL Figure 20.2 RES Low Width Timing NMI IRQ0 to IRQ3 WKP0 to WKP5 ADTRG FTIOA0 to FTIOD0, FTIOA1 to FTIOD1, TMCIV, TMRIV TRGV, TMIB1 VIH VIL t IL t IH Figure 20.3 Input Timing Rev. 2.00 Sep.
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Section 20 Electrical Characteristics VIH SDA VIL tBUF tSTAH tSCLH tSTAS tSP tSTOS SCL P* S* tSf Sr* tSCLL tSCL P* tSDAS tSr tSDAH Note: * S, P, and Sr represent the following: S: Start condition P: Stop condition Sr: Retransmission start condition Figure 20.4 I2C Bus Interface Input/Output Timing t SCKW SCK3 t Scyc Figure 20.5 SCK3 Input Clock Timing Rev. 2.00 Sep.
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Section 20 Electrical Characteristics t Scyc SCK3 VIH or VOH * VIL or VOL * t TXD TXD (transmit data) VOH* VOL * t RXS t RXH RXD (receive data) Note: * Output timing reference levels Output high: V OH= 2.0 V Output low: V OL= 0.8 V Load conditions are shown in figure 20.7. Figure 20.6 SCI Input/Output Timing in Clocked Synchronous Mode Rev. 2.00 Sep.
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Section 20 Electrical Characteristics 20.5 Output Load Condition VCC 2.4 kΩ LSI output pin 30 pF 12 k Ω Figure 20.7 Output Load Circuit Rev. 2.00 Sep.
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Appendix Appendix A Instruction Set A.
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Appendix Symbol Description ¬ NOT (logical complement) ( ), < > Contents of operand Note: General registers include 8-bit registers (R0H to R7H and R0L to R7L) and 16-bit registers (R0 to R7 and E0 to E7). Symbol Description ↔ • Condition Code Notation (cont) Changed according to execution result * Undetermined (no guaranteed value) 0 Cleared to 0 1 Set to 1 — Not affected by execution of the instruction ∆ Varies depending on conditions, described in notes Rev. 2.00 Sep.
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Appendix Table A.1 Instruction Set 1. Data Transfer Instructions Condition Code MOV.B @(d:16, ERs), Rd B 4 @(d:16, ERs) → Rd8 — — MOV.B @(d:24, ERs), Rd B 8 @(d:24, ERs) → Rd8 — — MOV.B @ERs+, Rd B @ERs → Rd8 ERs32+1 → ERs32 — — MOV.B @aa:8, Rd B 2 @aa:8 → Rd8 — — MOV.B @aa:16, Rd B 4 @aa:16 → Rd8 — — MOV.B @aa:24, Rd B 6 @aa:24 → Rd8 — — MOV.B Rs, @ERd B Rs8 → @ERd — — MOV.B Rs, @(d:16, ERd) B 4 Rs8 → @(d:16, ERd) — — MOV.
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Appendix No. of States*1 Condition Code — — @(d:24, ERs) → ERd32 — — @ERs → ERd32 ERs32+4 → ERs32 — — 6 @aa:16 → ERd32 — — 8 @aa:24 → ERd32 — — ERs32 → @ERd — — ERs32 → @(d:16, ERd) — — ERs32 → @(d:24, ERd) — — ERd32–4 → ERd32 ERs32 → @ERd — — 6 ERs32 → @aa:16 — — 8 ERs32 → @aa:24 — — 0 — 0 — POP POP.W Rn W 2 @SP → Rn16 SP+2 → SP — — POP.L ERn L 4 @SP → ERn32 SP+4 → SP — — 0 — PUSH PUSH.W Rn W 2 SP–2 → SP Rn16 → @SP — — 0 — PUSH.
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Appendix 2. Arithmetic Instructions No. of States*1 Condition Code Z V C ↔ ↔ — (2) ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ERd32+ERs32 → ERd32 — (2) ↔ ↔ (3) ↔ ↔ Rd16+Rs16 → Rd16 — (1) ERd32+#xx:32 → ERd32 Rd8+#xx:8 +C → Rd8 — 2 B 2 Rd8+Rs8 +C → Rd8 — ADDS ADDS.L #1, ERd L 2 ERd32+1 → ERd32 — — — — — — 2 ADDS.L #2, ERd L 2 ERd32+2 → ERd32 — — — — — — 2 ADDS.L #4, ERd L 2 ERd32+4 → ERd32 — — — — — — 2 INC.B Rd B 2 Rd8+1 → Rd8 — — INC.W #1, Rd W 2 Rd16+1 → Rd16 — — INC.
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Appendix No. of States*1 Condition Code Advanced V C ERd32–1 → ERd32 — — L 2 ERd32–2 → ERd32 — — ↔ ↔ — 2 DAS.Rd B 2 Rd8 decimal adjust → Rd8 — * ↔ ↔ ↔ 2 DEC.L #2, ERd ↔ ↔ ↔ — * — 2 B 2 Rd8 × Rs8 → Rd16 (unsigned multiplication) — — — — — — 14 W 2 Rd16 × Rs16 → ERd32 (unsigned multiplication) — — — — — — 22 B 4 Rd8 × Rs8 → Rd16 (signed multiplication) — — ↔ W 4 Rd16 × Rs16 → ERd32 (signed multiplication) — — B 2 W DIVXU DIVXU. B Rs, Rd DIVXU.
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Appendix No. of States*1 Condition Code W 2 0–Rd16 → Rd16 — NEG.L ERd L 2 0–ERd32 → ERd32 — EXTU EXTU.W Rd W 2 0 → ( of Rd16) — — 0 EXTU.L ERd L 2 0 → ( of ERd32) — — 0 EXTS EXTS.W Rd W 2 ( of Rd16) → ( of Rd16) — — EXTS.L ERd L 2 ( of ERd32) → ( of ERd32) — — Advanced ↔ ↔ ↔ NEG.W Rd Normal C ↔ ↔ ↔ — ↔ ↔ ↔ V ↔ ↔ ↔ ↔ 0–Rd8 → Rd8 2 0 — 2 ↔ 2 0 — 2 ↔ H B 0 — 2 ↔ Z ↔ I NEG NEG.
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Appendix 3. Logic Instructions AND.B Rs, Rd B AND.W #xx:16, Rd W 4 AND.W Rs, Rd W AND.L #xx:32, ERd L AND.L ERs, ERd L OR.B #xx:8, Rd B OR.B Rs, Rd B OR.W #xx:16, Rd W 4 OR.W Rs, Rd W OR.L #xx:32, ERd L OR.L ERs, ERd L XOR.B #xx:8, Rd B XOR.B Rs, Rd B XOR.W #xx:16, Rd W 4 XOR.W Rs, Rd W XOR.L #xx:32, ERd L XOR.L ERs, ERd L 4 ERd32⊕ERs32 → ERd32 — — NOT.B Rd B 2 ¬ Rd8 → Rd8 — — NOT.W Rd W 2 ¬ Rd16 → Rd16 — — NOT.
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Appendix 4. Shift Instructions W 2 SHAL.L ERd L 2 SHAR SHAR.B Rd B 2 SHAR.W Rd W 2 SHAR.L ERd L 2 SHLL SHLL.B Rd B 2 SHLL.W Rd W 2 SHLL.L ERd L 2 SHLR SHLR.B Rd B 2 SHLR.W Rd W 2 SHLR.L ERd L 2 ROTXL ROTXL.B Rd B 2 ROTXL.W Rd W 2 ROTXL.L ERd L 2 B 2 ROTXR.W Rd W 2 ROTXR.L ERd L 2 ROTL ROTL.B Rd B 2 ROTL.W Rd W 2 ROTL.L ERd L 2 ROTR ROTR.B Rd B 2 ROTR.W Rd W 2 ROTR.L ERd L 2 ROTXR ROTXR.
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Appendix 5.
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Appendix B BLD #xx:3, @aa:8 B BILD BILD #xx:3, Rd BST BILD #xx:3, @ERd B BILD #xx:3, @aa:8 B BST #xx:3, Rd B BST #xx:3, @ERd B BST #xx:3, @aa:8 B BIST BIST #xx:3, Rd B BIST #xx:3, @ERd B BIST #xx:3, @aa:8 B BAND BAND #xx:3, Rd B BAND #xx:3, @ERd B BAND #xx:3, @aa:8 B BIAND BIAND #xx:3, Rd BOR B B BIAND #xx:3, @ERd B BIAND #xx:3, @aa:8 B BOR #xx:3, Rd B BOR #xx:3, @ERd B BOR #xx:3, @aa:8 B BIOR BIOR #xx:3, Rd B BIOR #xx:3, @ERd B BIOR #xx:3, @aa:8 B BXOR BXOR #
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Appendix 6. Branching Instructions Bcc No.
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Appendix JMP BSR JSR RTS JMP @ERn — JMP @aa:24 — JMP @@aa:8 — BSR d:8 — BSR d:16 — JSR @ERn — JSR @aa:24 — JSR @@aa:8 — RTS — No.
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Appendix 7. System Control Instructions No.
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Appendix 8. Block Transfer Instructions EEPMOV No. of States*1 H N Z V C Normal — @@aa @(d, PC) I EEPMOV. B — 4 if R4L ≠ 0 then repeat @R5 → @R6 R5+1 → R5 R6+1 → R6 R4L–1 → R4L until R4L=0 else next — — — — — — 8+ 4n*2 EEPMOV.
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REJ09B0160-0200 Rev. 2.00 Sep. 23, 2005 Page 422 of 472 STC NOP XOR SUBX OR XOR AND MOV B C D E F BILD BIST BLD BST CMP BIAND BVC 8 MOV BVS 9 A B JMP BPL BMI MOV Table A.2 Table A.2 (2) (2) Table A.2 Table A.2 (2) (2) Table A.2 Table A.2 EEPMOV (2) (2) SUB ADD Table A.2 TRAPA (2) BEQ A BIXOR BAND AND RTE BNE MOV.B Table A.2 (2) LDC 7 ADDX BIOR BXOR OR BOR BSR BCS RTS BCC AND.B ANDC 6 9 BTST DIVXU BLS XOR.B XORC 5 ADD BCLR MULXU BHI OR.
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MOV 79 ADD BRA 58 MOV ADD DAS 1F 7A BRN SUBS 1B NOT 17 DEC ROTXR 13 1 1A ROTXL 12 DAA 0F SHLR ADDS 0B 11 INC 0A SHLL MOV 01 10 0 BH AH AL CMP CMP BHI 2 SUB SUB BLS NOT ROTXR ROTXL SHLR SHLL 3 4 XOR XOR OR OR BCS DEC EXTU INC 5 BCC LDC/STC 1st byte 2nd byte AH AL BH BL AND AND BNE 6 BEQ DEC EXTU INC 7 BVC SUB NEG 9 BVS ROTR ROTL SHAR SHAL ADDS SLEEP 8 BPL A MOV BMI NEG CMP SUB ROTR ROTL SHAR C D BGE BLT DEC EXTS I
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REJ09B0160-0200 Rev. 2.00 Sep. 23, 2005 Page 424 of 472 DIVXS 3 BSET 7Faa7 * 2 BNOT BNOT BCLR BCLR Notes: 1. r is the register designation field. 2. aa is the absolute address field.
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Appendix A.3 Number of Execution States The status of execution for each instruction of the H8/300H CPU and the method of calculating the number of states required for instruction execution are shown below. Table A.4 shows the number of cycles of each type occurring in each instruction, such as instruction fetch and data read/write. Table A.3 shows the number of states required for each cycle.
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Appendix Table A.3 Number of Cycles in Each Instruction Access Location Execution Status (Instruction Cycle) On-Chip Memory On-Chip Peripheral Module 2 — Instruction fetch SI Branch address read SJ Stack operation SK Byte data access SL 2 or 3* Word data access SM 2 or 3* Internal operation SN Note: * 1 Depends on which on-chip peripheral module is accessed. See section 19.1, Register Addresses (Address Order). Rev. 2.00 Sep.
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Appendix Table A.4 Number of Cycles in Each Instruction Instruction Branch Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic I J L M N ADD ADD.B #xx:8, Rd 1 ADD.B Rs, Rd 1 ADD.W #xx:16, Rd 2 ADD.W Rs, Rd 1 ADD.L #xx:32, ERd 3 ADD.L ERs, ERd 1 ADDS ADDS #1/2/4, ERd 1 ADDX ADDX #xx:8, Rd 1 ADDX Rs, Rd 1 AND.B #xx:8, Rd 1 AND.B Rs, Rd 1 AND.W #xx:16, Rd 2 AND.W Rs, Rd 1 AND.L #xx:32, ERd 3 AND.
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Appendix Instruction Branch Byte Data Word Data Internal Fetch Addr.
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Appendix Instruction Branch Byte Data Word Data Internal Fetch Addr.
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Appendix Instruction Branch Byte Data Word Data Internal Fetch Addr.
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Appendix Instruction Branch Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic I J L M N DEC DEC.B Rd 1 DEC.W #1/2, Rd 1 DEC.L #1/2, ERd 1 DIVXS.B Rs, Rd 2 12 DIVXS.W Rs, ERd 2 20 DIVXU DIVXU.B Rs, Rd 1 12 DIVXU.W Rs, ERd 1 EEPMOV EEPMOV.B 2 2n+2*1 EEPMOV.W 2 2n+2*1 EXTS.W Rd 1 EXTS.L ERd 1 DUVXS EXTS EXTU INC JMP JSR LDC EXTU.W Rd 1 EXTU.L ERd 1 INC.B Rd 1 INC.W #1/2, Rd 1 INC.
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Appendix Instruction Branch Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic I J L M N MOV MOV.B #xx:8, Rd 1 MOV.B Rs, Rd 1 MOV.B @ERs, Rd 1 1 MOV.B @(d:16, ERs), Rd 2 1 MOV.B @(d:24, ERs), Rd 4 1 MOV.B @ERs+, Rd 1 1 MOV.B @aa:8, Rd 1 1 MOV.B @aa:16, Rd 2 1 MOV.B @aa:24, Rd 3 1 MOV.B Rs, @Erd 1 1 MOV.B Rs, @(d:16, ERd) 2 1 MOV.B Rs, @(d:24, ERd) 4 1 MOV.B Rs, @-ERd 1 1 MOV Stack K 2 2 MOV.
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Appendix Instruction Mnemonic MOV Instruction Branch Byte Data Word Data Internal Fetch Addr. Read Operation Stack Access Access Operation I J L M N 2 K MOV.W Rs, @-ERd 1 1 MOV.W Rs, @aa:16 2 1 MOV.W Rs, @aa:24 3 1 MOV.L #xx:32, ERd 3 MOV.L ERs, ERd 1 MOV.L @ERs, ERd 2 2 MOV.L @(d:16,ERs), ERd 3 2 MOV.L @(d:24,ERs), ERd 5 2 MOV.L @ERs+, ERd 2 2 MOV.L @aa:16, ERd 3 2 MOV.L @aa:24, ERd 4 2 MOV.L ERs,@ERd 2 2 MOV.L ERs, @(d:16,ERd) 3 2 MOV.
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Appendix Instruction Branch Byte Data Word Data Internal Fetch Addr. Read Operation Stack Access Access Operation Instruction Mnemonic I J L M N OR OR.B #xx:8, Rd 1 OR.B Rs, Rd 1 OR.W #xx:16, Rd 2 OR.W Rs, Rd 1 OR.L #xx:32, ERd 3 K OR.L ERs, ERd 2 ORC ORC #xx:8, CCR 1 POP POP.W Rn 1 1 2 POP.L ERn 2 2 2 PUSH.W Rn 1 1 2 PUSH.L ERn 2 2 2 PUSH ROTL ROTR ROTXL ROTXR ROTL.B Rd 1 ROTL.W Rd 1 ROTL.L ERd 1 ROTR.B Rd 1 ROTR.W Rd 1 ROTR.
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Appendix Instruction Branch Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic I J L M N SHAR SHAR.B Rd 1 SHAR.W Rd 1 SHAR.L ERd 1 SHLL.B Rd 1 SHLL.W Rd 1 SHLL.L ERd 1 SHLL Stack K SHLR.B Rd 1 SHLR.W Rd 1 SHLR.L ERd 1 SLEEP SLEEP 1 STC STC CCR, Rd 1 STC CCR, @ERd 2 1 STC CCR, @(d:16,ERd) 3 1 STC CCR, @(d:24,ERd) 5 1 STC CCR,@-ERd 2 1 STC CCR, @aa:16 3 1 STC CCR, @aa:24 4 1 SUB.B Rs, Rd 1 SUB.
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Appendix Instruction Branch Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic I J L M N XOR XOR.B #xx:8, Rd 1 XOR.B Rs, Rd 1 XOR.W #xx:16, Rd 2 XOR.W Rs, Rd 1 XOR.L #xx:32, ERd 3 XORC XOR.L ERs, ERd 2 XORC #xx:8, CCR 1 Stack K Notes: 1. n: Specified value in R4L and R4. The source and destination operands are accessed n+1 times respectively. 2. Cannot be used in this LSI. Rev. 2.00 Sep.
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Appendix A.4 Combinations of Instructions and Addressing Modes Table A.5 Combinations of Instructions and Addressing Modes @@aa:8 — — — — — — — WL — BWL BWL — @(d:16.PC) — — — @aa:24 — — — B @aa:16 — — — @aa:8 @ERn+/@ERn @(d:24.ERn) @ERn BWL BWL BWL BWL BWL BWL — — — — — — — — — — — — @(d:8.PC) Data MOV transfer POP, PUSH instructions MOVFPE, Rn Instructions #xx Functions @(d:16.
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Appendix Appendix B I/O Port Block Diagrams B.1 I/O Port Block Diagrams RES goes low in a reset, and SBY goes low at reset and in standby mode. Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR IRQ TRGV [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.1 Port 1 Block Diagram (P17) Rev. 2.00 Sep.
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Appendix Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR IRQ [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.2 Port 1 Block Diagram (P14, P16) Rev. 2.00 Sep.
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Appendix Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR IRQ TMIB1 [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.3 Port 1 Block Diagram (P15) Rev. 2.00 Sep.
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Appendix Internal data bus RES SBY PUCR Pull-up MOS PDR PCR [Legend] PUCR: Port pull-up control register PDR: Port data register PCR: Port control register Figure B.4 Port 1 Block Diagram (P12) Rev. 2.00 Sep.
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Appendix Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR 14-bit PWM PWM [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.5 Port 2 Block Diagram (P11) Rev. 2.00 Sep.
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Appendix Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR RTC TMOW [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.6 Port 1 Block Diagram (P10) Rev. 2.00 Sep.
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Appendix Internal data bus SBY PMR PDR PCR [Legend] PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.7 Port 2 Block Diagram (P24, P23) Rev. 2.00 Sep.
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Appendix Internal data bus SBY PMR PDR PCR SCI3 TxD [Legend] PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.8 Port 2 Block Diagram (P22) Rev. 2.00 Sep.
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Appendix SBY Internal data bus PDR PCR SCI3 RE RxD [Legend] PDR: Port data register PCR: Port control register Figure B.9 Port 2 Block Diagram (P21) Rev. 2.00 Sep.
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Appendix SBY SCI3 SCKIE SCKOE Internal data bus PDR PCR SCKO SCKI [Legend] PDR: Port data register PCR: Port control register Figure B.10 Port 2 Block Diagram (P20) Rev. 2.00 Sep.
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Appendix Internal data bus SBY PDR PCR [Legend] PDR: Port data register PCR: Port control register Figure B.11 Port 3 Block Diagram (P37 to P30) Rev. 2.00 Sep.
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Appendix Internal data bus SBY PMR PDR PCR IIC2 ICE SDAO/SCLO SDAI/SCLI [Legend] PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.12 Port 5 Block Diagram (P57, P56) Rev. 2.00 Sep.
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Appendix Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR WKP ADTRG [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.13 Port 5 Block Diagram (P55) Rev. 2.00 Sep.
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Appendix Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR WKP [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.14 Port 5 Block Diagram (P54 to P50) Rev. 2.00 Sep.
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Appendix Internal data bus SBY Timer Z Output control signals A to D PDR PCR FTIOA to FTIOD [Legend] PDR: Port data register PCR: Port control register Figure B.15 Port 6 Block Diagram (P67 to P60) Rev. 2.00 Sep.
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Appendix Internal data bus SBY Timer V OS3 OS2 OS1 OS0 PDR PCR TMOV [Legend] PDR: Port data register PCR: Port control register Figure B.16 Port 7 Block Diagram (P76) Rev. 2.00 Sep.
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Appendix Internal data bus SBY PDR PCR Timer V TMCIV [Legend] PDR: Port data register PCR: Port control register Figure B.17 Port 7 Block Diagram (P75) Rev. 2.00 Sep.
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Appendix Internal data bus SBY PDR PCR Timer V TMRIV [Legend] PDR: Port data register PCR: Port control register Figure B.18 Port 7 Block Diagram (P74) Rev. 2.00 Sep.
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Appendix Internal data bus SBY PMR PDR PCR SCI3_2 TxD [Legend] PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.19 Port 7 Block Diagram (P72) Rev. 2.00 Sep.
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Appendix SBY Internal data bus PDR PCR SCI3_2 RE RxD [Legend] PDR: Port data register PCR: Port control register Figure B.20 Port 7 Block Diagram (P71) SBY SCI3_2 SCKIE SCKOE Internal data bus PDR PCR SCKO SCKI [Legend] PDR: Port data register PCR: Port control register Figure B.21 Port 7 Block Diagram (P70) Rev. 2.00 Sep.
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Appendix Internal data bus SBY PDR PCR [Legend] PDR: Port data register PCR: Port control register Figure B.22 Port 8 Block Diagram (P87 to P85) Rev. 2.00 Sep.
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Appendix Internal data bus A/D converter DEC CH3 to CH0 VIN Figure B.23 Port B Block Diagram (PB7 to PB0) Rev. 2.00 Sep.
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Appendix B.
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Appendix Appendix C Product Code Lineup Product Classification Product Code Model Marking Package Code H8/36087 Flash memory Standard version product HD64F36087H QFP-64 (FP-64A) HD64F36087FP DF36087FP LQFP-64 (FP-64E) Mask ROM version Standard product HD64336087H QFP-64 (FP-64A) HD64336087FP D336087(***)FP LQFP-64 (FP-64E) Mask ROM version Standard product HD64336086H QFP-64 (FP-64A) HD64336086FP D336086(***)FP LQFP-64 (FP-64E) Mask ROM version Standard product HD64336085H QFP-64 (F
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Appendix Appendix D Package Dimensions The package dimensions that are shown in the Renesas Semiconductor Packages Data Book have priority. Rev. 2.00 Sep.
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64 e ZD 1 y *3 bp Index mark D 16 33 x F M 17 32 E *2 49 48 *1 MASS[Typ.] 0.4g Detail F L1 L Terminal cross section b1 bp θ 0.5 L 1.0 1.25 ZE L1 1.25 ZD 0.7 0.08 8° 0.22 0.27 0.20 1.70 0.10 0.5 0.15 0.17 0.20 0.22 0.10 y 0.3 0° 0.12 0.17 0.00 12.2 12.2 Max x e θ c1 c b1 bp A1 A 12.0 12.0 11.8 11.8 A2 HE 10 1.45 E HD 10 Nom Dimension in Millimeters Min D Reference Symbol NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2.
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Figure D.2 FP-64A Package Dimensions 64 e 1 ZD D HD y *3 bp 16 33 x F M 17 32 E *2 49 48 *1 Previous Code FP-64A/FP-64AV MASS[Typ.] 1.2g Detail F L1 L Terminal cross section b1 bp θ 17.2 16.9 16.9 A2 HD HE 0.5 1.6 0.8 L L1 1.0 ZE 1.1 0.10 1.0 ZD 0.15 8° y 0.8 0.22 x e θ 0° 0.17 0.15 c c1 0.35 b1 0.12 0.29 bp 0.45 0.25 0.00 A1 0.37 3.05 17.5 17.5 Max A 0.10 17.2 14 2.70 E 14 Nom Dimension in Millimeters Min D Reference Symbol NOTE) 1.
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Main Revisions and Additions in this Edition Item Page Revision (See Manual for Details) Preface vi, vii When using the on-chip emulator (E7, E8) for H8/36087 program development and debugging, the following restrictions must be noted. 1. The NMI pin is reserved for the E7 or E8, and cannot be used. 3. Area H'D000 to H'DFFF is used by the E7 or E8, and is not available to the user. 5. When the E7 or E8 is used, address breaks can be set as either available to the user or for use by the E7 or E8.
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Item Page Revision (See Manual for Details) Section 13 Timer Z 181 13.3.2 Timer Mode Register (TMDR) Bit Bit Name Description 0 SYNC Timer Synchronization 0: TCNT_1 and TCNT_0 operate as a different timer 1: TCNT_1 and TCNT_0 are synchronized TCNT_1 and TCNT_0 can be pre-set or cleared synchronously 13.4.4 Synchronous Operation 208 13.4.9 Timer Z Output Timing 237 Figure 13.44 Example of Output Disable Timing of Timer Z by Writing to TOER Figure 13.
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Item Page Revision (See Manual for Details) 2 Section 17 I C Bus Interface 2 (IIC2) 320 Bit Bit Name Description 3 STOP 2 17.3.
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Item Page Revision (See Manual for Details) 20.3.2 DC Characteristics 395 Table 20.9 DC Characteristics (1) Mode RES Pin Internal State Active mode 1 VCC Operates Active mode 2 Sleep mode 1 Operates (φOSC/64) VCC Sleep mode 2 20.3.2 DC Characteristics 391 to Preliminary has been deleted. 20.3.3 AC Characteristics 402 20.3.4 A/D Converter Characteristics 20.3.5 Watchdog Timer Characteristics Appendix 463, D.1 Package Dimensions 464 Swapped with new ones. Rev. 2.00 Sep.
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Index Numerics 14-bit PWM ............................................ 257 Register settings.................................. 259 Waveform output................................ 260 A Effective address extension....................... 29 Exception handling ................................... 45 Reset exception handling ...................... 55 Stack status ........................................... 58 Trap instruction..................................... 45 A/D converter ..............................
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Slave address ...................................... 325 Start condition .................................... 325 Stop condition..................................... 325 Transfer rate........................................ 312 Instruction set ........................................... 19 Arithmetic operations instructions........ 21 Bit manipulation instructions................ 24 Block data transfer instructions ............ 28 Branch instructions ...............................
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ICDRS ................................................ 323 ICDRT ........................ 323, 360, 366, 370 ICIER.......................... 317, 360, 365, 370 ICMR.......................... 315, 360, 365, 370 ICSR ........................... 319, 360, 365, 370 IEGR1........................... 48, 363, 368, 372 IEGR2........................... 49, 363, 368, 372 IENR1........................... 50, 363, 368, 372 IENR2........................... 51, 363, 368, 372 IRR1 .............................
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S Serial communication interface 3 (SCI3) ..................................................... 261 Asynchronous mode ........................... 280 Bit rate ................................................ 271 Break .................................................. 305 Clocked synchronous mode................ 288 Framing error...................................... 284 Mark state ........................................... 305 Multiprocessor communication function..........................................
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Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8/36087 Group Publication Date: Rev.1.00, Jun. 03, 2004 Rev.2.00, Sep. 23, 2005 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp.  2005. Renesas Technology Corp., All rights reserved. Printed in Japan.
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Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES http://www.renesas.com Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.
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H8/36087 Group Hardware Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0160-0200