Datasheet

Section 13 Timer Z
Rev. 2.00 Sep. 23, 2005 Page 192 of 472
REJ09B0160-0200
Bit Bit Name
Initial
value R/W Description
3  1  Reserved
This bit is always read as 1.
2
1
0
IOC2
IOC1
IOC0
0
0
0
R/W
R/W
R/W
I/O Control C2 to C0
GRC is an output compare register:
000: Disables pin output by compare match
001: 0 output by GRC compare match
010: 1 output by GRC compare match
011: Toggle Output by GRC compare match
GRC is an input capture register:
100: Input capture to GRC at the rising edge
101: Input capture to GRC at the falling edge
11X: Input capture to GRC at both rising and falling
edges
[Legend]
X: Don't care
13.3.11 Timer Status Register (TSR)
TSR indicates generation of an overflow/underflow of TCNT and a compare match/input capture
of GRA, GRB, GRC, and GRD. These flags are interrupt sources. If an interrupt is enabled by a
corresponding bit in TIER, TSR requests an interrupt for the CPU. Timer Z has two TSR registers,
one for each channel.
Bit Bit Name
Initial
value R/W Description
7, 6  All 1  Reserved
These bits are always read as 1.
5 UDF* 0 R/W Underflow Flag
[Setting condition]
• When TCNT_1 underflows
[Clearing condition]
• When 0 is written to UDF after reading UDF = 1