Datasheet

Section 13 Timer Z
Rev. 2.00 Sep. 23, 2005 Page 195 of 472
REJ09B0160-0200
Bit Bit Name
Initial
value R/W Description
1 IMIEB 0 R/W Input Capture/Compare Match Interrupt Enable B
0: Interrupt requests (IMIB) by IMFB flag are disabled
1: Interrupt requests (IMIB) by IMFB flag are enabled
0 IMIEA 0 R/W Input Capture/Compare Match Interrupt Enable A
0: Interrupt requests (IMIA) by IMFA flag are disabled
1: Interrupt requests (IMIA) by IMFA flag are enabled
13.3.13 PWM Mode Output Level Control Register (POCR)
POCR control the active level in PWM mode. Timer Z has two POCR registers, one for each
channel.
Bit Bit Name
Initial
value R/W Description
7 to 3  All 1  Reserved
These bits are always read as 1.
2 POLD 0 R/W PWM Mode Output Level Control D
0: The output level of FTIOD is low-active
1: The output level of FTIOD is high-active
1 POLC 0 R/W PWM Mode Output Level Control C
0: The output level of FTIOC is low-active
1: The output level of FTIOC is high-active
0 POLB 0 R/W PWM Mode Output Level Control B
0: The output level of FTIOB is low-active
1: The output level of FTIOB is high-active