Datasheet

Section 13 Timer Z

Rev. 2.00 Sep. 23, 2005 Page 206 of 472

REJ09B0160-0200

FTIOA

TCNT value

Counter cleared by FTIOB input (rising edge)

Time

FTIOB

GRA H'0005

H'0005

H'0000

H'0160

GRB H'0180

H'0180

Figure 13.17 Example of Input Capture Operation

2. Input capture signal timing

Input capture on the rising edge, falling edge, or both edges can be selected through settings in

TIOR. Figure 13.18 shows the timing when the rising edge is selected. The pulse width of the

input capture signal must be at least two system clock (φ) cycles.