Datasheet

Rev. 2.00 Sep. 23, 2005 Page xxii of xxx
Figure 13.31 Example of Complementary PWM Mode Operation (1) ...................................... 222
Figure 13.32 (1) Example of Complementary PWM Mode Operation
(TPSC2 = TPSC1 = TPSC0 = 0) (2)................................................................ 224
Figure 13.32 (2) Example of Complementary PWM Mode Operation
(TPSC2 = TPSC1 = TPSC0 ≠ 0) (3) ................................................................ 225
Figure 13.33 Timing of Overshooting ........................................................................................ 226
Figure 13.34 Timing of Undershooting ...................................................................................... 226
Figure 13.35 Compare Match Buffer Operation......................................................................... 229
Figure 13.36 Input Capture Buffer Operation............................................................................. 230
Figure 13.37 Example of Buffer Operation Setting Procedure................................................... 230
Figure 13.38 Example of Buffer Operation (1)
(Buffer Operation for Output Compare Register) ................................................. 231
Figure 13.39 Example of Compare Match Timing for Buffer Operation ................................... 232
Figure 13.40 Example of Buffer Operation (2)
(Buffer Operation for Input Capture Register)...................................................... 233
Figure 13.41 Input Capture Timing of Buffer Operation............................................................ 234
Figure 13.42 Buffer Operation (3)
(Buffer Operation in Complementary PWM Mode CMD1 = CMD0 = 1)............ 235
Figure 13.43 Buffer Operation (4)
(Buffer Operation in Complementary PWM Mode CMD1 = CMD0 = 1)............ 236
Figure 13.44 Example of Output Disable Timing of Timer Z by Writing to TOER .................. 237
Figure 13.45 Example of Output Disable Timing of Timer Z by External Trigger.................... 237
Figure 13.46 Example of Output Inverse Timing of Timer Z by Writing to TFCR ................... 238
Figure 13.47 Example of Output Inverse Timing of Timer Z by Writing to POCR................... 238
Figure 13.48 IMF Flag Set Timing when Compare Match Occurs ............................................ 239
Figure 13.49 IMF Flag Set Timing at Input Capture .................................................................. 240
Figure 13.50 OVF Flag Set Timing............................................................................................ 240
Figure 13.51 Status Flag Clearing Timing.................................................................................. 241
Figure 13.52 Contention between TCNT Write and Clear Operations....................................... 242
Figure 13.53 Contention between TCNT Write and Increment Operations ............................... 243
Figure 13.54 Contention between GR Write and Compare Match............................................. 244
Figure 13.55 Contention between TCNT Write and Overflow................................................... 245
Figure 13.56 Contention between GR Read and Input Capture.................................................. 246
Figure 13.57 Contention between Count Clearing and Increment Operations by Input
Capture .................................................................................................................. 247
Figure 13.58 Contention between GR Write and Input Capture................................................. 248
Figure 13.59 When Compare Match and Bit Manipulation Instruction to TOCR Occur at the
Same Timing ......................................................................................................... 250