Datasheet

Section 13 Timer Z
Rev. 2.00 Sep. 23, 2005 Page 208 of 472
REJ09B0160-0200
No
Yes
Synchronous operation
selection
Clearing
source generation
channel?
Set synchronous
operation
Select counter
clearing source
Synchronous presetting
Set TCNT
Synchronous clearing
[1]
[2]
[3]
Select counter
clearing source
[4]
Start counter operation
[5]
Start counter operation
[5]
[1] Set the SYNC bits in TMDR to 1.
[2] When a value is written to either of the TCNT counters, the same value is simultaneously written to the
other TCNT counter.
[3] Set bits CCLR1 and CCLR0 in TCR to specify counter clearing by compare match/input capture.
[4] Set bits CCLR1 and CCLR0 in TCR to designate synchronous clearing for the counter clearing source.
[5] Set the STR bit in TSTR to 1 to start the count operation.
<Synchronous presetting> <Synchronous clearing><Counter clearing>
Figure 13.19 Example of Synchronous Operation Setting Procedure
Figure 13.20 shows an example of synchronous operation. In this example, synchronous operation
has been selected, FTIOB0 and FTIOB1 have been designated for PWM mode, GRA_0 compare
match has been set as the channel 0 counter clearing source, and synchronous clearing has been set
for the channel 1 counter clearing source. In addition, the same input clock has been set as the
counter input clock for channel 0 and channel 1. Two-phase PWM waveforms are output from
pins FTIOB0 and FTIOB1. At this time, synchronous presetting and synchronous operation by
GRA_0 compare match are performed by TCNT counters.
For details on PWM mode, see section 13.4.5, PWM Mode.