Datasheet

Section 13 Timer Z
Rev. 2.00 Sep. 23, 2005 Page 209 of 472
REJ09B0160-0200
GRA_0
Time
Synchronous clearing by GRA_0 compare match
TCNT values
GRA_1
GRB_0
GRB_1
H'0000
FTIOB0
FTIOB1
Figure 13.20 Example of Synchronous Operation
13.4.5 PWM Mode
In PWM mode, PWM waveforms are output from the FTIOB, FTIOC, and FTIOD output pins
with GRA as a cycle register and GRB, GRC, and GRD as duty registers. The initial output level
of the corresponding pin depends on the setting values of TOCR and POCR. Table 13.3 shows an
example of the initial output level of the FTIOB0 pin.
The output level is determined by the POLB to POLD bits corresponding to POCR. When POLB
is 0, the FTIOB output pin is set to 0 by compare match B and set to 1 by compare match A.
When POLB is 1, the FTIOB output pin is set to 1 by compare match B and cleared to 0 by
compare match A. In PWM mode, maximum 6-phase PWM outputs are possible.
Figure 13.21 shows an example of the PWM mode setting procedure.