Datasheet

Rev. 2.00 Sep. 23, 2005 Page xxiv of xxx
Figure 17.4 I
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C Bus Timing........................................................................................................ 324
Figure 17.5 Master Transmit Mode Operation Timing (1)......................................................... 326
Figure 17.6 Master Transmit Mode Operation Timing (2)......................................................... 326
Figure 17.7 Master Receive Mode Operation Timing (1) .......................................................... 328
Figure 17.8 Master Receive Mode Operation Timing (2) .......................................................... 329
Figure 17.9 Slave Transmit Mode Operation Timing (1) ........................................................... 330
Figure 17.10 Slave Transmit Mode Operation Timing (2) ......................................................... 331
Figure 17.11 Slave Receive Mode Operation Timing (1)........................................................... 332
Figure 17.12 Slave Receive Mode Operation Timing (2)........................................................... 333
Figure 17.13 Clocked Synchronous Serial Transfer Format....................................................... 333
Figure 17.14 Transmit Mode Operation Timing......................................................................... 334
Figure 17.15 Receive Mode Operation Timing .......................................................................... 335
Figure 17.16 Block Diagram of Noise Conceler ........................................................................ 336
Figure 17.17 Sample Flowchart for Master Transmit Mode ...................................................... 337
Figure 17.18 Sample Flowchart for Master Receive Mode ........................................................ 338
Figure 17.19 Sample Flowchart for Slave Transmit Mode......................................................... 339
Figure 17.20 Sample Flowchart for Slave Receive Mode .......................................................... 340
Figure 17.21 The Timing of the Bit Synchronous Circuit .......................................................... 342
Section 18 A/D Converter
Figure 18.1 Block Diagram of A/D Converter ........................................................................... 346
Figure 18.2 A/D Conversion Timing.......................................................................................... 352
Figure 18.3 External Trigger Input Timing ................................................................................ 353
Figure 18.4 A/D Conversion Accuracy Definitions (1).............................................................. 355
Figure 18.5 A/D Conversion Accuracy Definitions (2).............................................................. 355
Figure 18.6 Analog Input Circuit Example ................................................................................ 356
Section 20 Electrical Characteristics
Figure 20.1 System Clock Input Timing .................................................................................... 403
Figure 20.2 RES Low Width Timing.......................................................................................... 403
Figure 20.3 Input Timing............................................................................................................ 403
Figure 20.4 I
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C Bus Interface Input/Output Timing ................................................................... 404
Figure 20.5 SCK3 Input Clock Timing ...................................................................................... 404
Figure 20.6 SCI Input/Output Timing in Clocked Synchronous Mode...................................... 405
Figure 20.7 Output Load Circuit ................................................................................................ 406
Appendix
Figure B.1 Port 1 Block Diagram (P17) ..................................................................................... 438
Figure B.2 Port 1 Block Diagram (P14, P16) ............................................................................. 439
Figure B.3 Port 1 Block Diagram (P15) ..................................................................................... 440
Figure B.4 Port 1 Block Diagram (P12) ..................................................................................... 441
Figure B.5 Port 2 Block Diagram (P11) ..................................................................................... 442