Datasheet

Section 13 Timer Z
Rev. 2.00 Sep. 23, 2005 Page 241 of 472
REJ09B0160-0200
13.5.2 Status Flag Clearing Timing
The status flag can be cleared by writing 0 after reading 1 from the CPU. Figure 13.51 shows the
timing in this case.
Address TSR address
φ
WTSR
(internal write signal)
IMF, OVF
ITMZ
Figure 13.51 Status Flag Clearing Timing