Datasheet

Section 13 Timer Z
Rev. 2.00 Sep. 23, 2005 Page 242 of 472
REJ09B0160-0200
13.6 Usage Notes
1. Contention between TCNT Write and Clear Operations: If a counter clear signal is generated
in the T
2
state of a TCNT write cycle, TCNT clearing has priority and the TCNT write is not
performed. Figure 13.52 shows the timing in this case.
T1 T2
TCNT
TCNT write cycle
TCNT address
WTCNT
(internal write signal)
Clearing has priority.
Counter clear signal
N H'0000
φ
Figure 13.52 Contention between TCNT Write and Clear Operations