Datasheet

Section 13 Timer Z
Rev. 2.00 Sep. 23, 2005 Page 246 of 472
REJ09B0160-0200
5. Contention between GR Read and Input Capture: If an input capture signal is generated in the
T
1
state of a GR read cycle, the data that is read will be transferred before input capture
transfer. Figure 13.56 shows the timing in this case.
T 1 T 2
GR
GR read cycle
GR address
Internal read
signal
Input capture
signal
Internal data
bus
X
X
M
φ
Figure 13.56 Contention between GR Read and Input Capture