Datasheet

Section 13 Timer Z
Rev. 2.00 Sep. 23, 2005 Page 248 of 472
REJ09B0160-0200
7. Contention between GR Write and Input Capture: If an input capture signal is generated in the
T
2
state of a GR write cycle, the input capture operation has priority and the write to GR is not
performed. Figure 13.58 shows the timing in this case.
T 1 T 2
TCNT N
GR write cycle
GR address
Input capture
signal
WGR
(internal write signal)
Address bus
GR write data
GR
M
φ
Figure 13.58 Contention between GR Write and Input Capture
8. Notes on Setting Reset Synchronous PWM Mode/Complementary PWM Mode: When bits
CMD1 and CMD0 in TFCR are set, note the following:
A. Write bits CMD1 and CMD0 while TCNT_1 and TCNT_0 are halted.
B. Changing the settings of reset synchronous PWM mode to complementary PWM mode or
vice versa is disabled. Set reset synchronous PWM mode or complementary PWM mode
after the normal operation (bits CMD1 and CMD0 are cleared to 0) has been set.
9. Note on Clearing TSR Flag: When a specific flag in TSR is cleared, a combination of the
BCLR or MOV instructions is used to read 1 from the flag and then write 0 to the flag.
However, if another bit is set during this processing, the bit may also be cleared
simultaneously. To avoid this, the following processing that does not use the BCLR
instruction must be executed. Note that this note is only applied to the F-ZTAT version. This
problem has already been solved in the mask ROM version.
Example: When clearing bit 4 (OVF) in TSR
MOV.B @TSR,R0L