Datasheet

Section 16 Serial Communication Interface 3 (SCI3)
Rev. 2.00 Sep. 23, 2005 Page 263 of 472
REJ09B0160-0200
Clock
TXD
RXD
SCK3
BRR
SMR
SCR3
SSR
TDR
RDR
TSR
RSR
Transmit/receive
control circuit
Internal data bus
[Legend]
RSR:
RDR:
TSR:
TDR:
SMR:
SCR3:
SSR:
BRR:
BRC:
Receive shift register
Receive data register
Transmit shift register
Transmit data register
Serial mode register
Serial control register 3
Serial status register
Bit rate register
Bit rate counter
Interrupt request
(TEI, TXI, RXI, ERI)
Internal clock (ø/64, ø/16, ø/4, ø)
External
clock
BRC
Baud rate generator
Figure 16.1 Block Diagram of SCI3