Datasheet

Rev. 2.00 Sep. 23, 2005 Page xxviii of xxx
Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is
Possible................................................................................................................... 96
Table 7.4 Reprogram Data Computation Table .................................................................... 100
Table 7.5 Additional-Program Data Computation Table...................................................... 100
Table 7.6 Programming Time............................................................................................... 100
Table 7.7 Flash Memory Operating States............................................................................ 105
Section 10 Realtime Clock (RTC)
Table 10.1 Pin Configuration.................................................................................................. 143
Table 10.2 Interrupt Source .................................................................................................... 152
Section 11 Timer B1
Table 11.1 Pin Configuration.................................................................................................. 154
Table 11.2 Timer B1 Operating Modes .................................................................................. 157
Section 12 Timer V
Table 12.1 Pin Configuration.................................................................................................. 161
Table 12.2 Clock Signals to Input to TCNTV and Counting Conditions ............................... 163
Section 13 Timer Z
Table 13.1 Timer Z Functions ................................................................................................ 174
Table 13.2 Pin Configuration.................................................................................................. 178
Table 13.3 Initial Output Level of FTIOB0 Pin...................................................................... 210
Table 13.4 Output Pins in Reset Synchronous PWM Mode................................................... 215
Table 13.5 Register Settings in Reset Synchronous PWM Mode........................................... 215
Table 13.6 Output Pins in Complementary PWM Mode........................................................ 219
Table 13.7 Register Settings in Complementary PWM Mode................................................ 219
Table 13.8 Register Combinations in Buffer Operation ......................................................... 229
Section 15 14-Bit PWM
Table 15.1 Pin Configuration.................................................................................................. 258
Section 16 Serial Communication Interface 3 (SCI3)
Table 16.1 Channel Configuration.......................................................................................... 262
Table 16.2 Pin Configuration.................................................................................................. 264
Table 16.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ...... 272
Table 16.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ...... 273
Table 16.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (3) ...... 275
Table 16.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) .......................... 277
Table 16.5 Examples of BRR Settings for Various Bit Rates (Clocked Synchronous Mode)
(1) ......................................................................................................................... 278
Table 16.5 Examples of BRR Settings for Various Bit Rates (Clocked Synchronous Mode)
(2) ......................................................................................................................... 279