Datasheet

Section 17 I
2
C Bus Interface 2 (IIC2)
Rev. 2.00 Sep. 23, 2005 Page 310 of 472
REJ09B0160-0200
17.2 Input/Output Pins
Table 17.1 summarizes the input/output pins used by the I
2
C bus interface 2.
Table 17.1 I
2
C Bus Interface Pins
Name Abbreviation I/O Function
Serial clock SCL I/O IIC serial clock input/output
Serial data SDA I/O IIC serial data input/output
Note: SCL and SDA pins are NMOS open drains, when the bus drive function is selected.
However the voltage which can be applied to these pins depends on the voltage of the
power supply (V
CC
) of this LSI.
17.3 Register Descriptions
The I
2
C bus interface 2 has the following registers:
• I
2
C bus control register 1 (ICCR1)
• I
2
C bus control register 2 (ICCR2)
• I
2
C bus mode register (ICMR)
• I
2
C bus interrupt enable register (ICIER)
• I
2
C bus status register (ICSR)
• I
2
C bus slave address register (SAR)
• I
2
C bus transmit data register (ICDRT)
• I
2
C bus receive data register (ICDRR)
• I
2
C bus shift register (ICDRS)