Datasheet

Rev. 2.00 Sep. 23, 2005 Page 466 of 354
REJ09B0160-0200
Item Page Revision (See Manual for Details)
Bit Bit Name Description
0 SYNC Timer Synchronization
0: TCNT_1 and TCNT_0 operate as a different
timer
1: TCNT_1 and TCNT_0 are synchronized
TCNT_1 and TCNT_0 can be pre-set or
cleared synchronously
Section 13 Timer Z
13.3.2 Timer Mode
Register (TMDR)
181
13.4.4 Synchronous
Operation
208 Figure 13.20 shows an example of synchronous operation. In
this example, synchronous operation has been selected,
FTIOB0 and FTIOB1 have been designated for PWM mode,
GRA_0 compare match has been set as the channel 0
counter clearing source, and synchronous clearing has been
set for the channel 1 counter clearing source. In addition, the
same input clock has been set as the counter input clock for
channel 0 and channel 1. Two-phase PWM waveforms are
output from pins FTIOB0 and FTIOB1.
13.4.9 Timer Z Output
Timing
Figure 13.44 Example of
Output Disable Timing of
Timer Z by Writing to
TOER
237
φ
Timer Z
output pin
Timer output
Address bus TOER address
T
1 T 2
I/O port
Timer Z output
I/O port
Figure 13.45 Example of
Output Disable Timing of
Timer Z by External Trigger
237
φ
TOER N
Timer Z
output pin
Timer Z output
Timer Z output
I/O port
I/O port
H'FF
Bit Bit Name
Description
4 TCSRWE
Timer Control/Status Register WD Write Enable
Section 14 Watchdog
Timer
14.2.1 Timer Control/Status
Register WD (TCSRWD)
252