Datasheet

Rev. 2.00 Sep. 23, 2005 Page 467 of 354
REJ09B0160-0200
Item Page Revision (See Manual for Details)
Bit Bit Name Description
3 STOP [Setting Conditions]
• In master mode, when a stop condition is
detected after frame transfer
• In slave mode, when a stop condition is
detected after the general call address or the
first byte slave address, next to detection of
start condition, accords with the address set
in SAR
[Clearing Condition]
• When 0 is written in STOP after reading
STOP = 1
Section 17 I
2
C Bus
Interface 2 (IIC2)
17.3.5 I
2
C Bus Status
Register (ICSR)
320
17.7 Usage Notes 343 Added
Section 18 A/D Converter
18.3.1 A/D Data Registers
A to D (ADDRA to
ADDRD)
348 Therefore byte access to ADDR should be done by reading the
upper byte first then the lower one. Word access is also
possible. ADDR is initialized to H'0000.
Mode RES Pin Internal State
Active mode 1 Operates
Active mode 2
V
CC
Operates
(φOSC/64)
Sleep mode 1 Only timers operate
Sleep mode 2
V
CC
Only timers operate
(φOSC/64)
Section 20 Electrical
Characteristics
20.2.2 DC Characteristics
Table 20.2 DC
Characteristics (1)
379