To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.
Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office.
User’s Manual The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8/36109 Group 16 Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Tiny Series H8/36109F HD64F36109 HD64F36109G Rev.1.50 2007.
Rev. 1.50 Sep.
Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2.
General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins.
Configuration of This Manual This manual comprises the following items: 1. 2. 3. 4. 5. 6. General Precautions on Handling of Product Configuration of This Manual Preface Contents Overview Description of Functional Modules • CPU and System-Control Modules • On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module.
Preface The H8/36109 Group are single-chip microcomputers made up of the high-speed H8/300H CPU employing Renesas Technology original architecture as their cores, and the peripheral functions required to configure a system. The H8/300H CPU has an instruction set that is compatible with the H8/300 CPU. Target Users: This manual was written for users who will be using the H8/36109 Group in the design of application systems.
Notes: When using an on-chip emulator (E7, E8) for H8/36109 program development and debugging, the following restrictions must be noted. 1. The NMI pin is reserved for the E7 or E8, and cannot be used. 2. Pins P85, P86, and P87 cannot be used. In order to use these pins, additional hardware must be provided on the user board. 3. Area H'01F000 to H'01FFFF is used by the E7 or E8, and is not available to the user. 4. Area H'F780 to H'FB7F must on no account be accessed. 5.
Application notes: Document Title Document No. H8S, H8/300 Series C/C++ Compiler Package Application Note TM Single Power Supply F-ZTAT On-Board Programming REJ05B0464 REJ05B0520 All trademarks and registered trademarks are the property of their respective owners. Rev. 1.50 Sep.
Contents Section 1 Overview................................................................................................1 1.1 1.2 1.3 1.4 Features.................................................................................................................................. 1 Internal Block Diagram.......................................................................................................... 3 Pin Assignment ...................................................................................
3.3 3.4 3.5 3.2.4 Interrupt Enable Register 2 (IENR2) ...................................................................... 51 3.2.5 Interrupt Flag Register 1 (IRR1)............................................................................. 51 3.2.6 Interrupt Flag Register 2 (IRR2)............................................................................. 53 3.2.7 Wakeup Interrupt Flag Register (IWPR) ................................................................ 53 3.2.
5.6 5.7 5.8 Subclock Generator.............................................................................................................. 86 5.6.1 Connecting 32.768-kHz Crystal Resonator............................................................. 86 5.6.2 Pin Connection when not Using Subclock.............................................................. 87 Prescaler............................................................................................................................... 87 5.7.
7.4 7.5 7.6 7.7 Flash Memory Programming/Erasing................................................................................ 115 7.4.1 Programming/Program-Verify.............................................................................. 115 7.4.2 Erasure/Erase-Verify ............................................................................................ 118 7.4.3 Interrupt Handling when Programming/Erasing Flash Memory........................... 118 Programming/Erasing Protection.............
9.7 9.8 9.9 9.10 9.11 9.12 9.13 9.6.1 Port Control Register 8 (PCR8) ............................................................................ 147 9.6.2 Port Data Register 8 (PDR8)................................................................................. 148 9.6.3 Pin Functions ........................................................................................................ 148 Port C ....................................................................................................
10.3.4 Day-of-Week Data Register (RWKDR) ............................................................... 191 10.3.5 RTC Control Register 1 (RTCCR1) ..................................................................... 192 10.3.6 RTC Control Register 2 (RTCCR2) ..................................................................... 193 10.3.7 Clock Source Select Register (RTCCSR)............................................................. 194 10.4 Operation ....................................................
Section 13 Timer RC .........................................................................................217 13.1 Features.............................................................................................................................. 217 13.2 Input/Output Pins ............................................................................................................... 220 13.3 Register Descriptions .........................................................................................
14.3.5 Timer RD Output Master Enable Register 1 (TRDOER1) ................................... 282 14.3.6 Timer RD Output Master Enable Register 2 (TRDOER2) ................................... 284 14.3.7 Timer RD Output Control Register (TRDOCR)................................................... 284 14.3.8 Timer RD Counter (TRDCNT)............................................................................. 286 14.3.9 General Registers A, B, C, and D (GRA, GRB, GRC, and GRD)........................ 286 14.3.
Section 16 14-Bit PWM.....................................................................................365 16.1 Features.............................................................................................................................. 365 16.2 Input/Output Pin................................................................................................................. 365 16.3 Register Descriptions ............................................................................................
17.8.3 Receive Error Flags and Transmit Operations (Clock Synchronous Mode Only) ......................................................................... 404 17.8.4 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode..................................................................................................................... 405 Section 18 I2C Bus Interface 2 (IIC2)................................................................ 407 18.1 Features..................................
19.4.3 Input Sampling and A/D Conversion Time .......................................................... 451 19.4.4 External Trigger Input Timing.............................................................................. 452 19.5 A/D Conversion Accuracy Definitions .............................................................................. 453 19.6 Usage Notes ....................................................................................................................... 456 19.6.
Appendix A. B. C. D. ......................................................................................................... 521 Instruction Set .................................................................................................................... 521 A.1 Instruction List...................................................................................................... 521 A.2 Operation Code Map...........................................................................................
Figures Section 1 Figure 1.1 Figure 1.2 Figure 1.3 Overview Internal Block Diagram ................................................................................................. 3 Pin Assignments (FP-100A).......................................................................................... 4 Pin Assignments (FP-100U).......................................................................................... 5 Section 2 CPU Figure 2.1 Memory Map........................................................
Figure 5.4 Flowchart of Clock Switching (From External Clock to On-Chip Oscillator Clock)................................................... 79 Figure 5.5 Timing Chart of Switching from On-Chip Oscillator Clock to External Clock .......... 80 Figure 5.6 Timing Chart to Switch from External Clock to On-Chip Oscillator Clock ............... 81 Figure 5.7 Example of Trimming Flow for On-Chip Oscillator Frequency ................................. 82 Figure 5.
Section 10 Figure 10.1 Figure 10.2 Figure 10.3 Figure 10.4 Realtime Clock (RTC) Block Diagram of RTC ........................................................................................... 187 Definition of Time Expression ................................................................................ 192 Initial Setting Procedure .......................................................................................... 195 Example: Reading of Inaccurate Time Data......................................
Figure 13.17 Figure 13.18 Figure 13.19 Figure 13.20 Figure 13.21 Figure 13.22 Figure 13.23 Figure 13.24 Figure 13.25 Figure 13.26 Figure 13.27 Figure 13.28 Figure 13.29 Figure 13.30 Figure 13.31 Figure 13.32 Figure 13.33 Figure 13.34 Figure 13.35 Example (1) of TRGC Synchronous Operation in PWM2 Mode.......................... 250 Example (2) of TRGC Synchronous Operation in PWM2 Mode.......................... 250 Example of Stopping Operation of the Counter in PWM2 Mode .........................
Figure 14.16 Figure 14.17 Figure 14.18 Figure 14.19 Figure 14.20 Figure 14.21 Figure 14.22 Figure 14.23 Figure 14.24 Figure 14.25 Figure 14.26 Figure 14.27 Figure 14.28 Figure 14.29 Figure 14.30 Figure 14.31 Figure 14.32 Figure 14.33 Figure 14.34 Figure 14.35 Figure 14.36 Figure 14.37 Figure 14.38 Figure 14.39 Figure 14.40 Figure 14.41 Figure 14.42 Figure 14.43 Figure 14.44 Figure 14.45 Figure 14.46 Figure 14.47 Figure 14.48 Figure 14.49 Figure 14.50 Figure 14.51 Example of 0 Output/1 Output Operation ....
Figure 14.52 Figure 14.53 Figure 14.54 Figure 14.55 Figure 14.56 Figure 14.57 Figure 14.58 Figure 14.59 Figure 14.60 Figure 14.61 Figure 14.62 Figure 14.63 Figure 14.64 Figure 14.65 Figure 14.66 Figure 14.67 Figure 14.68 Figure 14.69 Example of Output Inverse Timing of Timer RD by Writing to TRDFCR........... 345 Example of Output Inverse Timing of Timer RD by Writing to POCR................ 345 Block Diagram of Digital Filter ............................................................................
Figure 17.8 Sample Serial Reception Data Flowchart (Asynchronous Mode) (1)...................... 389 Figure 17.8 Sample Serial Reception Data Flowchart (Asynchronous Mode) (2)...................... 390 Figure 17.9 Data Format in Clock Synchronous Communication .............................................. 391 Figure 17.10 Example of SCI3 Transmission in Clock Synchronous Mode .............................. 392 Figure 17.11 Sample Serial Transmission Flowchart (Clock Synchronous Mode) ....................
Section 19 Figure 19.1 Figure 19.2 Figure 19.3 Figure 19.4 Figure 19.4 Figure 19.5 A/D Converter Block Diagram of A/D Converter ........................................................................... 444 A/D Conversion Timing.......................................................................................... 451 External Trigger Input Timing ................................................................................ 452 A/D Conversion Accuracy Definitions (1).................................
Figure B.13 Port 5 Block Diagram (P55, P54, P53, P52, P51, P50)........................................... 557 Figure B.14 Port 7 Block Diagram (P77) ................................................................................... 558 Figure B.15 Port 7 Block Diagram (P76) ................................................................................... 558 Figure B.16 Port 7 Block Diagram (P75) ................................................................................... 559 Figure B.
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Tables Section 1 Overview Table 1.1 Pin Functions ............................................................................................................ 6 Section 2 CPU Table 2.1 Operation Notation ................................................................................................. 20 Table 2.2 Data Transfer Instructions....................................................................................... 21 Table 2.3 Arithmetic Operations Instructions (1) ...............................
Table 7.3 Table 7.4 Table 7.5 Table 7.6 Table 7.7 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible ............................................................................................................. 114 Reprogramming Data Computation Table............................................................ 117 Additional-Program Data Computation Table ...................................................... 117 Programming Time ............................................
Table 17.4 Table 17.5 Table 17.6 Table 17.7 Maximum Bit Rate for Each Frequency (Asynchronous Mode) .......................... 382 Examples of BRR Settings for Various Bit Rates (Clock Synchronous Mode) .......... 382 SSR Status Flags and Receive Data Handling ...................................................... 388 SCI3 Interrupt Requests........................................................................................ 403 Section 18 I2C Bus Interface 2 (IIC2) Table 18.1 Pin Configuration........
Rev. 1.50 Sep.
Section 1 Overview Section 1 Overview 1.
Section 1 Overview • General I/O ports I/O pins: 79 I/O pins, including 20 large current ports (IOL = 20 mA @VOL = 1.5 V) Input-only pins: 8 input pins (also used for analog input) • Supports various power-down modes • Compact package Package Code Body Size Pin Pitch QFP-100 FP-100A 20.0 × 14.0 mm 0.65 mm LQFP-100 FP-100U 14.0 × 14.0 mm 0.5 mm Rev. 1.50 Sep.
Section 1 Overview Port 7 Port 8 P87 P86 P85 Port C PC3 PC2 PC1 PC0 Por D PD7/FTIOD1 PD6/FTIOC1 PD5/FTIOB1 PD4/FTIOA1 PD3/FTIOD0 PD2/FTIOC0 PD1/FTIOB0 PD0/FTIOA0 Port E PE7/FTIOD3 PE6/FTIOC3 PE5/FTIOB3 PE4/FTIOA3 PE3/FTIOD2 PE2/FTIOC2 PE1/FTIOB2 PE0/FTIOA2 Port H VCL VCC VCC VSS VSS VSS RES TEST NMI Port 1 ROM RAM RTC IIC2 14-bit PWM SCI3 Timer RD_0 SCI3_2 Timer RD_1 SCI3_3 Timer V Watchdog timer Timer RC Timer B1 A/D Converter POR and LVD (optional) Data bus (upper) Address bus
Section 1 Overview Pin Assignment 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PC0 P55/WKP5 P54/WKP4 P53/WKP3 P52/WKP2 P51/WKP1 P50/WKP0 P17/IRQ3/TRGV P16/IRQ2 P15/IRQ1/TMIB1 VSS P14/IRQ0 P12 VCC P11/PWM P10/TMOW P27 P26 P25 P24 P23 P22/TXD P21/RXD P20/SCK3 PH3/FTCI PH2/TXD_3 PH1/RXD_3 PH0/SCK3_3/ADTRG PH7/FTIOD PH6/FTIOC 1.
51 52 54 53 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 76 50 77 49 78 48 79 47 80 46 81 45 82 44 83 43 84 42 85 41 86 40 39 87 FP-100U (Top View) 88 89 38 37 24 25 23 22 21 20 19 18 17 16 15 14 13 26 12 27 100 11 28 99 9 10 29 98 8 30 97 7 31 96 6 32 95 5 33 94 4 34 93 3 35 92 2 36 91 1 90 PH0/SCK3_3/ADTRG PH7/FTIOD PH6/FTIOC PH5/FTIOB PH4/FTIOA/TRGC PD7/FTIOD1 PD6/FTIOC1 PD5/FTIOB1 PD4/FTIOA1 PD3/
Section 1 Overview 1.4 Table 1.1 Pin Functions Pin Functions Pin No. Type Symbol FP-100A FP-100U I/O Functions 19, 67 16, 64 Input Power supply pin. Connect this pin to the system power supply. Vss 16, 42, 70 13, 39, 67 Input Ground pin. Ensure to connect all pins to the system power supply (0 V). AVcc 7 4 Input Analog power supply pin for the A/D converter. When the A/D converter is not used, connect this pin to the system power supply.
Section 1 Overview Pin No. Type Symbol FP-100A FP-100U I/O Functions External interrupt pins NMI 20 17 Non-maskable interrupt request input pin. Input Be sure to pull-up by a pull-up resistor. IRQ0 to IRQ3 69, 71 to 73 66, 68, 69, 70 Input External interrupt request input pins. Can select the rising or falling edge. WKP0 to WKP5 74 to 79 71 to 76 Input External interrupt request input pins. Can select the rising or falling edge.
Section 1 Overview Pin No.
Section 1 Overview Pin No.
Section 1 Overview Rev. 1.50 Sep.
Section 2 CPU Section 2 CPU This LSI has an H8/300H CPU with an internal 32-bit architecture that is upward-compatible with the H8/300CPU, and supports only advanced mode, which has a 16-Mbyte address space. • Upward-compatible with H8/300 CPUs Can execute H8/300 CPUs object programs Additional eight 16-bit extended registers 32-bit transfer and arithmetic and logic instructions are added Signed multiply and divide instructions are added.
Section 2 CPU • Power-down state Transition to power-down state by SLEEP instruction 2.1 Address Space and Memory Map The address space of this LSI is 16 Mbytes, which includes the program area and data area. Figure 2.1 shows the memory map.
Section 2 CPU 2.2 Register Configuration The H8/300H CPU has the internal registers shown in figure 2.2. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), and an 8-bit condition-code register (CCR).
Section 2 CPU 2.2.1 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.3 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).
Section 2 CPU Empty area SP (ER7) Stack area Figure 2.4 Relationship between Stack Pointer and Stack Area 2.2.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0).
Section 2 CPU Bit Initial Bit Name Value R/W 7 I R/W 1 Description Interrupt Mask Bit Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence. 6 UI Undefined R/W User Bit Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. 5 H Undefined R/W Half-Carry Flag When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.
Section 2 CPU 2.3 Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.3.1 General Register Data Formats Figure 2.5 shows the data formats in general registers.
Section 2 CPU Data Type General Register Word data Rn Data Format 15 Word data MSB En 15 MSB Longword data 0 LSB 0 LSB ERn 31 16 15 MSB [Legend] ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2.5 General Register Data Formats (2) Rev. 1.50 Sep.
Section 2 CPU 2.3.2 Memory Data Formats Figure 2.6 shows the data formats in memory. The H8/300H CPU can access word data and longword data in memory, however word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, an address error does not occur, however the least significant bit of the address is regarded as 0, so access begins the preceding address. This also applies to instruction fetches.
Section 2 CPU 2.4 Instruction Set 2.4.1 List of Instructions Classified by Function The H8/300H CPU has 62 instructions. Tables 2.2 to 2.9 summarize the instructions in each functional category. The notation used in tables 2.2 to 2.9 is defined below. Table 2.
Section 2 CPU Table 2.2 Data Transfer Instructions Instruction Size* Function MOV B/W/L (EAs) → Rd, Rs → (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B (EAs) → Rd Cannot be used in this LSI. MOVTPE B Rs → (EAs) Cannot be used in this LSI. POP W/L @SP+ → Rn Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn.
Section 2 CPU Table 2.3 Arithmetic Operations Instructions (1) Instruction Size* Function ADD SUB B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.
Section 2 CPU Table 2.3 Arithmetic Operations Instructions (2) Instruction Size* Function DIVXS B/W Rd ÷ Rs → Rd Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder. CMP B/W/L Rd – Rs, Rd – #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result.
Section 2 CPU Table 2.4 Logic Operations Instructions Instruction Size* Function AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd Performs a logical OR operation on a general register and another general register or immediate data.
Section 2 CPU Table 2.6 Bit Manipulation Instructions (1) Instruction Size* Function BSET B 1 → ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 → ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
Section 2 CPU Table 2.6 Bit Manipulation Instructions (2) Instruction Size* Function BXOR B C ⊕ ( of ) → C XORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B C ⊕ ~ ( of ) → C XORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BLD B (
Section 2 CPU Table 2.7 Branch Instructions Instruction Size Function Bcc* — Branches to a specified address if a specified condition is true. The branching conditions are listed below.
Section 2 CPU Table 2.8 System Control Instructions Instruction Size* Function TRAPA — Starts trap-instruction exception handling. RTE — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. LDC B/W (EAs) → CCR Moves the source operand contents to the CCR. The CCR size is one byte, but in transfer from memory, data is read by word access. STC B/W CCR → (EAd) Transfers the CCR contents to a destination location.
Section 2 CPU Table 2.9 Block Data Transfer Instructions Instruction Size Function EEPMOV.B — if R4L ≠ 0 then Repeat @ER5+ → @ER6+, R4L–1 → R4L Until R4L = 0 else next; EEPMOV.W — if R4 ≠ 0 then Repeat @ER5+ → @ER6+, R4–1 → R4 Until R4 = 0 else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed. Rev. 1.50 Sep.
Section 2 CPU 2.4.2 Basic Instruction Formats H8/300H CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op), a register field (r), an effective address extension (EA), and a condition field (cc). Figure 2.7 shows examples of instruction formats. (1) Operation Field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction.
Section 2 CPU 2.5 Addressing Modes and Effective Address Calculation 2.5.1 Addressing Modes The H8/300H CPU supports the eight addressing modes listed in table 2.10. Each instruction uses a subset of these addressing modes. Addressing modes that can be used differ depending on the instruction. For details, refer to appendix A.4, Combinations of Instructions and Addressing Modes. Arithmetic and logic instructions can use the register direct and immediate modes.
Section 2 CPU (3) Register Indirect with Displacement—@(d:16, ERn) or @(d:24, ERn) A 16-bit or 24-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the lower 24 bits of the sum the address of a memory operand. A 16-bit displacement is sign-extended when added.
Section 2 CPU (6) Immediate—#xx:8, #xx:16, or #xx:32 The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address.
Section 2 CPU 2.5.2 Effective Address Calculation Table 2.12 indicates how effective addresses are calculated in each addressing mode. In this LSI, a 24-bit effective address is generated. Table 2.12 Effective Address Calculation (1) No 1 Addressing Mode and Instruction Format op 2 Effective Address Calculation Effective Address (EA) Register direct(Rn) rm Operand is general register contents.
Section 2 CPU Table 2.12 Effective Address Calculation (2) No 5 Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Absolute address @aa:8 8 7 23 op abs 0 H'FFFF @aa:16 23 op abs 16 15 0 Sign extension @aa:24 op 0 23 abs 6 Immediate #xx:8/#xx:16/#xx:32 op 7 Operand is immediate data.
Section 2 CPU 2.6 Basic Bus Cycle CPU operation is synchronized by a system clock (φ) or a subclock (φSUB). The period from a rising edge of φ or φSUB to the next rising edge is called one state. A bus cycle consists of two states or three states. The cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules. 2.6.1 Access to On-Chip Memory (RAM, ROM) Access to on-chip memory takes place in two states.
Section 2 CPU 2.6.2 On-Chip Peripheral Modules On-chip peripheral modules are accessed in two to four states. The data bus width is 8 bits or 16 bits depending on the register. For details on the data bus width and number of accessing states of each register, refer to section 22, List of Registers. Registers with 16-bit data bus width can be accessed only in words. Registers with 8-bit data bus width can be accessed in bytes or words.
Section 2 CPU 2.7 CPU States There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active mode and subactive mode. For the program halt state, there are a sleep mode, standby mode, and sub-sleep mode. These states are shown in figure 2.11. Figure 2.12 shows the state transitions. For details on program execution state and program halt state, refer to section 6, Power-Down Modes.
Section 2 CPU Reset cleared Reset state Exception-handling state Reset occurs Reset occurs Reset occurs Interrupt source Program halt state Interrupt source Exceptionhandling complete Program execution state SLEEP instruction executed Figure 2.12 State Transitions 2.8 Usage Notes 2.8.1 Notes on Data Access to Empty Areas The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip I/O registers areas available to the user.
Section 2 CPU (1) Bit manipulation for two registers assigned to the same address Example 1: Bit manipulation for the timer load register and timer counter (Applicable for timer B1 in the H8/36109 Group.) Figure 2.13 shows an example of a timer in which two timer registers are assigned to the same address. When a bit-manipulation instruction accesses the timer load register and timer counter of a reloadable timer, since these two registers share the same address, the following operations takes place. 1.
Section 2 CPU Example 2: The BSET instruction is executed for port 5. P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at P56. P55 to P50 are output pins and output low-level signals. An example to output a high-level signal at P50 with a BSET instruction is shown below.
Section 2 CPU As a result of the BSET instruction, bit 0 in PDR5 becomes 1, and P50 outputs a high-level signal. However, bits 7 and 6 of PDR5 end up with different values. To prevent this problem, store a copy of the PDR5 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PDR5. • Prior to executing BSET instruction MOV.B MOV.B MOV.
Section 2 CPU (2) Bit Manipulation in a Register Containing a Write-Only Bit Example 3: BCLR instruction executed designating port 5 control register PCR5 P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at P56. P55 to P50 are output pins that output low-level signals. An example of setting the P50 pin as an input pin by the BCLR instruction is shown below. It is assumed that a high-level signal will be input to this input pin.
Section 2 CPU As a result of this operation, bit 0 in PCR5 becomes 0, making P50 an input port. However, bits 7 and 6 in PCR5 change to 1, so that P57 and P56 change from input pins to output pins. To prevent this problem, store a copy of the PCR5 data in a work area in memory and manipulate data of the bit in the work area, then write this data to PCR5. • Prior to executing BCLR instruction MOV.B MOV.B MOV.
Section 3 Exception Handling Section 3 Exception Handling Exception handling is caused by a reset, a trap instruction (TRAPA), or interrupts. • Reset A reset has the highest exception priority. Exception handling starts after the reset state is cleared by a negation of the RES signal. Exception handling is also started when the watchdog timer overflows. The exception handling executed at this time is the same as that for a reset by the RES pin.
Section 3 Exception Handling Table 3.
Section 3 Exception Handling Related Module Exception Sources Vector Number Vector Address ICR Priority Reserved for system use 25 to 28 H'000064 to H'000073 High Timer B1 Overflow 29 H'000074 to H'000077 ICRC7 Reserved for system use 30, 31 H'000078 to H'00007F SCI3_2 Receive data full Transmit data empty Transmit end Receive error 32 H'000080 to H'000083 ICRC4 Reserved for system use 33 H'000084 to H'000087 SCI3_3 Receive data full Transmit data empty Transmit
Section 3 Exception Handling 3.2 Register Descriptions Interrupts are controlled by the following registers. • • • • • • • • Interrupt edge select register 1 (IEGR1) Interrupt edge select register 2 (IEGR2) Interrupt enable register 1 (IENR1) Interrupt enable register 2 (IENR2) Interrupt flag register 1 (IRR1) Interrupt flag register 2 (IRR2) Wakeup interrupt flag register (IWPR) Interrupt control registers A to D (ICRA to ICRD) 3.2.
Section 3 Exception Handling 3.2.2 Interrupt Edge Select Register 2 (IEGR2) IEGR2 selects the direction of an edge that generates interrupt requests of pins WKP5 to WKP0. Bit Bit Name Initial Value R/W 7, 6 All 1 Description Reserved These bits are always read as 1.
Section 3 Exception Handling 3.2.3 Interrupt Enable Register 1 (IENR1) IENR1 enables direct transition interrupts, RTC interrupts, and external pin interrupts. Bit Bit Name Initial Value R/W Description 7 IENDT 0 R/W Direct Transition Interrupt Enable When this bit is set to 1, direct transition interrupt requests are enabled. 6 IENTA 0 R/W RTC Interrupt Enable When this bit is set to 1, an RTC interrupt request is enabled.
Section 3 Exception Handling 3.2.4 Interrupt Enable Register 2 (IENR2) IENR2 enables a timer B1 overflow interrupt. Bit Bit Name Initial Value R/W 7, 6 All 0 Description Reserved These bits are always read as 0. 5 IENTB1 0 R/W Timer B1 Interrupt Enable When this bit is set to 1, a timer B1 overflow interrupt request is enabled. 4 to 0 All 1 Reserved These bits are always read as 1.
Section 3 Exception Handling Bit Bit Name Initial Value R/W Description 6 IRRTA R/W RTC Interrupt Request Flag [Setting condition] When the RTC counter value overflows [Clearing condition] When writing 0 5, 4 All 1 Reserved These bits are always read as 1. 3 IRRI3 0 R/W IRQ3 Interrupt Request Flag [Setting condition] When the IRQ3 pin is specified as an interrupt input and the specified edge is detected.
Section 3 Exception Handling 3.2.6 Interrupt Flag Register 2 (IRR2) IRR2 is a status flag register for timer B1 overflow interrupts. Bit Bit Name Initial Value R/W Description 7, 6 All 0 Reserved These bits are always read as 0. 5 IRRTB1 0 R/W Timer B1 Interrupt Request flag [Setting condition] When the timer B1 counter overflows [Clearing condition] When writing 0 4 to 0 All 1 Reserved These bits are always read as 1. 3.2.
Section 3 Exception Handling Bit Bit Name Initial Value R/W Description 3 IWPF3 0 R/W WKP3 Interrupt Request Flag [Setting condition] When the WKP3 pin is specified as an interrupt input and the specified edge is detected [Clearing condition] When writing 0 2 IWPF2 0 R/W WKP2 Interrupt Request Flag [Setting condition] When the WKP2 pin is specified as an interrupt input and the specified edge is detected.
Section 3 Exception Handling 3.2.8 Interrupt Control Registers A to D (ICRA to ICRD) ICR sets the priority level of an interrupt source other than the NMI and address break. The correspondence between interrupt requests and bits ICRA to ICRD is shown in table 3.2.
Section 3 Exception Handling 3.3 Reset Exception Handling When the RES signal goes low, all processing halts and this LSI enters the reset state. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized by the reset. When the power is turned on, hold the RES signal low until oscillation of the clock pulse generator settles to ensure that this LSI is reset. To reset this LSI during operation, hold the RES signal low for a given time.
Section 3 Exception Handling • WKP5 to WKP0 Interrupts WKP5 to WKP0 interrupts are generated when the edges of the WKP5 to WKP0 signals are input. These six interrupts are assigned to the same vector addresses, and the detecting edge for each signal can be selected from rising or falling, depending on the settings of bits WPEG5 to WPEG0 in IEGR2.
Section 3 Exception Handling 3.4.2 Internal Interrupts Each on-chip peripheral module has a flag to indicate the interrupt request status and the enable bit to enable or disable the interrupt. For RTC interrupt requests and direct transition interrupt requests generated by execution of the SLEEP instruction, this function is included in IRR1, IRR2, IENR1, and IENR2.
Section 3 Exception Handling Figure 3.2 shows the interrupt acceptance flowchart. Figure 3.4 shows a typical interrupt sequence where the program area is in the on-chip ROM and the stack area is in the on-chip RAM.
Section 3 Exception Handling SP – 4 SP (ER7) SP – 3 SP + 1 PCE SP – 2 SP + 2 PCH SP – 1 SP + 3 PCL SP (ER7) SP + 4 CCR Even address Stack area Prior to start of interrupt exception handling PC and CCR saved to stack After completion of interrupt exception handling [Legend] PCE: Bits 23 to 16 of program counter (PC) PCH: Bits 15 to 8 of program counter (PC) PCL: Bits 7 to 0 of program counter (PC) CCR: Condition code register SP: Stack pointer Notes: 1.
Internal data bus Instruction code (not executed) Instruction prefetch address (not executed) SP – 2 SP – 4 (2), (4) (3) (5) (7) (4) High (3) Instruction prefetch address (not executed; return address, same as PC contents) (2) (1) (1) Internal write signal Internal read signal Internal address bus Interrupt request signal φ Interrupt accepted Interrupt level Instruction decision and wait for prefetch end of instruction (6), (8) (9), (11) (10), (12) (13) (14) Internal processing (8) (7) (
Section 3 Exception Handling 3.4.4 Interrupt Response Time Table 3.3 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handling-routine is executed. Table 3.3 Interrupt Wait States Item States 1 Interrupt priority determination 2* 2 Waiting time for completion of executing instruction* 1 to 23 Saving of PC and CCR to stack 4 Vector fetch 4 Instruction fetch 4 Internal processing 4 Notes: 1.
Section 3 Exception Handling 3.5 Usage Notes 3.5.1 Interrupts after Reset If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset.
Section 3 Exception Handling Rev. 1.50 Sep.
Section 4 Address Break Section 4 Address Break The address break simplifies on-board program debugging. It requests an address break interrupt when the set break condition is satisfied. The interrupt request is not affected by the I bit of CCR. Break conditions that can be set include instruction execution at a specific address and a combination of access and data at a specific address.
Section 4 Address Break 4.1 Register Descriptions The address break has the following registers. • • • • Address break control register (ABRKCR) Address break status register (ABRKSR) Break address registers E, H, L (BARE, BARH, BARL) Break data register (BDRH, BDRL) 4.1.1 Address Break Control Register (ABRKCR) ABRKCR sets address break conditions.
Section 4 Address Break Bit Bit Name Initial Value R/W Description 1 DCMP1 0 R/W Data Compare 1 and 0 0 DCMP0 0 R/W These bits set the comparison condition between the data set in BDR and the internal data bus. 00: No data comparison 01: Compares lower 8-bit data between BDRL and data bus 10: Compares upper 8-bit data between BDRH and data bus 11: Compares 16-bit data between BDR and data bus [Legend] x: Don't care.
Section 4 Address Break 4.1.2 Address Break Status Register (ABRKSR) ABRKSR consists of the address break interrupt flag and the address break interrupt enable bit. Bit Bit Name Initial Value R/W Description 7 ABIF 0 R/W Address Break Interrupt Flag [Setting condition] When the condition set in ABRKCR is satisfied [Clearing condition] When 0 is written after ABIF=1 is read 6 ABIE 0 R/W Address Break Interrupt Enable When this bit is 1, an address break interrupt request is enabled.
Section 4 Address Break 4.2 Operation When the ABIE bit in ABRKSR is set to 1, if the ABIF bit in ABRKSR is set to 1 by the combination of the address set in BAR, the data set in BDR, and the conditions set in ABRKCR, the address break function generates an interrupt request to the CPU. When the interrupt request is accepted, interrupt exception handling starts after the instruction being executed ends. The address break interrupt is not masked because of the I bit in CCR of the CPU. Figures 4.
Section 4 Address Break When the address break is specified in the data read cycle Register setting • ABRKCR = H'A0 • BAR = H'025A Program 0258 025A * 025C 0260 0262 : NOP NOP MOV.W @H'025A,R0 NOP Underline indicates the address NOP to be stacked.
Section 5 Clock Pulse Generators Section 5 Clock Pulse Generators The clock pulse generator consists of a system clock generating circuitry, a subclock generating circuitry, and two prescalers. The system clock generating circuitry includes a system clock oscillator, a duty correction circuit, an on-chip oscillator, an on-chip oscillator divider, a clock select circuit, and a system clock divider. The subclock generating circuitry includes a subclock oscillator and a subclock divider. Figure 5.
Section 5 Clock Pulse Generators 5.1 Features • Choice of two clock sources On-chip oscillator clock External oscillator clock • Choice of two frequencies of the on-chip oscillator by the user software 40 MHz 32 MHz The signal generated by dividing the above clock by a value from 2 to 8 can be used as the system clock and the above clock can be used as the clock source for timer RC or timer RD.
Section 5 Clock Pulse Generators 5.2.1 RC Control Register (RCCR) RCCR controls the on-chip oscillator. Bit Bit Name Initial Value R/W Description 7 RCSTP 0 R/W On-Chip Oscillator Standby The on-chip oscillator standby state is entered by setting this bit to 1. 6 FSEL 1 R/W Frequency Select for On-Chip Oscillator The system clock is generated by dividing this clock while this clock is supplied to timer RC or timer RD (φ40M).
Section 5 Clock Pulse Generators 5.2.2 RC Trimming Data Protect Register (RCTRMDPR) RCTRMDPR controls RCTRMDPR itself and writing to RCTRMDR. Use the MOV instruction to rewrite this register. Bit manipulation instruction cannot change the settings. Bit Bit Name Initial Value R/W Description 7 WRI 1 W Write Inhibit Only when writing 0 to this bit, this register can be written to. This bit is always read as 1.
Section 5 Clock Pulse Generators Initial Value Bit Bit Name 4 TRMDRWE 0 R/W Description R/W Trimming Date Register Write Enable This register can be written to when the LOCKDW bit is 0 and this bit is 1. [Setting condition] • When writing 0 to the WRI bit and writing 1 to the TRMDRWE bit while the PRWE bit is 1. [Clearing conditions] 3 to 0 All 1 • Reset • When writing 0 to the WRI bit and writing 0 to the TRMDRWE bit while the PRWE bit is 1. Reserved These bits are always read as 1.
Section 5 Clock Pulse Generators 5.2.4 Clock Control/Status Register (CKCSR) CKCSR selects the OSC pin function, controls switching system clocks, and indicates the system clock state. These bits must be written in active mode.
Section 5 Clock Pulse Generators Bit Bit Name Initial Value R/W 1 1 Description Reserved This bit is always read as 1. 0 CKSTA 0 R LSI Operating Clock Status 0: This LSI operates on on-chip oscillator clock. 1: This LSI operates on external clock. 5.3 System Clock Oscillator 5.3.1 State Transition of System Clock The system clock of this LSI is generated from the on-chip oscillator clock after a reset.
Section 5 Clock Pulse Generators 5.3.2 Clock Control Operation Figure 5.3 shows the flowchart to switch clock sources from the on-chip oscillator to the external clock. Figure 5.4 shows the flowchart to switch clock sources from the external clock to the onchip oscillator. LSI operates on on-chip oscillator clock Start (reset) Write 1 to PMRC0 in CKCSR Write 1 to PMRC1 in CKCSR [1] [1] External oscillation starts to be enabled when pins PJ0/OSC1 and PJ1/OSC2 are specified as external clock pins.
Section 5 Clock Pulse Generators LSI operates on external clock [1] When 0 is written to the OSCSEL bit, this LSI switches the external clock to the on-chip oscillator clock after the φ stop duration. Seven rising edges of the φRC clock after the OSCSEL bit becomes 0 are included in the φ stop duration. Start (LSI operates on external clock) Write 0 to RCSTP in RCCR [2] Writing 0 to bit PMRJ0 stops the external oscillation.
Section 5 Clock Pulse Generators 5.3.3 Clock Change Timing The timing for changing clocks are shown in figures 5.5 and 5.6.
Section 5 Clock Pulse Generators φOSC φRC φ OSCSEL PHISTOP (Internal signal) CKSTA CKSWIF External RC clock operation [Legend] φOSC: φRC: φ: OSCSEL: PHISTOP: CKSTA: CKSWIF: Note: * φ halt* External clock operation External clock Internal RC clock System clock Bit 4 in CKCSR System clock stop control signal Bit 0 in CKCSR Bit 2 in CKCSR The φ halt duration is the duration from the timing when the φ clock stops to the seventh rising edge of the φRC clock. Figure 5.
Section 5 Clock Pulse Generators 5.4 Trimming of On-Chip Oscillator Frequency Users can trim the on-chip oscillator frequency, supplying the external reference pulses with the input capture function in timer RC or timer RD. An example of trimming flow using timer RC and a timing chart are shown in figures 5.7 and 5.8, respectively.
Section 5 Clock Pulse Generators φRC FTIOA input capture input tA (µs) Timer RC TRCCNT M-1 M N GRA M+α M+1 M+α M GRC N M Capture 1 Capture 2 Figure 5.8 Timing Chart of Trimming of On-Chip Oscillator Frequency The on-chip oscillator frequency is obtained by the expression below. Since the input-capture input is sampled at the rate of φRC, the calculated result includes a sampling error of ±1 φRC clock cycle.
Section 5 Clock Pulse Generators 5.5 External Oscillator This LSI has two methods to supply external clock pulses into it: connecting a crystal or ceramic resonator, and an external clock. Oscillation pins PJ0/OSC1 and PJ1/OSC2/CLKOUT are common with general ports PC0 and PC1, respectively. To set pins PC0 and PC1 as crystal resonator or external clock input ports, refer to section 5.3.2, Clock Control Operation.
Section 5 Clock Pulse Generators Table 5.1 Crystal Resonator Parameters Frequency (MHz) 4 8 10 RS (Max.) 120 Ω 80 Ω 60 Ω C0 (Max.) 5.5.2 16 20 50 Ω 40 Ω 7 pF Connecting Ceramic Resonator Figure 5.12 shows an example of connecting a ceramic resonator. C1 OSC1 C2 OSC2 C1 = 30 pF ±10% C2 = 30 pF ±10% Capacitances are reference values. Figure 5.12 Example of Connection to Ceramic Resonator 5.5.
Section 5 Clock Pulse Generators 5.6 Subclock Generator Figure 5.14 shows a block diagram of the subclock generator. X2 8 MΩ X1 Note: Resistance is a reference value. Figure 5.14 Block Diagram of Subclock Generator 5.6.1 Connecting 32.768-kHz Crystal Resonator Clock pulses can be supplied to the subclock divider by connecting a 32.768-kHz crystal resonator, as shown in figure 5.15. Figure 5.16 shows the equivalent circuit of the 32.768-kHz crystal resonator. C1 X1 C2 C1 = C2 = 15 pF (typ.
Section 5 Clock Pulse Generators 5.6.2 Pin Connection when not Using Subclock When the subclock is not used, connect pin X1 to VCL or VSS and leave pin X2 open, as shown in figure 5.17. VCL or VSS X1 X2 Open Figure 5.17 Pin Connection when not Using Subclock 5.7 Prescaler 5.7.1 Prescaler S Prescaler S is a 13-bit counter using the system clock (φ) as its input clock. The outputs, which are divided clocks, are used as internal clocks by the on-chip peripheral modules.
Section 5 Clock Pulse Generators 5.8 Usage Notes 5.8.1 Note on Resonators Resonator characteristics are closely related to board design and should be carefully evaluated by the user, referring to the examples shown in this section. Resonator circuit parameters will differ depending on the resonator element, stray capacitance of the PCB, and other factors. Suitable values should be determined in consultation with the resonator element manufacturer.
Section 6 Power-Down Modes Section 6 Power-Down Modes This LSI has five operating modes after a reset: a normal active mode and four power-down modes in which power consumption is significantly reduced. In addition to these modes, there is a module standby function in which power consumption is also reduced by selectively halting onchip module functions. • Active mode The CPU and all on-chip peripheral modules operate on the system clock.
Section 6 Power-Down Modes 6.1 Register Descriptions The registers related to power-down modes are listed below. For details on the serial mode control register (SCI3_3 module standby), see section 17.1, Features. • • • • • • • System control register 1 (SYSCR1) System control register 2 (SYSCR2) System control register 3 (SYSCR3) Module standby control register 1 (MSTCR1) Module standby control register 2 (MSTCR2) Module standby control register 4 (MSTCR4) Serial Mode Control Register (SMCR) 6.1.
Section 6 Power-Down Modes Bit Bit Name Initial Value R/W Description 6 STS2 0 R/W Standby Timer Select 2 to 0 5 STS1 0 R/W 4 STS0 0 R/W These bits specify the waiting time in number of cycles until clocks are supplied after the system clock oscillator starts oscillation when making a transition from the standby, subactive, or subsleep mode to the active or sleep mode. The number of cycles for the waiting time should be specified so that the waiting time is 6.
Section 6 Power-Down Modes Bit Bit Name Initial Value R/W Description 3 NESEL 0 R/W Noise Elimination Sampling Frequency Select This bit selects the clock frequency to sample the watch clock signal (φW) generated by the subclock oscillator. The oscillator clock (φOSC) generated by the system clock oscillator or the φRC clock generated by the on-chip oscillator can be used as the sampling clock source. When φOSC or φRC = 4 to 20 MHz, set this bit to 0.
Section 6 Power-Down Modes 6.1.2 System Control Register 2 (SYSCR2) SYSCR2 controls the power-down modes, as well as SYSCR1. Bit Bit Name Initial Value R/W Description 7 SMSEL 0 R/W Sleep Mode Select 6 LSON 0 R/W Low Speed on Flag 5 DTON 0 R/W Direct Transfer on Flag These bits select the mode to enter after the execution of a SLEEP instruction, as well as bit SSBY of SYSCR1. For details, see table 6.2.
Section 6 Power-Down Modes 6.1.3 System Control Register 3 (SYSCR3) SYSCR3 controls waiting time in combination with SYSCR1. Bit Bit Name Initial Value R/W Description 7 STS3 1 R/W Standby Timer Select 3 This bit selects the waiting time in combination with bits STS2 to STS0 in SYSCR1. The relationship between the register setting and waiting time is shown in table 6.1. 6 to 0 All 1 Reserved These bits are always read as 0. 6.1.
Section 6 Power-Down Modes Bit Bit Name Initial Value R/W Description 1 MSTTV 0 R/W Timer V Module Standby Timer V enters the standby mode when this bit is set to 1 0 MSTTA 0 R/W RTC Module Standby RTC enters the standby mode when this bit is set to 1 6.1.5 Module Standby Control Register 2 (MSTCR2) MSTCR2 allows the on-chip peripheral modules to enter a standby state in module units.
Section 6 Power-Down Modes 6.1.6 Module Standby Control Register 4 (MSTCR4) MSTCR4 allows the on-chip peripheral modules to enter a standby state in module units.
Section 6 Power-Down Modes 6.2 Mode Transitions and States of LSI Figure 6.1 shows the possible transitions among these operating modes. A transition is made from the program execution state to the program halt state by executing a SLEEP instruction. Interrupts allow for returning from the program halt state to the program execution state. A direct transition between active mode and subactive mode, which are both program execution states, can be made without halting the program.
Section 6 Power-Down Modes Table 6.2 Transition Mode after SLEEP Instruction Execution and Transition Mode due to Interrupt DTON SSBY SMSEL LSON Transition Mode after SLEEP Instruction Execution 0 0 0 0 Sleep mode 1 1 0 Active mode Subactive mode Subsleep mode 1 1 Transition Mode due to Interrupt Active mode Subactive mode 1 X X Standby mode Active mode X 0* 0 Active mode (direct transition) — X X 1 Subactive mode (direct transition) — [Legend] X: Don't care.
Section 6 Power-Down Modes Table 6.
Section 6 Power-Down Modes 6.2.1 Sleep Mode In sleep mode, CPU operation is halted but the on-chip peripheral modules function at the clock frequency set by the MA2, MA1, and MA0 bits in SYSCR2. CPU register contents are retained. When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts. Sleep mode is not cleared if the I bit of the condition code register (CCR) is set to 1 or the requested interrupt is disabled in the interrupt enable register.
Section 6 Power-Down Modes 6.2.3 Subsleep Mode In subsleep mode, operation of the CPU and on-chip peripheral modules other than the RTC is halted. As long as a required voltage is applied, the contents of CPU registers, the on-chip RAM, and some registers of the on-chip peripheral modules are retained. I/O ports keep the same states as before the transition. The subsleep mode is lifted by an interrupt.
Section 6 Power-Down Modes 6.4 Direct Transition The CPU can execute programs in two modes: active and subactive modes. A direct transition is a transition between these two modes without stopping program execution. A direct transition can be made by executing the SLEEP instruction while the DTON bit in SYSCR2 is set to 1. The direct transition also enables operating frequency modification in active or subactive mode. After the mode transition, direct transition interrupt exception handling starts.
Section 6 Power-Down Modes 6.4.2 Direct Transition from Subactive Mode to Active Mode The time from the start of the SLEEP instruction execution to the end of the interrupt exception handling (the direct transition time) is calculated by equation (2).
Section 6 Power-Down Modes Rev. 1.50 Sep.
Section 7 ROM Section 7 ROM The features of the 128-kbyte flash memory in this LSI are summarized below. • Programming/erasing methods The flash memory is programmed 128 bytes at a time. Erasure is performed in single-block units. The flash memory is configured as follows: four 1-kbyte blocks, one 28-kbyte block, and three 32-kbyte blocks. To erase the entire flash memory, each block must be erased in turn. • Reprogramming capability The flash memory can be reprogrammed up to 1,000 times.
Section 7 ROM 7.1 Block Configuration Figure 7.1 shows the block configuration of flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values in the frames are addresses. The 128kbyte flash memory is divided into four 1-kbyte blocks, one 28-kbyte block, and three 32-kbyte blocks. Erasing is performed in these units. Programming is performed in 128-byte units, each starting at an address with H'00 or H'80 as the low-order byte.
Section 7 ROM 7.2 Register Descriptions The flash memory has the following registers. • • • • • Flash memory control register 1 (FLMCR1) Flash memory control register 2 (FLMCR2) Erase block register 1 (EBR1) Flash memory power control register (FLPWCR) Flash memory enable register (FENR) 7.2.1 Flash Memory Control Register 1 (FLMCR1) FLMCR1 is a register that makes the flash memory change to programming mode, program-verify mode, erasing mode, or erase-verify mode.
Section 7 ROM Bit Bit Name Initial Value R/W Description 2 PV 0 R/W Program-Verify When this bit is set to 1, the flash memory changes to program-verify mode. When it is cleared to 0, programverify mode is cancelled. 1 E 0 R/W Erasure When this bit is set to 1 while SWE=1 and ESU=1, the flash memory changes to erasing mode. When it is cleared to 0, erasing mode is cancelled. 0 P 0 R/W Program When this bit is set to 1 while SWE=1 and PSU=1, the flash memory changes to programming mode.
Section 7 ROM 7.2.3 Erase Block Register 1 (EBR1) EBR1 specifies whether or not a block in the flash memory is erased. EBR1 is initialized to H'00 when the SWE bit in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 to be automatically cleared to 0. Bit Bit Name Initial Value R/W Description 7 EB7 0 R/W When this bit is set to 1, 32 kbytes of H'018000 to H'01FFFF will be erased.
Section 7 ROM 7.2.4 Flash Memory Power Control Register (FLPWCR) FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI switches to subactive mode. There are two modes: mode in which operation of the power supply circuit of flash memory is partly halted in power-down mode and flash memory can be read, and mode in which even if a transition is made to subactive mode, operation of the power supply circuit of flash memory is retained and flash memory can be read.
Section 7 ROM 7.3 On-Board Programming Modes There are two modes for programming/erasing of the flash memory; boot mode, which enables onboard programming/erasing, and programmer mode, in which programming/erasing is performed with a PROM programmer. On-board programming/erasing can also be performed in user programming mode. At reset-start in reset mode, this LSI changes to a mode depending on the TEST pin settings, NMI pin settings, and input level of each port, as shown in table 7.1.
Section 7 ROM 3. When the boot program is initiated, the chip measures the low-level period of asynchronous SCI communication data (H'00) transmitted continuously from the host. The chip then calculates the bit rate of transmission from the host, and adjusts the SCI3 bit rate to match that of the host. The reset should end with the RxD pin high. The RxD and TxD pins should be pulled up on the board if necessary.
Section 7 ROM Boot Mode Operation Host Operation Processing Contents Communication Contents Transfer of number of bytes of programming control program Flash memory erase Bit rate adjustment Boot mode initiation Item Table 7.2 LSI Operation Processing Contents Branches to boot program at reset-start. Boot program initiation Continuously transmits data H'00 at specified bit rate. Transmits data H'55 when data H'00 is received error-free.
Section 7 ROM Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible Host Bit Rate System Clock Frequency Range of LSI 9,600 bps On-chip oscillator (10 MHz) 4,800 bps 2,400 bps 7.3.2 Programming/Erasing in User Programming Mode On-board programming/erasing of an individual flash memory block can also be performed in user programming mode by branching to a user programming/erasure control program.
Section 7 ROM 7.4 Flash Memory Programming/Erasing A software method using the CPU is employed to program and erase flash memory in the onboard programming modes. Depending on the FLMCR1 setting, the flash memory operates in one of the following four modes: Programming mode, program-verify mode, erasing mode, and eraseverify mode.
Section 7 ROM 8. The maximum number of repetitions of the programming/program-verify sequence of the same bit is 1,000.
Section 7 ROM Table 7.4 Reprogramming Data Computation Table Programming Data Verify Data Reprogramming Data Comments 0 0 1 Programming completed 0 1 0 Reprogramming bit 1 0 1 — 1 1 1 Remains in erased state Table 7.
Section 7 ROM 7.4.2 Erasure/Erase-Verify When erasing flash memory, the erasure/erase-verify flowchart shown in figure 7.4 should be followed. 1. Prewriting (setting erase block data to all 0s) is not necessary. 2. Erasing is performed in block units. Make only a single-bit specification in the erase block register (EBR1). To erase multiple blocks, each block must be erased in turn. 3. The time during which the E bit is set to 1 is the flash memory erase time. 4.
Section 7 ROM Erase start SWE bit ← 1 Wait 1 µs n←1 Set EBR1 Enable WDT ESU bit ← 1 Wait 100 µs E bit ← 1 Wait 10 ms E bit ← 0 Wait 10 µs ESU bit ← 10 10 µs Disable WDT EV bit ← 1 Wait 20 µs Set block start address as verify address H'FF dummy write to verify address Wait 2 µs * n←n+1 Read verify data No Verify data + all 1s ? Increment address Yes No Last address of block ? Yes No EV bit ← 0 EV bit ← 0 Wait 4 µs Wait 4µs All erasing block erased ? Yes n ≤100 ? SWE bit ← 0 SWE bit ← 0 Wait
Section 7 ROM 7.5 Programming/Erasing Protection There are three types of flash memory programming/erasing protection; hardware protection, software protection, and error protection. 7.5.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset, subactive mode, subsleep mode, or standby mode.
Section 7 ROM The FLMCR1, FLMCR2, and EBR1 settings are retained, however programming mode or erasing mode is aborted at the point at which the error occurred. Programming mode or erasing mode cannot be re-entered by re-setting the P or E bit. However, PV and EV bit settings are retained, and a transition can be made to verify mode. Error protection can be cleared only by a power-on reset. 7.
Section 7 ROM Table 7.7 Flash Memory Operating States Flash Memory Operating State LSI Operating State PDWND = 0 (Initial Value) PDWND = 1 Active mode Normal operating mode Normal operating mode Subactive mode Power-down mode Normal operating mode Sleep mode Normal operating mode Normal operating mode Subsleep mode Standby mode Standby mode Standby mode Standby mode Standby mode Rev. 1.50 Sep.
Section 8 RAM Section 8 RAM This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling the CPU to access both byte data and word data in two states. Product Classification Flash memory version (F-ZTAT version) Note: * H8/36109F RAM Size RAM Address 5 kbytes H'FFE400 to H'FFEFFF, H'FFF780 to H'FFFF7F* When the E7 is used, the area from H'FFF780 to H'FFFB7F must not be accessed. Rev. 1.50 Sep.
Section 8 RAM Rev. 1.50 Sep.
Section 9 I/O Ports Section 9 I/O Ports This LSI has seventy-nine general I/O ports and eight general input-only ports. Twenty ports are large current ports, which can drive 20 mA (@VOL = 1.5 V) when a low level signal is output. Any of these ports can become an input port immediately after a reset. They can also be used as I/O pins of the on-chip peripheral modules or external interrupt input pins, and these functions can be switched depending on the register settings.
Section 9 I/O Ports 9.1.1 Port Mode Register 1 (PMR1) PMR1 switches functions of pins in port 1 and port 2. Bit Bit Name Initial Value R/W Description 7 IRQ3 0 R/W Selects the function of pin P17/IRQ3/TRGV. 0: General I/O port 1: IRQ3/TRGV input pin 6 IRQ2 0 R/W Selects the function of pin P16/IRQ2. 0: General I/O port 1: IRQ2 input pin 5 IRQ1 0 R/W Selects the function of pin P15/IRQ1/TMIB1.
Section 9 I/O Ports 9.1.2 Port Control Register 1 (PCR1) PCR1 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 1. Bit Bit Name Initial Value R/W Description 7 PCR17 0 W 6 PCR16 0 W 5 PCR15 0 W When the corresponding pin is designated in PMR1 as a general I/O pin, setting a PCR1 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. 4 PCR14 0 W Bit 3 is a reserved bit.
Section 9 I/O Ports 9.1.4 Port Pull-Up Control Register 1 (PUCR1) PUCR1 controls the pull-up MOS in bit units of the pins set as the input ports. Bit Bit Name Initial Value R/W Description 7 PUCR17 0 R/W 6 PUCR16 0 R/W 5 PUCR15 0 R/W Only bits for which PCR1 is cleared are valid. The pullup MOSs of P17 to P14 and P12 to P10 pins enter the on-state when these bits are set to 1, while they enter the off-state when these bits are cleared to 0. 4 PUCR14 0 R/W Bit 3 is a reserved bit.
Section 9 I/O Ports • P16/IRQ2 pin Register PMR1 PCR1 Bit Name IRQ2 PCR16 Pin Function Setting value 0 0 P16 input pin 1 P16 output pin X IRQ2 input pin 1 [Legend] X: Don't care. • P15/IRQ1/TMIB1 pin Register PMR1 PCR1 Bit Name IRQ1 PCR15 Pin Function Setting value 0 0 P15 input pin 1 P15 output pin X IRQ1 input/TMIB1 input pin 1 [Legend] X: Don't care.
Section 9 I/O Ports • P11/PWM pin Register PMR1 PCR1 Bit Name PWM PCR11 Pin Function Setting value 0 0 P11 input pin 1 P11 output pin X PWM output pin 1 [Legend] X: Don't care. • P10/TMOW pin Register PMR1 PCR1 Bit Name TMOW PCR10 Pin Function Setting value 0 0 P10 input pin 1 P10 output pin X TMOW output pin 1 [Legend] X: Don't care. Rev. 1.50 Sep.
Section 9 I/O Ports 9.2 Port 2 Port 2 is a general I/O port also functioning as SCI3 I/O pins. Each pin of port 2 is shown in figure 9.2. The register settings of PMR1 and SCI3 have priority for functions of the pins for both uses. Port 2 P27 P26 P25 P24 P23 P22/TXD P21/RXD P20/SCK3 Figure 9.2 Port 2 Pin Configuration Port 2 has the following registers. • Port control register 2 (PCR2) • Port data register 2 (PDR2) • Port mode register 3 (PMR3) 9.2.
Section 9 I/O Ports 9.2.2 Port Data Register 2 (PDR2) PDR2 is a general I/O port data register of port 2. Bit Bit Name Initial Value R/W Description 7 P27 0 R/W PDR2 stores output data for port 2 pins. 6 P26 0 R/W 5 P25 0 R/W 4 P24 0 R/W If PDR2 is read while PCR2 bits are set to 1, the values stored in PDR2 are read. If PDR2 is read while PCR2 bits are cleared to 0, the pin states are read regardless of the value stored in PDR2.
Section 9 I/O Ports 9.2.4 Pin Functions The correspondence between the register specification and the port functions is shown below.
Section 9 I/O Ports • P23 pin Register PCR2 Bit Name PCR23 Pin Function Setting Value 0 P23 input pin 1 P23 output pin • P22/TXD pin Register PMR1 PCR2 Bit Name TXD PCR22 Pin Function Setting Value 0 0 P22 input pin 1 P22 output pin X TXD output pin 1 [Legend] X: Don't care. • P21/RXD pin Register SCR3 PCR2 Bit Name RE PCR21 Pin Function Setting Value 0 0 P21 input pin 1 P21 output pin X RXD input pin 1 [Legend] X: Don't care.
Section 9 I/O Ports 9.3 Port 3 Port 3 is a general I/O port. Each pin of port 3 is shown in figure 9.3. Port 3 P37 P36 P35 P34 P33 P32 P31 P30 Figure 9.3 Port 3 Pin Configuration Port 3 has the following registers. • Port control register 3 (PCR3) • Port data register 3 (PDR3) 9.3.1 Port Control Register 3 (PCR3) PCR3 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 3.
Section 9 I/O Ports 9.3.2 Port Data Register 3 (PDR3) PDR3 is a general I/O port data register of port 3. Bit Bit Name Initial Value R/W Description 7 P37 0 R/W PDR3 stores output data for port 3 pins. 6 P36 0 R/W 5 P35 0 R/W 4 P34 0 R/W If PDR3 is read while PCR3 bits are set to 1, the values stored in PDR3 are read. If PDR3 is read while PCR3 bits are cleared to 0, the pin states are read regardless of the value stored in PDR3.
Section 9 I/O Ports • P35 pin Register PCR3 Bit Name PCR35 Pin Function Setting Value 0 P35 input pin 1 P35 output pin • P34 pin Register PCR3 Bit Name PCR34 Setting Value 0 1 Pin Function P34 input pin P34 output pin • P33 pin Register PCR3 Bit Name PCR33 Setting Value 0 1 Pin Function P33 input pin P33 output pin • P32 pin Register PCR3 Bit Name PCR32 Setting Value 0 1 Pin Function P32 input pin P32 output pin • P31 pin Register PCR3 Bit Name PCR31 Setting Value 0 1 Pin F
Section 9 I/O Ports • P30 pin Register PCR3 Bit Name PCR30 Setting Value 0 1 9.4 Pin Function P30 input pin P30 output pin Port 5 Port 5 is a general I/O port also functioning as an I2C bus interface I/O pin and a wakeup interrupt input pin. Each pin of port 5 is shown in figure 9.4. The register setting of the I2C bus interface has priority for functions of the pins P57/SCL and P56/SDA.
Section 9 I/O Ports 9.4.1 Port Mode Register 5 (PMR5) PMR5 switches functions of pins in port 5. Bit Bit Name Initial Value R/W Description 7 POF57 0 R/W 6 POF56 0 R/W When the bit is set to 1, the corresponding pin is cut off by PMOS and it functions as the NMOS open-drain output. When cleared to 0, the pin functions as the CMOS output. 5 WKP5 0 R/W Selects the function of pin P55/WKP5. 0: General I/O port 1: WKP5 input pin 4 WKP4 0 R/W Selects the function of pin P54/WKP4.
Section 9 I/O Ports 9.4.2 Port Control Register 5 (PCR5) PCR5 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 5. Bit Bit Name Initial Value R/W Description 7 PCR57 0 W 6 PCR56 0 W 5 PCR55 0 W When each of the port 5 pins P57 to P50 functions as a general I/O port, setting a PCR5 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port.
Section 9 I/O Ports 9.4.4 Port Pull-Up Control Register 5 (PUCR5) PUCR5 controls the pull-up MOS in bit units of the pins set as the input ports. Bit Bit Name Initial Value R/W Description 7, 6 All 0 Reserved These bits are always read as 0. 5 PUCR55 0 R/W 4 PUCR54 0 R/W 3 PUCR53 0 R/W 2 PUCR52 0 R/W 1 PUCR51 0 R/W 0 PUCR50 0 R/W 9.4.5 Pin Functions Only bits for which PCR5 is cleared are valid.
Section 9 I/O Ports • P56/SDA pin Register ICCR1 PCR5 Bit Name ICE PCR56 Pin Function Setting Value 0 0 P56 input pin 1 P56 output pin X SDA I/O pin 1 [Legend] X: Don't care. SDA performs the NMOS open-drain output, that enables a direct bus drive. • P55/WKP5 pin Register PMR5 PCR5 Bit Name WKP5 PCR55 Pin Function Setting Value 0 0 P55 input pin 1 P55 output pin X WKP5 input pin 1 [Legend] X: Don't care.
Section 9 I/O Ports • P53/WKP3 pin Register PMR5 PCR5 Bit Name WKP3 PCR53 Pin Function Setting Value 0 0 P53 input pin 1 P53 output pin X WKP3 input pin 1 [Legend] X: Don't care. • P52/WKP2 pin Register PMR5 PCR5 Bit Name WKP2 PCR52 Pin Function Setting Value 0 0 P52 input pin 1 P52 output pin X WKP2 input pin 1 [Legend] X: Don't care.
Section 9 I/O Ports 9.5 Port 7 Port 7 is a general I/O port also functioning as a timer V I/O pin and SCI3_2 I/O pin. Each pin of port 7 is shown in figure 9.5. The register settings of the timer V and SCI3_2 have priority for functions of the pins for both uses. Port 7 P77 P76/TMOV P75/TMCIV P74/TMRIV P72/TXD_2 P71/RXD_2 P70/SCK3_2 Figure 9.5 Port 7 Pin Configuration Port 7 has the following registers. • Port control register 7 (PCR7) • Port data register 7 (PDR7) 9.5.
Section 9 I/O Ports 9.5.2 Port Data Register 7 (PDR7) PDR7 is a general I/O port data register of port 7. Bit Bit Name Initial Value R/W Description 7 P77 0 R/W PDR7 stores output data for port 7 pins. 6 P76 0 R/W 5 P75 0 R/W 4 P74 0 R/W If PDR7 is read while PCR7 bits are set to 1, the values stored in PDR7 are read. If PDR7 is read while PCR7 bits are cleared to 0, the pin states are read regardless of the value stored in PDR7. 3 1 Bit 3 is a reserved bit.
Section 9 I/O Ports • P75/TMCIV pin Register PCR7 Bit Name PCR75 Pin Function Setting Value 0 P75 input/TMCIV input pin 1 P75 output/TMCIV input pin • P74/TMRIV pin Register PCR7 Bit Name PCR74 Pin Function Setting Value 0 P74 input/TMRIV input pin 1 P74 output/TMRIV input pin • P72/TXD_2 pin Register PMR1 PCR7 Bit Name TXD2 PCR72 Pin Function Setting Value 0 0 P72 input pin 1 P72 output pin X TXD_2 output pin 1 [Legend] X: Don't care.
Section 9 I/O Ports • P70/SCK3_2 pin Register SCR3_2 SMR_2 PCR7 Bit Name CKE1 CKE0 COM PCR70 Pin Function Setting Value 0 0 0 0 P70 input pin 1 P70 output pin [Legend] 9.6 0 0 1 X SCK3_2 output pin 0 1 X X SCK3_2 output pin 1 X X X SCK3_2 input pin X: Don't care. Port 8 Port 8 is a general I/O port. Each pin of port 8 is shown in figure 9.6. Port 8 P87 P86 P85 Figure 9.6 Port 8 Pin Configuration Port 8 has the following registers.
Section 9 I/O Ports 9.6.2 Port Data Register 8 (PDR8) PDR8 is a general I/O port data register of port 8. Bit Bit Name Initial Value R/W Description 7 P87 0 R/W PDR8 stores output data for port 8 pins. 6 P86 0 R/W 5 P85 0 R/W If PDR8 is read while PCR8 bits are set to 1, the values stored in PDR8 are read. If PDR8 is read while PCR8 bits are cleared to 0, the pin states are read regardless of the value stored in PDR8. 4 to 0 All 1 Reserved These bits are always read as 1. 9.6.
Section 9 I/O Ports • P85 pin Register PCR8 Bit Name PCR85 Pin Function Setting Value 0 P85 input pin 1 P85 output pin 9.7 Port C Port C is a general I/O port. Each pin of port C is shown in figure 9.7. Port C PC3 PC2 PC1 PC0 Figure 9.7 Port C Pin Configuration Port C has the following registers. • Port control register C (PCRC) • Port data register C (PDRC) 9.7.1 Port Control Register C (PCRC) PCRC selects inputs/outputs in bit units for pins to be used as general I/O ports of port C.
Section 9 I/O Ports 9.7.2 Port Data Register C (PDRC) PDR9 is a general I/O port data register of port C. Bit Bit Name Initial Value R/W Description 7 to 4 All 1 Reserved These bits are always read as 1. 3 PC3 0 R/W PDRC stores output data for port C pins. 2 PC2 0 R/W 1 PC1 0 R/W 0 PC0 0 R/W If PDRC is read while PCRC bits are set to 1, the values stored in PDRC are read.
Section 9 I/O Ports • PC1 pin Register PCRC Bit Name PCRC1 Pin Function Setting Value 0 PC1 input pin 1 PC1 output pin • PC0 pin Register PCRC Bit Name PCRC0 Pin Function Setting Value 0 PC0 input pin 1 PC0 output pin 9.8 Port D Port D is a general I/O port also functioning as timer RD_0 I/O pins. Each pin of port D is shown in figure 9.8. The setting for the timer RD_0 function has priority over those for other functions.
Section 9 I/O Ports 9.8.1 Port Control Register D (PCRD) PCRD selects inputs/outputs in bit units for pins to be used as general I/O ports of port D. Bit Bit Name Initial Value R/W Description 7 PCRD7 0 W 6 PCRD6 0 W 5 PCRD5 0 W When each of the port D pins functions as a general I/O port, setting a PCRD bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port.
Section 9 I/O Ports 9.8.3 Pin Functions The correspondence between the register specification and the port functions is shown below.
Section 9 I/O Ports • PD6/FTIOC1 pin Register TRDOER 1_01 TRDFCR_01 Bit Name EC1 CMD1 and CMD0 Setting Value 1 XX 0 00 PWM3 PWMC1 IOC3 to IOC0 PCRD6 Pin Function X XXXX 0 PD6 input/FTIOC1 input pin 1 PD6 output pin 0 PD6 input/FTIOC1 input pin 1 PD6 output pin 0 1 Other than X 00 [Legend] X: Don't care. Rev. 1.50 Sep.
Section 9 I/O Ports • PD5/FTIOB1 pin Register TRDOER1 _01 Bit Name EB1 CMD1 and CMD0 PWM3 PWMB1 IOB2 to IOB0 PCRD5 Pin Function Setting Value 1 XX XXX 0 PD5 input/FTIOB1 input pin 1 PD5 output pin 0 PD5 input/FTIOB1 input pin 1 PD5 output pin 0 TRDFCR_01 00 X 0 1 Other than X 00 [Legend] TRDPMR TRDIORA _01 _1 PCRD X X XXX 1 XXX X FTIOB1 output pin 0 01X or 001 X FTIOB1 output pin 1XX or 000 0 PD5 input/FTIOB1 input pin 1 PD5 output pin X FTIOB1 output pin X XXX
Section 9 I/O Ports • PD4/FTIOA1 pin Register TRDOER1_ 01 Bit Name EA1 Setting Value 1 0 TRDFCR_01 TRDIORA_1 PCRD CMD1 and CMD0 PWM3 IOA2 to IOA0 PCRD4 Pin Function XX XXX 0 PD4 input/FTIOA1 input pin 1 PD4 output pin 0 PD4 input/FTIOA1 input pin 1 PD4 output pin 01X or 001 X FTIOA1 output pin 1XX or 000 0 PD4 input/FTIOA1 input pin 1 PD4 output pin X FTIOA1 output pin 00 X 0 1 Other than X 00 [Legend] X: Don't care. Rev. 1.50 Sep.
Section 9 I/O Ports • PD3/FTIOD0 pin Register TRDOER1 _01 Bit Name ED0 CMD1 and CMD0 PWM3 PWMD0 IOD3 to IOD0 PCRD3 Pin Function Setting Value 1 XX XXXX 0 PD3 input/FTIOD0 input pin 1 PD3 output pin 0 PD3 input/FTIOD0 input pin 1 PD3 output pin 0 TRDFCR_01 00 X 0 1 Other than X 00 [Legend] TRDPMR TRDIORC_ _01 0 PCRD X X XXXX 1 XXXX X FTIOD0 output pin 0 0XXX 0 PD3 input/FTIOD0 input pin 1 PD3 output pin 101X or 1001 X FTIOD0 output pin 11XX or 1000 0 PD3 input/FT
Section 9 I/O Ports • PD2/FTIOC0 pin Register TRDOER1 _01 Bit Name EC0 CMD1 and CMD0 PWM3 PWMC0 IOC3 to IOC0 PCRD2 Pin Function Setting Value 1 XX XXXX 0 PD2 input/FTIOC0 input pin 1 PD2 output pin 0 PD2 input/FTIOC0 input pin 1 PD2 output pin 0 TRDFCR_01 00 X 0 1 Other than X 00 [Legend] X: Don't care. Rev. 1.50 Sep.
Section 9 I/O Ports • PD1/FTIOB0 pin Register TRDOER1 _01 IOB2 to IOB0 PCRD1 Pin Function 1 XX X X XXX 0 0 00 0 1 X 1 0 XXX XXX 01X or 001 1XX or 000 PD1 input/FTIOB0 input pin PD1 output pin FTIOB0 output pin FTIOB0 output pin FTIOB0 output pin Other than X 00 [Legend] TRDPMR TRDIORA_ PCRD _01 0 CMD1 and PWM3 PWMB0 CMD0 Bit Name EB0 Setting Value TRDFCR_01 X XXX 1 X X X 0 1 X PD1 input/FTIOB0 input pin PD1 output pin FTIOB0 output pin X: Don't care. Rev. 1.50 Sep.
Section 9 I/O Ports • PD0/FTIOA0 pin Register TRDOER1 _01 TRDIORA PCRD _0 TRDFCR_01 Bit Name EA0 STCLK CMD1 and PWM3 CMD0 IOA2 to IOA0 PCRD0 Pin Function Setting Value 1 X XX X XXX 0 0 1 XX X XXX 1 0 0 00 0 1 XXX 01X or 001 1XX or 000 Other than X 00 XXX 1 X X 0 PD0 input/FTIOA0 input pin 1 0 PD0 output pin PD0 input/FTIOA0 input pin PD0 output pin 1 [Legend] 9.
Section 9 I/O Ports Port E has the following registers. • Port control register E (PCRE) • Port data register E (PDRE) 9.9.1 Port Control Register E (PCRE) PCRE selects inputs/outputs in bit units for pins to be used as general I/O ports of port E.
Section 9 I/O Ports 9.9.3 Pin Functions The correspondence between the register specification and the port functions is shown below. • PE7/FTIOD3 pin Register TRDOER1 _23 Bit Name ED1 Setting Value 1 0 TRDFCR_23 CMD1 and CMD0 PWM3 PWMD1 IOD3 to IOD0 PCRE7 Pin Function XX XXXX 0 PE7 input/FTIOD3 input pin 1 PE7 output pin 0 PE7 input/FTIOD3 input pin 1 PE7 output pin 00 X 0 1 Other than X 00 [Legend] X: Don't care. Rev. 1.50 Sep.
Section 9 I/O Ports • PE6/FTIOC3 pin Register TRDOER 1_23 Bit Name EC1 Setting Value 1 0 TRDFCR_23 TRDIOR C_3 PCRE CMD1 and CMD0 PWM IOC3 to 3 PWMC1 IOC0 PCRE 6 Pin Function XX X 0 PE6 input/FTIOC3 input pin 1 PE6 output pin 0 PE6 input/FTIOC3 input pin 1 PE6 output pin 00 0 1 Other than X 00 [Legend] TRDPM R_23 X X XXXX XXXX 1 XXXX X FTIOC3 output pin 0 0XXX 0 PE6 input/FTIOC3 input pin 1 PE6 output pin 101X or 1001 X FTIOC3 output pin 11XX or 1000 0 PE6 input/F
Section 9 I/O Ports • PE5/FTIOB3 pin Register TRDOER 1_23 Bit Name EB1 Setting Value 1 0 TRDFCR_23 PWM IOB2 to 3 PWMB1 IOB0 PCRE 5 Pin Function XX X 0 PE5 input/FTIOB3 input pin 1 PE5 output pin 0 PE5 input/FTIOB3 input pin 1 PE5 output pin 00 0 Other than X 00 X: Don't care. Rev. 1.50 Sep.
Section 9 I/O Ports • PE4/FTIOA3 pin TRDOER1_23 Bit Name EA1 CMD1 and PWM IOA2 to CMD0 3 IOA0 PCRE4 Pin Function Setting Value 1 XX 0 PE4 input/FTIOA3 input pin 1 PE4 output pin 0 PE4 input/FTIOA3 input pin 1 PE4 output pin 01X or 001 X FTIOA3 output pin 1XX or 000 0 PE4 input/FTIOA3 input pin 1 PE4 output pin X FTIOA3 output pin 0 TRDFCR_23 TRDIORA_ 3 Register 00 X 0 1 Other than X 00 [Legend] XXX XXX XXX PCRE X: Don't care. Rev. 1.50 Sep.
Section 9 I/O Ports • PE3/FTIOD2 pin Register TRDOER 1_23 Bit Name ED0 Setting Value 1 0 TRDFCR_23 PWM IOD3 to 3 PWMD0 IOD0 PCRE 3 Pin Function XX X 0 PE3 input/FTIOD2 input pin 1 PE3 output pin 0 PE3 input/FTIOD2 input pin 1 PE3 output pin 00 0 Other than X 00 X: Don't care. Rev. 1.50 Sep.
Section 9 I/O Ports • PE2/FTIOC2 pin Register TRDOER 1_23 Bit Name EC0 Setting Value 1 0 TRDFCR_23 TRDIOR C_2 PCRE CMD1 and CMD0 PWM IOC3 to 3 PWMC0 IOC0 PCRE 2 Pin Function XX X 0 PE2 input/FTIOC2 input pin 1 PE2 output pin 0 PE2 input/FTIOC2 input pin 1 PE2 output pin 00 0 1 Other than X 00 [Legend] TRDPM R_23 X X XXXX XXXX 1 XXXX X FTIOC2 output pin 0 0XXX 0 PE2 input/FTIOC2 input pin 1 PE2 output pin 101X or 1001 X FTIOC2 output pin 11XX or 1000 0 PE2 input/F
Section 9 I/O Ports • PE1/FTIOB2 pin Register TRDOER 1_23 Bit Name EB0 Setting Value 1 0 TRDFCR_23 PWM IOB2 to 3 PWMB0 IOB0 PCRE 1 Pin Function XX X 0 PE1 input/FTIOB2 input pin 1 PE1 output pin 00 X XXX 0 X XXX X FTIOB2 output pin 1 1 XXX X FTIOB2 output pin 0 01X or 001 X FTIOB2 output pin 1XX or 000 0 PE1 input/FTIOB2 input pin 1 PE1 output pin X FTIOB2 output pin X: Don't care. Rev. 1.50 Sep.
Section 9 I/O Ports • PE0/FTIOA2 pin Register TRDOER 1_23 Bit Name EA0 Setting Value 1 0 CMD1 and STCLK CMD0 IOA2 to PWM3 IOA0 PCRE0 Pin Function X X 0 PE0 input/FTIOA2 input pin 1 PE0 output pin 0 PE0 input/FTIOA2 input pin 1 PE0 output pin 1 0 XX XX 00 Other than 00 [Legend] TRDIOR A_2 PCRE TRDFCR_23 X XXX XXX 0 XXX X FTIOA2 output pin 1 01X or 001 X FTIOA2 output pin 1XX or 000 0 PE0 input/FTIOA2 input pin 1 PE0 output pin 0 FTIOA2 output pin X XXX X: Don't
Section 9 I/O Ports 9.10 Port F Port F is a general input port also functioning as A/D converter analog input pins. Each pin of port F is shown in figure 9.10. Port F PF7/AN7 PF6/AN6 PF5/AN5 PF4/AN4 PF3/AN3 PF2/AN2 PF1/AN1 PF0/AN0 Figure 9.10 Port F Pin Configuration Port F has the following registers. • Port data register F (PDRF) • Port mode register F (PMRF) 9.10.1 Port Data Register F (PDRF) PDRF is a general input port data register of port F.
Section 9 I/O Ports 9.10.2 Port Mode Register F (PMRF) PMRF switches functions of pins in port F. Bit Bit Name Initial Value R/W Description 7 to 1 All 1 Reserved These bits are always read as 1. 0 PMRF0 0 R/W This bit selects the function of pin PF0/AN0. 0: AN0 input pin 1: General input port 9.10.3 Pin Functions The correspondence between the register specification and the port functions is shown below.
Section 9 I/O Ports • PF5/AN5 pin Register ADCR ADCSR Bit Name CH3 SCAN CH2 CH1 CH0 Pin Function Setting Value 0 0 1 0 1 AN5 input pin 1 1 1 X 0 1 Other than above [Legend] PF5 input pin X: Don't care. • PF4/AN4 pin Register ADCR ADCSR Bit Name CH3 SCAN CH2 CH1 CH0 Pin Function Setting Value 0 0 1 0 0 AN4 input pin 1 1 X X Other than above [Legend] PF4 input pin X: Don't care.
Section 9 I/O Ports • PF1/AN1 pin Register ADCR ADCSR Bit Name CH3 SCAN CH2 CH1 CH0 Pin Function Setting Value 0 0 0 0 1 AN1 input pin 1 0 1 X 0 1 Other than above [Legend] PF1 input pin X: Don't care. • PF0/AN0 pin Register PMRF ADCR Bit Name PF0 CH3 SCAN CH2 CH1 CH0 Pin Function 0 0 0 0 0 AN0 input pin 1 0 X X Setting Value 0 ADCSR Other than above [Legend] 9.11 PF0 input pin X: Don't care.
Section 9 I/O Ports Port G has the following registers. • Port control register G (PCRG) • Port data register G (PDRG) • Port mode register G (PMRG) 9.11.1 Port Control Register G (PCRG) PCRG selects inputs/outputs in bit units for pins to be used as general I/O ports of port G.
Section 9 I/O Ports 9.11.3 Port Mode Register G (PMRG) PMRG switches functions of pins in port G. Bit Bit Name Initial Value R/W 7 PMRG7 0 R/W Description This bit selects the function of pin PG7/AN15/TRDOI_1. 0: General I/O port 1: AN15/TRDOI_1 input pin 6 PMRG6 0 R/W This bit selects the function of pin PG6/AN14/TRDOI_0. 0: General I/O port 1: AN14/TRDOI_0 input pin 5 PMRG5 0 R/W This bit selects the function of pin PG5/AN13/TRCOI.
Section 9 I/O Ports 9.11.4 Pin Functions The correspondence between the register specification and the port functions is shown below. • PG7/AN15/TRDOI_1 pin Register ADCR Bit Name CH3 Setting Value 1 ADCSR PMRG SCAN CH2 CH1 CH0 X 1 1 1 Other than above [Legend] PCRG PMRG7 PCRG7 Pin Function X X AN15 input pin 1 X TRDOI_1 input pin 0 0 PG7 input pin 1 PG7 output pin X: Don't care.
Section 9 I/O Ports • PG5/AN13/TRCOI pin Register ADCR Bit Name CH3 ADCSR PMRG PCRG SCAN CH2 CH1 CH0 PMRG5 PCRG5 Pin Function Setting Value 1 X 1 0 1 X X AN13 input pin 1 1 1 1 0 X X 1 1 1 1 1 X X 1 X Other than above 0 [Legend] TRCOI input pin 0 PG5 input pin 1 PG5 output pin X: Don't care.
Section 9 I/O Ports • PG2/AN10 pin Register ADCR ADCSR PCRG Bit Name CH3 SCAN CH2 CH1 CH0 PCRG2 Pin Function Setting Value 1 X 0 1 0 X AN10 input pin 1 1 0 1 1 X Other than above [Legend] 0 PG2 input pin 1 PG2 output pin X: Don't care.
Section 9 I/O Ports 9.12 Port H Port H is a general I/O port also functioning as SCI3_3 I/O pins, timer RC input pins, and A/D converter input pins. Each pin of port H is shown in figure 9.12. The settings for the SCI3_3 and timer RC functions have priority over those for other functions. PH7/FTIOD PH6/FTIOC PH5/FTIOB PH4/FTIOA/TRGC PH3/FTCI PH2/TXD_3 PH1/RXD_3 PH0/SCK3_3/ADTRG Port H Figure 9.12 Port H Pin Configuration Port H has the following registers.
Section 9 I/O Ports 9.12.2 Port Data Register H (PDRH) PDRH is a general I/O port data register of port H. Bit Bit Name Initial Value R/W Description 7 PH7 0 R/W PDRH stores output data for port H pins. 6 PH6 0 R/W 5 PH5 0 R/W 4 PH4 0 R/W If PDRH is read while PCRH bits are set to 1, the values stored in PDRH are read. If PDRH is read while PCRH bits are cleared to 0, the pin states are read regardless of the value stored in PDRH.
Section 9 I/O Ports • PH6/FTIOC pin Register TRCOER Bit Name EC PWM2 PWMC IOC2 IOC1 IOC0 PCRH6 Pin Function Setting Value 1 X X X X 0 PH6 input/FTIOC input pin 1 PH6 output pin 0 PH6 input/FTIOC input pin 1 PH6 output pin 0 TRCMR 0 1 X X TRCIOR1 X X 1 X X X X FTIOC (PWM) output pin 0 0 1 X X FTIOC output pin 0 1 X FTIOC output pin 0 0 PH6 input/FTIOC input pin 1 PH6 output pin 0 PH6 input/FTIOC input pin 1 PH6 output pin 1 [Legend] X PCRH X X X:
Section 9 I/O Ports • PH4/FTIOA/TRGC pin Register TRCOER Bit Name EA PWM2 IOA2 IOA1 IOA0 PCRH4 Pin Function Setting Value 1 X X X X 0 PH4 input/FTIOA input /TRGC input pin 1 PH4 output pin 0 PH4 input/FTIOA input /TRGC input pin 1 PH4 output pin 0 TRCMR 0 1 TRCIOR0 X 0 1 [Legend] X PCRH X 1 X X FTIOA output pin 0 1 X FTIOA output pin 0 0 PH4 input/FTIOA input /TRGC input pin 1 PH4 output pin 0 PH4 input/FTIOA input /TRGC input pin 1 PH4 output pin X X
Section 9 I/O Ports • PH2/TXD_3 pin Register SMCR PCRH Bit Name TXD_3 PCRH2 Pin Function Setting Value 0 0 PH2 input pin 1 PH2 output pin X TXD_3 output pin 1 [Legend] X: Don't care. • PH1/RXD_3 pin Register SCR3_3 PCRH Bit Name RE PCRH1 Pin Function Setting Value 0 0 PH1 input pin 1 PH1 output pin X RXD_3 input pin 1 [Legend] X: Don't care.
Section 9 I/O Ports 9.13 Port J Port J is a general I/O port also functioning as external oscillation pins and a clock output pin. Each pin of port J is shown in figure 9.13. The setting of CKCSR has priority over those for other functions. PJ1/OSC2/CLKOUT PJ0/OSC1 Port J Figure 9.13 Port J Pin Configuration Port J has the following registers. • Port control register J (PCRJ) • Port data register J (PDRJ) 9.13.
Section 9 I/O Ports 9.13.2 Port Data Register J (PDRJ) PDRJ is a general I/O port data register of port J. Bit Bit Name Initial Value R/W Description 7 to 2 Reserved 1 PJ1 0 R/W PDRJ stores output data for port J pins. 0 PJ0 0 R/W If PDRJ is read while PCRJ bits are set to 1, the values stored in PDRJ are read. If PDRJ is read while PCRJ bits are cleared to 0, the pin states are read regardless of the value stored in PDRJ. 9.13.
Section 9 I/O Ports Rev. 1.50 Sep.
Section 10 Realtime Clock (RTC) Section 10 Realtime Clock (RTC) The realtime clock (RTC) is a timer used to count time ranging from a second to a week. Figure 10.1 shows the block diagram of the RTC. 10.
Section 10 Realtime Clock (RTC) 10.2 Input/Output Pin Table 10.1 shows the RTC input/output pin. Table 10.1 Pin Configuration Name Abbreviation I/O Function Clock output TMOW Output RTC divided clock output 10.3 Register Descriptions The RTC has the following registers.
Section 10 Realtime Clock (RTC) Bit Bit Name Initial Value R/W Description 6 SC12 — R/W Counting Ten's Position of Seconds 5 SC11 — R/W Counts on 0 to 5 for 60-second counting. 4 SC10 — R/W 3 SC03 — R/W Counting One's Position of Seconds 2 SC02 — R/W 1 SC01 — R/W Counts on 0 to 9 once per second. When a carry is generated, 1 is added to the ten's position. 0 SC00 — R/W 10.3.
Section 10 Realtime Clock (RTC) 10.3.3 Hour Data Register (RHRDR) RHRDR counts the BCD-coded hour value on the carry generated once per hour by RMINDR. The setting range is either decimal 00 to 11 or 00 to 23 by the selection of the 12/24 bit in RTCCR1. Bit Bit Name Initial Value R/W Description 7 BSY — R RTC Busy This bit is set to 1 when the RTC is updating (operating) the values of second, minute, hour, and day-of-week data registers.
Section 10 Realtime Clock (RTC) 10.3.4 Day-of-Week Data Register (RWKDR) RWKDR counts the BCD-coded day-of-week value on the carry generated once per day by RHRDR. The setting range is decimal 0 to 6 using bits WK2 to WK0. Bit Bit Name Initial Value R/W Description 7 BSY — R RTC Busy This bit is set to 1 when the RTC is updating (operating) the values of second, minute, hour, and day-of-week data registers.
Section 10 Realtime Clock (RTC) 10.3.5 RTC Control Register 1 (RTCCR1) RTCCR1 controls start/stop and reset of the clock timer. For the definition of time expression, see figure 10.2. Bit Bit Name Initial Value R/W Description 7 RUN — R/W 6 12/24 — R/W 5 PM — R/W 4 RST 0 R/W 3 INT — R/W RTC Operation Start 0: Stops RTC operation 1: Starts RTC operation Operating Mode 0: RTC operates in 12-hour mode. RHRDR counts on 0 to 11. 1: RTC operates in 24-hour mode.
Section 10 Realtime Clock (RTC) 10.3.6 RTC Control Register 2 (RTCCR2) RTCCR2 controls RTC periodic interrupts of weeks, days, hours, minutes, and seconds. Enabling interrupts of weeks, days, hours, minutes, and seconds sets the IRRTA flag to 1 in the interrupt flag register 1 (IRR1) when an interrupt occurs. It also controls an overflow interrupt of a free running counter when RTC operates as a free running counter.
Section 10 Realtime Clock (RTC) 10.3.7 Clock Source Select Register (RTCCSR) RTCCSR selects clock source. A free running counter controls start/stop of counter operation by the RUN bit in RTCCR1. When a clock other than 32.768 kHz is selected, the RTC is disabled and operates as an 8-bit free running counter. When the RTC operates as an 8-bit free running counter, RSECDR enables counter values to be read.
Section 10 Realtime Clock (RTC) 10.4 Operation 10.4.1 Initial Settings of Registers after Power-On The RTC registers that store second, minute, hour, and day-of week data are not reset by a RES input. Therefore, all registers must be set to their initial values after power-on. Once the register settings are made, the RTC provides an accurate time as long as power is supplied regardless of a RES input. 10.4.2 Initial Setting Procedure Figure 10.3 shows the procedure for the initial setting of the RTC.
Section 10 Realtime Clock (RTC) 10.4.3 Data Reading Procedure When the seconds, minutes, hours, or day-of-week datum is updated while time data is being read, the data obtained may not be correct, and so the time data must be read again. Figure 10.4 shows an example in which correct data is not obtained. In this example, since only RSECDR is read after data update, about 1-minute inconsistency occurs. To avoid reading in this timing, the following processing must be performed. 1.
Section 10 Realtime Clock (RTC) 10.5 Interrupt Sources There are five kinds of RTC interrupts: week interrupts, day interrupts, hour interrupts, minute interrupts, and second interrupts. When using an interrupt, initiate the RTC last after other registers are set. Do not set multiple interrupt enable bits in RTCCR2 simultaneously to 1. When an interrupt request of the RTC occurs, the IRRTA flag in IRR1 is set to 1. When clearing the flag, write 0. Table 10.
Section 10 Realtime Clock (RTC) Rev. 1.50 Sep.
Section 11 Timer B1 Section 11 Timer B1 Timer B1 is an 8-bit timer that increments each time a clock pulse is input. This timer has two operating modes, interval and auto reload. Figure 11.1 shows a block diagram of timer B1. 11.1 Features • Selection of seven internal clock sources (φ/8192, φ/2048, φ/512, φ/256, φ/64, φ/16, and φ/4) or an external clock (can be used to count external events). • An interrupt is generated when the counter overflows.
Section 11 Timer B1 11.3 Register Descriptions The timer B1 has the following registers. • Timer mode register B1 (TMB1) • Timer counter B1 (TCB1) • Timer load register B1 (TLB1) 11.3.1 Timer Mode Register B1 (TMB1) TMB1 selects the auto-reload function and input clock. Bit Bit Name Initial Value R/W Description 7 TMB17 0 R/W Auto-Reload Function Select 0: Interval timer function selected 1: Auto-reload function selected 6 to 3 All 1 Reserved These bits are always read as 1.
Section 11 Timer B1 11.3.2 Timer Counter B1 (TCB1) TCB1 is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock source for input to this counter is selected by bits TMB12 to TMB10 in TMB1. TCB1 values can be read by the CPU at any time. When TCB1 overflows from H'FF to H'00 or to the value set in TLB1, the IRRTB1 flag in IRR2 is set to 1. TCB1 is allocated to the same address as TLB1. TCB1 is initialized to H'00. 11.3.
Section 11 Timer B1 11.4.2 Auto-Reload Timer Operation Setting bit TMB17 in TMB1 to 1 causes timer B1 to function as an 8-bit auto-reload timer. When a reload value is set in TLB1, the same value is loaded into TCB1, becoming the value from which TCB1 starts its count. After the count value in TCB1 reaches H'FF, the next clock signal input causes timer B1 to overflow. The TLB1 value is then loaded into TCB1, and the count continues from that value.
Section 12 Timer V Section 12 Timer V Timer V is an 8-bit timer based on an 8-bit counter. Timer V counts external events. Comparematch signals with two registers can also be used to reset the counter, request an interrupt, or output a pulse signal with an arbitrary duty cycle. Counting can be initiated by a trigger input at the TRGV pin, enabling pulse output control to be synchronized to the trigger, with an arbitrary delay from the trigger input. Figure 12.1 shows a block diagram of timer V. 12.
Section 12 Timer V TCRV1 TCORB Trigger control TRGV Comparator Clock select TCNTV Internal data bus TMCIV Comparator φ PSS TCORA Clear control TMRIV TCRV0 Interrupt request control Output control TMOV [Legend] TCORA: TCORB: TCNTV: TCSRV: TCRV0: Time constant register A Time constant register B Timer counter V Timer control/status register V Timer control register V0 TCSRV TCRV1: PSS: CMIA: CMIB: OVI: Timer control register V1 Prescaler S Compare-match interrupt A Compare-match interrupt
Section 12 Timer V 12.3 Register Descriptions Time V has the following registers. • • • • • • Timer counter V (TCNTV) Timer constant register A (TCORA) Timer constant register B (TCORB) Timer control register V0 (TCRV0) Timer control/status register V (TCSRV) Timer control register V1 (TCRV1) 12.3.1 Timer Counter V (TCNTV) TCNTV is an 8-bit up-counter. The clock source is selected by bits CKS2 to CKS0 in timer control register V0 (TCRV0).
Section 12 Timer V 12.3.3 Timer Control Register V0 (TCRV0) TCRV0 selects the input clock signals of TCNTV, specifies the clearing conditions of TCNTV, and controls each interrupt request. Bit Bit Name Initial Value R/W Description 7 CMIEB 0 R/W 6 CMIEA 0 R/W 5 OVIE 0 R/W 4 3 CCLR1 CCLR0 0 0 R/W R/W 2 1 0 CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Compare Match Interrupt Enable B When this bit is set to 1, interrupt request from the CMFB bit in TCSRV is enabled.
Section 12 Timer V Table 12.
Section 12 Timer V Bit Bit Name Initial Value R/W Description 5 OVF 0 R/W Timer Overflow Flag Setting condition: When TCNTV overflows from H'FF to H'00 Clearing condition: After reading OVF = 1, cleared by writing 0 to OVF 4 1 Reserved This bit is always read as 1. 3 OS3 0 R/W Output Select 3 and 2 2 OS2 0 R/W These bits select an output method for the TOMV pin by the compare match of TCORB and TCNTV.
Section 12 Timer V 12.3.5 Timer Control Register V1 (TCRV1) TCRV1 selects the edge at the TRGV pin, enables TRGV input, and selects the clock input to TCNTV. Bit Bit Name Initial Value R/W Description 7 to 5 All 1 Reserved 4 TVEG1 0 R/W TRGV Input Edge Select 3 TVEG0 0 R/W These bits select the TRGV input edge. These bits are always read as 1.
Section 12 Timer V 12.4 Operation 12.4.1 Timer V Operation 1. According to table 12.2, six internal/external clock signals output by prescaler S can be selected as the timer V operating clock signals. When the operating clock signal is selected, TCNTV starts counting-up. Figure 12.2 shows the count timing with an internal clock signal selected, and figure 12.3 shows the count timing with both edges of an external clock signal selected. 2.
Section 12 Timer V φ Internal clock TCNTV input clock TCNTV N–1 N N+1 Figure 12.2 Increment Timing with Internal Clock φ TMCIV (External clock input pin) TCNTV input clock TCNTV N–1 N N+1 Figure 12.3 Increment Timing with External Clock φ TCNTV H'FF H'00 Overflow signal OVF Figure 12.4 OVF Set Timing Rev. 1.50 Sep.
Section 12 Timer V φ TCNTV N TCORA or TCORB N N+1 Compare match signal CMFA or CMFB Figure 12.5 CMFA and CMFB Set Timing φ Compare match A signal Timer V output pin Figure 12.6 TMOV Output Timing φ Compare match A signal TCNTV N H'00 Figure 12.7 Clear Timing by Compare Match φ TMRIV (External counter reset input pin) TCNTV reset signal TCNTV N–1 N H'00 Figure 12.8 Clear Timing by TMRIV Input Rev. 1.50 Sep.
Section 12 Timer V 12.5 Timer V Application Examples 12.5.1 Pulse Output with Arbitrary Duty Cycle Figure 12.9 shows an example of output of pulses with an arbitrary duty cycle. 1. Set bits CCLR1 and CCLR0 in TCRV0 so that TCNTV will be cleared by compare match with TCORA. 2. Set bits OS3 to OS0 in TCSRV so that the output will go to 1 at compare match with TCORA and to 0 at compare match with TCORB. 3. Set bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1 to select the desired clock source. 4.
Section 12 Timer V 12.5.2 Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input The trigger function can be used to output a pulse with an arbitrary pulse width at an arbitrary delay from the TRGV input, as shown in figure 12.10. To set up this output: 1. Set bits CCLR1 and CCLR0 in TCRV0 so that TCNTV will be cleared by compare match with TCORB. 2. Set bits OS3 to OS0 in TCSRV so that the output will go to 1 at compare match with TCORA and to 0 at compare match with TCORB. 3.
Section 12 Timer V 12.6 Usage Notes The following types of contention or operation can occur in timer V operation. 1. 2. 3. 4. Writing to registers is performed in the T3 state of a TCNTV write cycle. If a TCNTV clear signal is generated in the T3 state of a TCNTV write cycle, as shown in figure 12.11, clearing takes precedence and the write to the counter is not carried out. If counting-up is generated in the T3 state of a TCNTV write cycle, writing takes precedence.
Section 12 Timer V TCORA write cycle by CPU T2 T3 T1 φ TCORA address Address Internal write signal TCNTV N TCORA N N+1 M TCORA write data Compare match signal Inhibited Figure 12.12 Contention between TCORA Write and Compare Match Clock before switching Clock after switching Count clock TCNTV N N+1 N+2 Write to CKS1 and CKS0 Figure 12.13 Internal Clock Switching and TCNTV Operation Rev. 1.50 Sep.
Section 13 Timer RC Section 13 Timer RC Timer RC is a 16-bit timer having output compare and input capture functions. Timer RC can count external events and output pulses with a desired duty cycle using the compare match function between the timer counter and four general registers. Thus, it can be applied to various systems. 13.
Section 13 Timer RC Table 13.1 summarizes the timer RC functions, and figure 13.1 shows a block diagram of timer RC. Table 13.
Section 13 Timer RC Internal clock: φ φ/2 φ/4 φ/8 φ/32 φ40M FTIOA/TRGC Clock selecter FTIOB FTIOC Control logic External clock: FTCI FTIOD Comparator TRCOI TRCDF TRCOER TRCIOR1 TRCIOR0 TRCSR TRCIER TRCCR2 TRCCR1 GRD GRC TMCMR Bus interface [Legend] TMCMR: TRCCR1: TRCCR2: TRCIER: TRCSR: TRCIOR0: TRCIOR1: TRCOER: TRCDF: TRCCNT: GRA: GRB: GRC: GRD: GRB GRA TRCCNT IRRTRG Internal data bus Timer RC mode register (8 bits) Timer RC control register 1 (8 bits) Timer RC control register 2
Section 13 Timer RC 13.2 Input/Output Pins Table 13.2 summarizes the timer RC pins. Table 13.
Section 13 Timer RC 13.3 Register Descriptions Timer RC has the following registers.
Section 13 Timer RC 13.3.1 Timer RC Mode Register (TRCMR) TRCMR selects the general register functions and the timer output mode. Bit Bit Name Initial Value R/W Description 7 CTS 0 R/W Counter Start TRCCNT stops counting when this bit is 0, while it performs counting when this bit is 1.
Section 13 Timer RC Bit Bit Name Initial Value R/W Description 2 PWMD 0 R/W PWM Mode D Selects the output mode of the FTIOD pin. 0: Functions in timer mode 1: Functions in PWM mode 1 PWMC 0 R/W PWM Mode C Selects the output mode of the FTIOC pin. 0: Functions in timer mode 1: Functions in PWM mode 0 PWMB 0 R/W PWM Mode B Selects the output mode of the FTIOB pin. 0: Functions in timer mode 1: Functions in PWM mode Rev. 1.50 Sep.
Section 13 Timer RC 13.3.2 Timer RC Control Register 1 (TRCCR1) TRCCR1 specifies the source of the counter clock, clearing conditions, and initial output levels of TRCCNT. Bit Bit Name Initial Value R/W Description 7 CCLR 0 R/W 6 5 4 CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W 3 TOD 0 R/W Counter Clear The TRCCNT value is cleared by compare match A when this bit is 1. When it is 0, TRCCNT functions as a freerunning counter. Clock Select 2 to 0 Select the source of the clock input to TRCCNT.
Section 13 Timer RC Bit Bit Name Initial Value R/W Description 1 TOB 0 R/W 0 TOA 0 R/W Timer Output Level Setting B Sets the output value of the FTIOB pin until the first compare match B is generated. In PWM mode, controls the output polarity of the FTIOB pin. 0: Output value is 0* 1: Output value is 1* Timer Output Level Setting A Sets the output value of the FTIOA pin until the first compare match A is generated. 0: Output value is 0* 1: Output value is 1* [Legend] X: Don't care.
Section 13 Timer RC 13.3.4 Timer RC Interrupt Enable Register (TRCIER) TRCIER controls the timer RC interrupt request. Bit Bit Name Initial Value R/W Description 7 OVIE 0 R/W Timer Overflow Interrupt Enable When this bit is set to 1, an FOVI interrupt requested by the OVF flag in TRCSR is enabled. 6 to 4 All 1 Reserved These bits are always read as 1.
Section 13 Timer RC 13.3.5 Timer RC Status Register (TRCSR) TRCSR shows the status of interrupt requests. Bit Bit Name Initial Value R/W Description 7 OVF 0 R/W Timer Overflow Flag [Setting condition] When TRCCNT overflows from H'FFFF to H'0000 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF 6 to 4 All 1 Reserved These bits are always read as 1.
Section 13 Timer RC Bit Bit Name Initial Value R/W Description 1 IMFB 0 R/W Input Capture/Compare Match Flag B [Setting conditions] • TRCCNT = GRB when GRB functions as an output compare register • The TRCCNT value is transferred to GRB by an input capture signal when GRB functions as an input capture register • TRCCNT = GRB when the PWMB bit is set to 1 or the PWM2 bit to 0 in TRCMR [Clearing condition] Read IMFB when IMFB = 1, then write 0 in IMFB 0 IMFA 0 R/W Input Capture/Compare Mat
Section 13 Timer RC 13.3.6 Timer RC I/O Control Register 0 (TRCIOR0) TRCIOR0 selects the functions of GRA and GRB, and specifies the functions of the FTIOA and FTIOB pins. Bit Bit Name Initial Value R/W Description 7 1 Reserved This bit is always read as 1. 6 IOB2 0 R/W I/O Control B2 Selects the GRB function.
Section 13 Timer RC Bit Bit Name Initial Value R/W Description 1 IOA1 0 R/W I/O Control A1 and A0 0 IOA0 0 R/W When IOA2 = 0, 00: No output at compare match 01: 0 output to the FTIOA pin at GRA compare match 10: 1 output to the FTIOA pin at GRA compare match 11: Output toggles to the FTIOA pin at GRA compare match When IOA2 = 1, 00: Input capture at rising edge of the FTIOA pin 01: Input capture at falling edge of the FTIOA pin 1X: Input capture at rising and falling edges of the FTIOA pin [
Section 13 Timer RC 13.3.7 Timer RC I/O Control Register 1 (TRCIOR1) TRCIOR1 selects the functions of GRC and GRD, and specifies the functions of the FTIOC and FTIOD pins. Bit Bit Name Initial Value R/W Description 7 1 Reserved 6 IOD2 0 R/W I/O Control D2 This bit is always read as 1. Selects the GRD function.
Section 13 Timer RC Bit Bit Name Initial Value R/W Description 1 IOC1 0 R/W I/O Control C1 and C0 0 IOC0 0 R/W When IOC2 = 0, 00: No output at compare match 01: 0 output to the FTIOC pin at GRC compare match 10: 1 output to the FTIOC pin at GRC compare match 11: Output toggles to the FTIOC pin at GRC compare match When IOC2 = 1, 00: Input capture to GRC at rising edge of the FTIOC pin 01: Input capture to GRC at falling edge of the FTIOC pin 1X: Input capture to GRC at rising and falling edge
Section 13 Timer RC 13.3.8 Timer RC Output Enable Register (TRCOER) TRCOER enables or disables the timer outputs. When setting the PTO bit to 1 and driving the TRCOI signal low, the ED, EC, EB and EA bits are set to 1 and timer RC outputs are disabled.
Section 13 Timer RC 13.3.9 Timer RC Digital Filtering Function Select Register (TRCDF) TRCDF enables or disables the digital filter for each of the FTIOA to FTIOD and TRGC pin. The setting in this register is valid on the corresponding pin when the FTIOA to FTIOA inputs are enabled by TRCIOR0 and TRCIOR1 and the TRGC input is selected by bits TCEG1 and TCEG0 in TRCCR2.
Section 13 Timer RC 13.3.10 Timer RC Counter (TRCCNT) TRCCNT is a 16-bit readable/writable up-counter. The input clock is selected by bits CKS2 to CKS0 in TRCCR1. TRCCNT can be cleared to H'0000 through a compare match of GRA by setting the CCLR bit in TRCCR1 to 1. When TRCCNT overflows (changes from H'FFFF to H'0000), the OVF flag in TRCSR is set to 1. If the OVIE bit in TRCIER is set to 1 at this time, an interrupt request is generated.
Section 13 Timer RC 13.4 Operation Timer RC has the following operating modes.
Section 13 Timer RC • FTIOB pin Register Name TRCOER Bit Name EB Setting values 0 0 0 0 TRCMR TRCIOR0 PWMB IOB2 to IOB0 Function 0 X XXX PWM2 mode waveform output 1 1 XXX PWM mode waveform output 1 0 001, 01X Timer mode waveform output (output compare function) 1 0 1XX Timer mode (input capture function) PWM2 1 Other than above General I/O port [Legend] X: Don't care.
Section 13 Timer RC • FTIOD pin Register Name TRCOER Bit Name ED PWM2 PWMD IOD2 to IOD0 Function Setting values 0 1 1 XXX PWM mode waveform output 0 1 0 001, 01X Timer mode waveform output (output compare function) 0 1 0 1XX Timer mode (input capture function) TRCMR TRCIOR1 1 Other than above General I/O port [Legend] X: Don't care. 13.4.1 Timer Mode Operation TRCCNT performs free-running or periodic counting operations. After a reset, TRCCNT is set as a free-running counter.
Section 13 Timer RC Periodic counting operation can be performed when GRA is set as an output compare register and the CCLR bit in TRCCR1 is set to 1. When the counter value matches GRA, TRCCNT is cleared to H'0000, the IMFA flag in TRCSR is set to 1. If the corresponding IMIEA bit in TRCIER is set to 1, an interrupt request is generated. TRCCNT continues counting from H'0000. Figure 13.3 shows an example of periodic counting. TRCCNT GRA H'0000 Time CTS bit Flag cleared by software IMFA Figure 13.
Section 13 Timer RC Figure 13.5 shows an example of toggled output when TRCCNT functions as a free-running counter, and the toggled output is selected for both compare matches A and B. TRCCNT H'FFFF GRA GRB Time H'0000 FTIOA Output toggled FTIOB Output toggled Figure 13.5 Toggle Output Example (TOA = 0, TOB = 1) Figure 13.6 shows another example of toggled output when TRCCNT functions as a periodic counter on both compare matches A and B.
Section 13 Timer RC The TRCCNT value can be captured into a general register (GRA, GRB, GRC, or GRD) when signal levels are changed on an input-capture pin (FTIOA, FTIOB, FTIOC, or FTIOD) by specifying the general register as an input capture register. The capture timing can be selected from the rising, falling, or both edges. By using the input-capture function, the width or cycle of a pulse can be measured. Figure 13.
Section 13 Timer RC Figure 13.8 shows an example of buffer operation when GRA is set as an input-capture register and GRC is set as the buffer register for GRA. TRCCNT functions as a free-running counter and is captured at both rising and falling edges of the FTIOA signal. Due to the buffer operation, the GRA value is transferred to GRC on an input-capture A and the TRCCNT value is stored in GRA.
Section 13 Timer RC 13.4.2 PWM Mode Operation In PWM mode, PWM waveforms are generated by using GRA as the cycle register and GRB, GRC, and GRD as duty cycle registers. PWM waveforms are output from the FTIOB, FTIOC, and FTIOD pins. Up to three-phase PWM waveforms can be output. In PWM mode, a general register functions as an output compare register automatically. The output level of each pin depends on the corresponding timer output level set bit (TOB, TOC, or TOD) in TRCCR1.
Section 13 Timer RC TRCCNT Counter cleared by compare match A GRA GRB GRC GRD H'0000 Time FTIOB FTIOC FTIOD Figure 13.10 PWM Mode Example (2) Figure 13.11 shows an example of buffer operation when the FTIOB pin is set to PWM mode and GRD is set as the buffer register for GRB. TRCCNT is cleared on compare match A, and the FTIOB pin outputs 1 on compare match B and 0 on compare match A.
Section 13 Timer RC Figures 13.12 and 13.13 show examples of the output of PWM waveforms with duty cycles of 0% and 100%. TRCCNT GRB changed GRA GRB GRB changed H'0000 Time Duty cycle 0% FTIOB TRCCNT GRB changed Output levels of FTIOB are not changed when compare matches of cycle register and duty cycle register occur simultaneously.
Section 13 Timer RC TRCCNT GRB changed GRA GRB GRB changed H'0000 Time Duty cycle 100% FTIOB TRCCNT GRB changed Output levels of FTIOB are not changed when compare matches of cycle register and duty cycle register occur simultaneously. GRA GRB changed GRB changed GRB H'0000 Time Duty cycle 0% FTIOB Output levels of FTIOB are not changed when compare matches of cycle register and duty cycle register occur simultaneously.
Section 13 Timer RC 13.4.3 PWM2 Mode Operation In PWM2 mode, waveforms are output on the FTIOB pin when a compare match occurs on GRB or GRC. GRD functions as a buffer register for GRB by setting the BUFEB bit in TRCMR to 1. The output level of the FTIOB signal is specified by the TOB bit in TRCCR1. When TOB = 0, 1 is output on a compare match of GRC and 0 is output on a compare match of GRB. When TOB = 1, 0 is output on a compare match of GRC and 1 is output on a compare match of GRB. Table 13.
Section 13 Timer RC Trigger signal FTIOA/TRGC Counter clear signal Input control TRCCNT Compare match signal Comparator GRA Comparator GRB Comparator GRC Compare match signal FTIOB Output control Compare match signal Figure 13.14 Block Diagram in PWM2 Mode φ TRCCNT L GRA L GRD M GRB N H'0000 M Compare match signal Figure 13.15 GRD and GRB Buffer Operating Timing in PWM2 Mode (1) Rev. 1.50 Sep.
Section 13 Timer RC φ TRCCNT N GRA L GRD M GRB N N+1 H'0000 M Counter clear signal by trigger input Figure 13.16 GRD and GRB Buffer Operating Timing in PWM2 Mode (2) In PWM2 mode, a pulse with a specified pulse width can be output on the FTIOB pin when a specified delay time has elapsed since the TRGC signal was asserted. An assertion of the TRGC signal starts counting up. Arbitrary values can be specified for the pulse width and delay time. Figures 13.17 and 13.
Section 13 Timer RC The value of TRCCNT H'FFFF GRA GRB GRC H'0000 Time FTIOA/TRGC FTIOB (Output transformation when TOB = 0) When TOB = 0, the trigger input is ignored while the FTIOB pin is driven high, whereas when TOB = 1, the trigger input is ignored while the FTIOB pin is driven low FTIOB (Output transformation when TOB = 1) GRD A GRB B D C A B C D Figure 13.
Section 13 Timer RC The value of TRCCNT H'FFFF GRA GRB GRC H'0000 Time CTS High FTIOA/TRGC FTIOB (Output transformation when TOB = 0) FTIOB (Output transformation when TOB = 1) Figure 13.19 Example of Stopping Operation of the Counter in PWM2 Mode The following is an example of output operation of the one-shot pulse waveform in PWM2 mode.
Section 13 Timer RC The following is an example of operation when TRCCNT starts counting by the TRGC input and the one-shot pulse waveform is output in PWM2 mode.
Section 13 Timer RC 13.4.4 Digital Filtering Function for Input Capture Inputs Input signals on the FTIOA to FIOD and TRGC pin can be input via the digital filters. The digital filter includes three latches connected in series and a matching detecting circuit. The latches operate on the sampling clock specified by bits DFCK1 and DFCK0 in TRCDF and stores an input signal on the FTIOA to FTIOD pins or TRGC pin.
Section 13 Timer RC 13.5 Operation Timing 13.5.1 TRCCNT Counting Timing Figure 13.23 shows the TRCCNT count timing when the internal clock source is selected. Figure 13.24 shows the timing when the external clock source is selected. φ Internal clock Rising edge TRCCNT input clock TRCCNT N N+1 N+2 Figure 13.23 Count Timing for Internal Clock Source φ External clock Rising edge Rising edge TRCCNT input clock TRCCNT N N+1 Figure 13.24 Count Timing for External Clock Source Rev. 1.50 Sep.
Section 13 Timer RC 13.5.2 Output Compare Output Timing The compare match signal is generated in the last state in which TRCCNT and GR match (when TRCCNT changes from the matching value to the next value). When the compare match signal is generated, the output value selected in TRCIOR is output on the compare match output pin (FTIOA, FTIOB, FTIOC, or FTIOD). When TRCCNT matches GR, the compare match signal is generated only after the next counter clock pulse is input. Figure 13.
Section 13 Timer RC 13.5.3 Input Capture Timing Input capture on the rising edge, falling edge, or both edges can be selected through settings in TRCIOR0 and TRCIOR1. Figure 13.26 shows the timing when the falling edge is selected. φ Input capture input Input capture signal N–1 TRCCNT N N+1 N+2 N GRA to GRD Figure 13.26 Input Capture Input Signal Timing 13.5.4 Timing of Counter Clearing by Compare Match Figure 13.27 shows the timing when the counter is cleared by compare match A.
Section 13 Timer RC 13.5.5 Buffer Operation Timing Figures 13.28 and 13.29 show the buffer operation timing. φ Compare match signal TRCCNT N GRC, GRD M N+1 GRA, GRB M Figure 13.28 Buffer Operation Timing (Compare Match) φ Input capture signal TRCCNT N GRA, GRB M GRC, GRD N+1 N N+1 M N Figure 13.29 Buffer Operation Timing (Input Capture) Rev. 1.50 Sep.
Section 13 Timer RC 13.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match If a general register (GRA, GRB, GRC, or GRD) is used as an output compare register, the corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when TRCCNT matches the general register. The compare match signal is generated in the last state in which the values match (when TRCCNT is updated from the matching count to the next count).
Section 13 Timer RC 13.5.7 Timing of IMFA to IMFD Setting at Input Capture If a general register (GRA, GRB, GRC, or GRD) is used as an input capture register, the corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when an input capture occurs. Figure 13.31 shows the timing of the IMFA to IMFD flag setting at input capture. φ Input capture signal TRCCNT GRA to GRD N N IMFA to IMFD IRRTRC Figure 13.31 Timing of IMFA to IMFD Flag Setting at Input Capture Rev. 1.50 Sep.
Section 13 Timer RC 13.5.8 Timing of Status Flag Clearing When the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is cleared. Figure 13.32 shows the status flag clearing timing. TRCSR write cycle T1 T2 T3 T4 φ TRCSR address Address Write signal IMFA to IMFD IRRTRC Figure 13.32 Timing of Status Flag Clearing by CPU Rev. 1.50 Sep.
Section 13 Timer RC 13.6 Usage Notes The following types of contention or operation can occur in timer RC operation. 1. The pulse width of the input clock signal and the input capture signal must be at least three system clock (φ) cycles when the CKS2 to CKS0 bits in TRCCR1 = B'0XX or B'10X, and at least three on-chip oscillator clock (φ40M) cycles for B'110; shorter pulses will not be detected correctly. 2. Writing to registers is performed in the T4 state of a TRCCNT write cycle.
Section 13 Timer RC Previous clock New clock Counter clock TRCCNT N+1 N N+2 N+3 Erroneous rising edge may occur depending on the timing of changing bits CKS2 to CKS0. In this case, TRCCNT counts up. Figure 13.34 Internal Clock Switching and TRCCNT Operation 5. The TOA to TOD bits in TRCCR1 decide the value of the FTIO pin, which is output until the first compare match occurs.
Section 13 Timer RC TRCCR1 has been set to H'06. Compare match B and compare match C are used. The FTIOB pin output 1, and is set to the toggle output or the 0 output on compare match B. When the TOC bit is cleared (the FTIOC signal is low) by execution of BCLR #2,@TRCCR1 and compare match B occurs at the same timing as shown below, writing H'02 to TRCCR has priority and the FTIOB signal is not driven low on compare match B; the FTIOB signal remains high.
Section 13 Timer RC Rev. 1.50 Sep.
Section 14 Timer RD Section 14 Timer RD This LSI has two units of 16-bit timers (timer RD_0 and timer RD_1), each of which has two channels. Table 14.1 lists the timer RD functions, table 14.2 lists the channel configuration of timer RD, and figure 14.1 is a block diagram of the entire timer RD. Block diagrams of channels 1 and 2 are shown in figures 14.2 and 14.3. Timer RD_1 has the same functions as timer RD_0.
Section 14 Timer RD • High-speed access by the internal 16-bit bus 16-bit TRDCNT and GR registers can be accessed in high speed by a 16-bit bus interface • Any initial timer output value can be set • Output of the timer is disabled by external trigger • Eleven interrupt sources Four compare match/input capture interrupts and an overflow interrupt are available for each channel. An underflow interrupt can be set for channel 1. Rev. 1.50 Sep.
Section 14 Timer RD Table 14.
Section 14 Timer RD Table 14.2 Channel Configuration of Timer RD Unit Channel Timer RD_0 0 Pin FTIOA0 FTIOB0 FTIOC0 FTIOD0 1 FTIOA1 FTIOB1 FTIOC1 FTIOD1 Timer RD_1 Shared by channels 0 and 1 TRDOI_0 2 FTIOA2 FTIOB2 FTIOC2 FTIOD2 3 FTIOA3 FTIOB3 FTIOC3 FTIOD3 Shared by channels 2 and 3 Rev. 1.50 Sep.
Section 14 Timer RD TRDOI ITMRD0 FTIOA0 FTIOB0 FTIOC0 FTIOD0 ITMRD1 Control logic FTIOA1 FTIOB1 FTIOC1 FTIOD1 φ, φ/2, φ/4, φ/8, φ/32, φ40M ADTRG Channel 0 timer Channel 1 timer TRDSTR TRDMDR TRDPMR TRDFCR TRDOER2 TRDOER1 TRDOCR Module data bus [Legend] TRDSTR: TRDMDR: TRDPMR: TRDFCR: TRDOER1: TRDOER2: TRDOCR: ADTRG: ITMRD0: ITMRD1: Timer RD start register (8 bits) Timer RD mode register (8 bits) Timer RD PWM mode register (8 bits) Timer RD function control register (8 bits) Timer RD output m
Section 14 Timer RD FTIOA0 φ, φ/2, φ/4, φ/8, φ/32, φ40M FTIOB0 FTIOC0 FTIOD0 Clock select Control logic ITMRD0 TRDDF_0 POCR_0 TRDIER_0 TRDSR_0 TRDIORC_0 TRDIORA_0 TRDCR_0 GRD_0 GRC_0 TRDOI_0 GRB_0 GRA_0 TRDCNT_0 Comparator Module data bus [Legend] TRDCNT_0: Timer RD counter_0 (16 bits) GRA_0, GRB_0, General registers A_0, B_0, C_0, and D_0 GRC_0, GRD_0: (input capture/output compare registers: 16 bits × 4) TRDCR_0: Timer RD control register_0 (8 bits) TRDIORA_0: Timer RD I/O control regis
Section 14 Timer RD FTIOA1 FTIOB1 FTIOC1 FTIOD1 Clock select Control logic ITMRD1 TRDDF_1 POCR_1 TRDIER_1 TRDSR_1 TRDIORC_1 TRDIORA_1 TRDCR_1 GRD_1 GRC_1 TRDOI_1 GRB_1 GRA_1 Comparator TRDCNT_1 φ, φ/2, φ/4, φ/8, φ/32, φ40M Module data bus [Legend] TRDCNT_1 Timer RD counter_1 (16 bits) GRA_1, GRB_1, General registers A_1, B_1, C_1, and D_1 GRC_1, GRD_1: (input capture/output compare registers: 16 bits × 4) TRDCR_1: Timer RD control register_1 (8 bits) TRDIORA_1: Timer RD I/O control regist
Section 14 Timer RD 14.2 Input/Output Pins Table 14.3 summarizes the timer RD pins. Table 14.
Section 14 Timer RD 14.3 Register Descriptions Timer RD has the following registers.
Section 14 Timer RD • • • • • Timer RD counter_1 (TRDCNT_1) General register A_1 (GRA_1) General register B_1 (GRB_1) General register C_1 (GRC_1) General register D_1 (GRD_1) 14.3.1 Timer RD Start Register (TRDSTR) TRDSTR selects the operation/stop for the TRDCNT counter. Use a MOV instruction to modify this register. Bit Bit Name Initial Value R/W Description 7 to 4 All 1 Reserved These bits are always read as 1, and cannot be modified.
Section 14 Timer RD Bit Bit Name Initial Value R/W Description 1 STR1 0 R/W Channel 1 Counter Start TRDCNT_1 stops counting when this bit is 0, while it performs counting when this bit is 1.
Section 14 Timer RD Figures 14.4 and 14.5 show examples of stopping operation of the counter in PWM3 mode, when the CCLR2 to CCLR0 bits in TRDCR are set to clear TRDCNT_0 on GRA_0 compare match. For details on PWM3 mode, refer to section 14.4.8, PWM3 Mode Operation. Counter cleared by GRA_0 compare match The value of TRDCNT H'FFFF GRA_0 GRA_1 GRB_0 GRB_1 H'0000 Time FTIOA0 FTIOB0 STR0 CSTPN0 Cleared to 0 by GRA_0 compare match Set to 1 by writing from the CPU Figure 14.
Section 14 Timer RD Figure 14.6 shows an example of starting and stopping operations of counters in PWM3 mode, when TRDCNT_0 is set to be cleared and stopped on GRA_0 compare match (CCLR2 to CCLR0 = 001, CSTPNT0 = 0) and TRDCNT_1 is used as a free-running counter. When TRDCNT_1 starts counting by setting the STR1 bit to 1 after TRDCNT_0 has started counting by setting the STR0 bit to 1, set 0 in the STR0 bit and 1 in the STR1 bit by using a MOV instruction.
Section 14 Timer RD 14.3.2 Timer RD Mode Register (TRDMDR) TRDMDR selects buffer operation settings and synchronized operation.
Section 14 Timer RD 14.3.3 Timer RD PWM Mode Register (TRDPMR) TRDPMR sets the pin to enter PWM mode. Bit Bit Name Initial Value R/W 7 1 Description Reserved This bit is always read as 1, and cannot be modified.
Section 14 Timer RD 14.3.4 Timer RD Function Control Register (TRDFCR) TFCR selects the settings and output levels for each operating mode. Bit Bit Name Initial Value R/W Description 7 PWM3 1 R/W PWM3 Mode Select Selects the PWM3 mode. 0: PWM3 mode is selected 1: PWM3 mode is not selected This bit is valid when both bits CMD1 and CMD0 are cleared to 0. When PWM3 mode is selected, TRDPMR, TRDIORA, and TRDIORC are invalid.
Section 14 Timer RD Bit Bit Name Initial Value R/W Description 2 OLS0 0 R/W Output Level Select 0 Selects the normal-phase output levels in reset synchronous PWM mode or complementary PWM mode. 0: Initial output is high and the active level is low. 1: Initial output is low and the active level is high. Figure 14.7 shows an example of outputs in reset synchronous PWM mode and complementary PWM mode when OLS1 = 0 and OLS0 = 0.
Section 14 Timer RD TRDCNT_0 TRDCNT_1 Normal phase Active level Counter phase Normal phase Active level Initial output Counter phase Initial output Active level Active level Reset synchronous PWM mode Note: Complementary PWM mode Write H'00 to TOCR to start initial outputs after stopping the counter. Figure 14.7 Example of Outputs in Reset Synchronous PWM Mode and Complementary PWM Mode 14.3.
Section 14 Timer RD Bit Bit Name Initial Value R/W Description 5 EB1 1 R/W Master Enable B1 0: FTIOB1 pin output is enabled according to the TRDPMR, TRDFCR, and TRDIORA_1 settings 1: FTIOB1 pin output is disabled regardless of the TRDPMR, TRDFCR, and TRDIORA_1 settings (FTIOB1 pin is operated as an I/O port).
Section 14 Timer RD 14.3.6 Timer RD Output Master Enable Register 2 (TRDOER2) TRDOER2 selects the output disabled mode for channels 0 and 1. Bit Bit Name Initial Value R/W Description 7 PTO 0 R/W Timer Output Disabled Mode 0: The corresponding bit in TRDOER1 is not set to 1 when the low level is input to the TRDOI pin 1: The corresponding bit in TRDOER1 is set to 1 when the low level is input to the TRDOI pin 6 to 0 All 1 Reserved These bits are always read as 1. 14.3.
Section 14 Timer RD Bit Bit Name Initial Value R/W Description 4 TOA1 0 R/W Output Level Select A1 0: 0 output at the FTIOA1 pin* 1: 1 output at the FTIOA1 pin* 3 TOD0 0 R/W Output Level Select D0 0: 0 output at the FTIOD0 pin* 1: 1 output at the FTIOD0 pin* 2 TOC0 0 R/W Output Level Select C0 0: 0 output at the FTIOC0 pin* 1: 1 output at the FTIOC0 pin* 1 TOB0 0 R/W Output Level Select B0 • In modes other than PWM3 mode 0: 0 output at the FTIOB0 pin* 1: 1 output at the FTIOB0 pin
Section 14 Timer RD 14.3.8 Timer RD Counter (TRDCNT) Timer RD has two TRDCNT counters (TRDCNT_0 and TRDCNT_1), one for each channel. The TRDCNT counters are 16-bit readable/writable registers that increment/decrement according to input clocks. Input clocks can be selected by bits TPSC2 to TPSC0 in TRDCR. TRDCNT_0 and TRDCNT_1 increment/decrement in complementary PWM mode, while they only increment in other modes.
Section 14 Timer RD 14.3.10 Timer RD Control Register (TRDCR) TRDCR selects a TRDCNT counter clock, an edge when an external clock is selected, and counter clearing sources. Timer RD has a total of two TRDCR registers, one for each channel.
Section 14 Timer RD Bit Bit Name Initial Value R/W Description 2 TPSC2 0 R/W Time Prescaler 2 to 0 1 TPSC1 0 R/W 000: Internal clock: count by φ* 0 TPSC0 0 R/W 001: Internal clock: count by φ/2 3 010: Internal clock: count by φ/4 011: Internal clock: count by φ/8 100: Internal clock: count by φ/32 101: External clock: count by FTIOA0 (TCLK) pin input 110: Internal clock: count by φ40M* 4 111: Reserved (setting prohibited) Notes: 1.
Section 14 Timer RD 14.3.11 Timer RD I/O Control Registers (TRDIORA and TRDIORC) TRDIOR control the general registers (GR). Timer RD has four TRDIOR registers (TRDIORA_0, TRDIORA_1, TRDIORC_0, and TRDIORC_1), two for each channel. In PWM mode, PWM3 mode, complementary PWM mode, and reset synchronous PWM mode, the settings of TRDIOR are invalid. • TRDIORA TRDIORA selects whether GRA or GRB is used as an output compare register or an input capture register.
Section 14 Timer RD Bit Bit Name Initial Value R/W Description 3 1 Reserved 0 should not be written to this bit. 2 IOA2 0 R/W I/O Control A2 Selects the GRA function.
Section 14 Timer RD • TRDIORC TRDIORC selects whether GRC or GRD is used as an output compare register or an input capture register. When an output compare register is selected, the output setting is selected. When an input capture register is selected, an input edge of an input capture signal is selected. TRDIORC also selects the function of the FTIOA to FTIOD pins. Bit Bit Name Initial Value R/W Description 7 IOD3 1 R/W I/O Control D3 Specifies GRD to be used as GR for the FTIOB or FTIOD pin.
Section 14 Timer RD Bit Bit Name Initial Value R/W Description 3 IOC3 1 R/W I/O Control C3 Specifies GRC to be used as GR for the FTIOA or FTIOC pin. 0: GRC is used as GR for the FTIOA pin 1: GRC is used as GR for the FTIOC pin 2 IOC2 0 R/W I/O Control C2 Selects the GRC function.
Section 14 Timer RD 14.3.12 Timer RD Status Register (TRDSR) TRDSR indicates generation of an overflow/underflow of TRDCNT and a compare match/input capture of GRA, GRB, GRC, and GRD. These flags are interrupt sources. If an interrupt is enabled by a corresponding bit in TRDIER, TRDSR requests an interrupt for the CPU. Timer RD has two TRDSR registers, one for each channel. Bit Bit Name Initial Value R/W Description 7, 6 All 1 Reserved These bits are always read as 1.
Section 14 Timer RD Bit Bit Name Initial Value R/W Description 2 IMFC 0 R/W Input Capture/Compare Match Flag C [Setting conditions] • When TRDCNT = GRC and GRC is functioning as output compare register • When TRDCNT = GRC while the FTIOC pin operates in PWM mode • When TRDCNT = GRC in PWM3 mode, reset synchronous PWM mode, or complementary PWM mode • When TRDCNT value is transferred to GRC by input capture signal and GRC is functioning as input capture register [Clearing condition] • 1 IM
Section 14 Timer RD Bit Bit Name Initial Value R/W Description 0 IMFA 0 R/W Input Capture/Compare Match Flag A [Setting conditions] • When TRDCNT = GRA and GRA is functioning as output compare register • When TRDCNT = GRA in PWM mode, PWM3 mode, reset synchronous PWM mode, or complementary PWM mode (in reset synchronous PWM mode, however, while TRDCNT_0 = GRA_1 and TRDCNT_0 = GRA_0) • When TRDCNT value is transferred to GRA by input capture signal and GRA is functioning as input capture regis
Section 14 Timer RD 14.3.13 Timer RD Interrupt Enable Register (TRDIER) TRDIER enables or disables interrupt requests for overflow or GR compare match/input capture. Timer RD has two TRDIER registers, one for each channel. Bit Bit Name Initial Value R/W Description 7 to 5 All 1 Reserved 4 OVIE 0 R/W Overflow Interrupt Enable These bits are always read as 1.
Section 14 Timer RD 14.3.14 PWM Mode Output Level Control Register (POCR) POCR control the active level in PWM mode. Timer RD has two POCR registers, one for each channel. Bit Bit Name Initial Value R/W Description 7 to 3 All 1 Reserved 2 POLD 0 R/W PWM Mode Output Level Control D These bits are always read as 1.
Section 14 Timer RD 14.3.15 Timer RD Digital Filtering Function Select Register (TRDDF) TRDDF enables or disables the digital filter for each of the FTIOA to FTIOD pins. The setting in this register is valid on the corresponding pin when the FTIOA to FTIOD inputs are enabled by TRDIORA and TRDIORC. Timer RD has two TRDDF registers, one for each channel. Bit Bit Name Initial Value R/W Description 7 DFCK1 0 R/W 6 DFCK0 0 R/W These bits select the clock to be used by the digital filter.
Section 14 Timer RD 14.3.16 Interface with CPU (1) 16-Bit Register TRDCNT and GR are 16-bit registers. Reading/writing in a 16-bit unit is enabled but disabled in an 8-bit unit since the data bus with the CPU is 16-bit width. These registers must always be accessed in a 16-bit unit. Figure 14.8 shows an example of accessing the 16-bit registers. Internal data bus H C P L Module data bus Bus interface U TRDCNTH TRDCNTL Figure 14.
Section 14 Timer RD 14.4 Operation Timer RD has the following operating modes.
Section 14 Timer RD • FTIOB0 pin Register Name TRDOER1 Bit Name EB0 CMD1, CMD0 Setting values 0 TRDFCR TRDPMR TRDIORA PWM3 PWMB0 IOB2 to IOB0 10, 11 X X XXX Complementary PWM mode waveform output 0 01 X X XXX Reset synchronous PWM mode waveform output 0 00 0 X XXX PWM3 mode waveform out 0 00 1 1 XXX PWM mode waveform out 0 00 1 0 001, 01X Timer mode waveform output (output compare function) 0 00 1 0 1XX Timer mode (input capture function) 1 Other than above
Section 14 Timer RD • FTIOC0 pin Register Name TRDOER1 Bit Name EC0 CMD1, CMD0 Setting values 0 TRDFCR TRDPMR TRDIORC PWM3 PWMC0 IOC2 to IOC0 10, 11 X X XXX Complementary PWM mode waveform output 0 01 X X XXX Reset synchronous PWM mode waveform output 0 00 1 1 XXX PWM mode waveform out 0 00 1 0 001, 01X Timer mode waveform output (output compare function) 0 00 1 0 1XX Timer mode (input capture function) 1 Other than above [Legend] X: Don't care. Rev. 1.50 Sep.
Section 14 Timer RD • FTIOD0 pin Register Name TRDOER1 Bit Name ED0 CMD1, CMD0 Setting values 0 TRDFCR TRDPMR TRDIORC PWM3 PWMD0 IOD2 to IOD0 10, 11 X X XXX Complementary PWM mode waveform output 0 01 X X XXX Reset synchronous PWM mode waveform output 0 00 1 1 XXX PWM mode waveform out 0 00 1 0 001, 01X Timer mode waveform output (output compare function) 0 00 1 0 1XX Timer mode (input capture function) 1 Other than above Function General I/O port [Legend] X: Do
Section 14 Timer RD • FTIOB1 pin Register Name TRDOER1 Bit Name EB1 CMD1, CMD0 Setting values 0 TRDFCR TRDPMR TRDIORA PWM3 PWMB1 IOB2 to IOB0 10, 11 X X XXX Complementary PWM mode waveform output 0 01 X X XXX Reset synchronous PWM mode waveform output 0 00 1 1 XXX PWM mode waveform out 0 00 1 0 001, 01X Timer mode waveform output (output compare function) 0 00 1 0 1XX Timer mode (input capture function) 1 Other than above Function General I/O port [Legend] X: Do
Section 14 Timer RD • FTIOD1 pin Register Name TRDOER1 Bit Name ED1 CMD1, CMD0 Setting values 0 TRDFCR TRDPMR TRDIORC PWM3 PWMD1 IOD2 to IOD0 10, 11 X X XXX Complementary PWM mode waveform output 0 01 X X XXX Reset synchronous PWM mode waveform output 0 00 1 1 XXX PWM mode waveform out 0 00 1 0 001, 01X Timer mode waveform output (output compare function) 0 00 1 0 1XX Timer mode (input capture function) 1 Other than above Function General I/O port [Legend] X: Do
Section 14 Timer RD 14.4.1 Counter Operation When one of bits STR0 and STR1 in TRDSTR is set to 1, the TRDCNT counter for the corresponding channel begins counting. TRDCNT can operate as a free-running counter, periodic counter, for example. Figure 14.10 shows an example of the counter operation setting procedure.
Section 14 Timer RD (1) Free-Running Count Operation and Periodic Count Operation Immediately after a reset, the TRDCNT counters for channels 0 and 1 are all designated as freerunning counters. When the relevant bit in TRDSTR is set to 1, the corresponding TRDCNT counter starts an increment operation as a free-running counter. When TRDCNT overflows, the OVF flag in TRDSR is set to 1. If the value of the OVIE bit in the corresponding TRDIER is 1 at this point, timer RD requests an interrupt.
Section 14 Timer RD Figure 14.12 illustrates periodic count operation. TRDCNT value Counter cleared by GR compare match GR value H'0000 Time STR IMF Figure 14.12 Periodic Counter Operation (2) TRDCNT Count Timing • Internal clock operation A system clock (φ), four types of clocks (φ/2, φ/4, φ/8, or φ/32) that are generated by dividing the system clock, or on-chip oscillator clock (φ40M) can be selected by bits TPSC2 to TPSC0 in TRDCR. Figure 14.13 illustrates this timing.
Section 14 Timer RD • External clock operation An external clock input pin (TCLK) can be selected by bits TPSC2 to TPSC0 in TRDCR, and a detection edge can be selected by bits CKEG1 and CKEG0. To detect an external clock, the rising edge, falling edge, or both edges can be selected. Figure 14.14 illustrates the detection timing of the rising and falling edges. φ External clock input pin TRDCNT input TRDCNT N-1 N N+1 Figure 14.14 Count Timing at External Clock Operation (Both Edges Detected) 14.4.
Section 14 Timer RD (1) Examples of Waveform Output Operation Figure 14.16 shows an example of 0 output/1 output. In this example, TRDCNT has been designated as a free-running counter, and settings have been made such that 0 is output by compare match A, and 1 is output by compare match B. When the set level and the pin level coincide, the pin level does not change. TRDCNT value H'FFFF Time H'0000 FTIOB No change No change FTIOA No change No change Figure 14.
Section 14 Timer RD TRDCNT value GRB GRA Time H'0000 FTIOB Toggle output FTIOA Toggle output Figure 14.17 Example of Toggle Output Operation (2) Output Compare Timing The compare match signal is generated in the last state in which TRDCNT and GR match (when TRDCNT changes from the matching value to the next value). When the compare match signal is generated, the output value selected in TRDIOR is output at the compare match output pin (FTIOA, FTIOB, FTIOC, or FTIOD).
Section 14 Timer RD 14.4.3 Input Capture Function The TRDCNT value can be transferred to GR on detection of the input edge of the input capture/output compare pin (FTIOA, FTIOB, FTIOC, or FTIOD). Rising edge, falling edge, or both edges can be selected as the detected edge. When the input capture function is used, the pulse width or period can be measured. Figure 14.19 shows an example of the input capture operation setting procedure.
Section 14 Timer RD (1) Example of Input Capture Operation Figure 14.20 shows an example of input capture operation. In this example, both rising and falling edges have been selected as the FTIOA pin input capture input edge, the falling edge has been selected as the FTIOB pin input capture input edge, and counter clearing by GRB input capture has been designated for TRDCNT.
Section 14 Timer RD (2) Input Capture Signal Timing Input capture on the rising edge, falling edge, or both edges can be selected through settings in TRDIOR. Figure 14.21 shows the timing when the rising edge is selected. φ Input capture input Input capture signal TRDCNT N GR N Figure 14.21 Input Capture Signal Timing Rev. 1.50 Sep.
Section 14 Timer RD 14.4.4 Synchronous Operation In synchronous operation, the values in a number of TRDCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TRDCNT counters can be cleared simultaneously by making the appropriate setting in TRDCR (synchronous clearing). Synchronous operation enables GR to be increased with respect to a single time base. Figure 14.22 shows an example of the synchronous operation setting procedure.
Section 14 Timer RD Figure 14.23 shows an example of synchronous operation. In this example, synchronous operation has been selected, FTIOB0 and FTIOB1 have been designated for PWM mode, GRA_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 counter clearing source. The same input clock has been set for the channel 0 and channel 1 counter input clocks. Two-phase PWM waveforms are output from pins FTIOB0 and FTIOB1.
Section 14 Timer RD Table 14.4 Initial Output Level of FTIOB0 Pin TOB0 POLB Initial Output Level 0 0 1 0 1 0 1 0 0 1 1 1 PWM mode Select counter clock [1] Select counter clearing source [2] Set PWM mode [3] Set initial output level [4] Select output level [5] Set GR [6] Enable waveform output Start counter operation [1] Select the counter clock with bits TPSC2 to TOSC0 in TRDCR.
Section 14 Timer RD Figure 14.25 shows an example of operation in PWM mode. The output signals go to 1 and TRDCNT is reset at compare match A, and the output signals go to 0 at compare match B, C, and D (TOB, TOC, and TOD = 0, POLB, POLC, and POLD = 0). TRDCNT value Counter cleared by GRA compare match GRA GRB GRC GRD H'0000 Time FTIOB FTIOC FTIOD Figure 14.25 Example of PWM Mode Operation (1) Rev. 1.50 Sep.
Section 14 Timer RD Figure 14.26 shows another example of operation in PWM mode. The output signals go to 0 and TRDCNT is reset at compare match A, and the output signals go to 1 at compare match B, C, and D (TOB, TOC, and TOD = 0, POLB, POLC, and POLD = 1). TRDCNT value Counter cleared by GRA compare match GRA GRB GRC GRD H'0000 Time FTIOB FTIOC FTIOD Figure 14.26 Example of PWM Mode Operation (2) Rev. 1.50 Sep.
Section 14 Timer RD Figures 14.27 (when TOB, TOC, and TOD = 0, POLB, POLC, and POLD = 0) and 14.28 (when TOB, TOC, and TOD = 0, POLB, POLC, and POLD = 1) show examples of the output of PWM waveforms with duty cycles of 0% and 100% in PWM mode. TRDCNT value GRB rewritten GRA GRB GRB rewritten Time H'0000 0% duty FTIOB TRDCNT value GRB rewritten When cycle register and duty register compare matches occur simultaneously, duty register compare match has priority.
Section 14 Timer RD TRDCNT value GRB rewritten GRA GRB rewritten GRB H'0000 Time FTIOB 0% duty TRDCNT value GRB rewritten When cycle register and duty register compare matches occur simultaneously, duty register compare match has priority. GRA GRB rewritten GRB rewritten GRB Time H'0000 100% duty FTIOB TRDCNT value GRB rewritten When cycle register and duty register compare matches occur simultaneously, duty register compare match has priority.
Section 14 Timer RD 14.4.6 Reset Synchronous PWM Mode Three normal- and counter-phase PWM waveforms are output by combining channels 0 and 1 that one of changing points of waveforms will be common. In reset synchronous PWM mode, the FTIOB0 to FTIOD0 and FTIOA1 to FTIOD1 pins become PWM-output pins automatically. TRDCNT_0 performs an increment operation. Tables 14.5 and 14.6 show the PWM-output pins used and the register settings, respectively. Figure 14.
Section 14 Timer RD [1] Clear bit STR0 in TRDSTR to 0 and stop the counter operation of TRDCNT_0. Set reset synchronous PWM mode after TRDCNT_0 stops. Reset synchronous PWM mode Stop counter operation [1] Select counter clock [2] Select counter clearing source [3] Set reset synchronous PWM mode [4] Set TRDCNT [5] Set GR [3] Use bits CCLR2 to CCLR0 in TRDCR to select counter clearing source GRA_0. [4] Select the reset synchronous PWM mode with bits CMD1 and CMD0 in TRDFCR.
Section 14 Timer RD Figures 14.30 and 14.31 show examples of operation in reset synchronous PWM mode. TCRDNT value Counter cleared by GRA compare match GRA_0 GRB_0 GRA_1 GRB_1 H'0000 Time FTIOB0 FTIOD0 FTIOA1 FTIOC1 FTIOB1 FTIOD1 FTIOC0 Figure 14.30 Example of Reset Synchronous PWM Mode Operation (OLS0 = OLS1 = 1) Rev. 1.50 Sep.
Section 14 Timer RD TRDCNT value Counter cleared by GRA compare match GRA_0 GRB_0 GRA_1 GRB_1 H'0000 Time FTIOB0 FTIOD0 FTIOA1 FTIOC1 FTIOB1 FTIOD1 FTIOC0 Figure 14.31 Example of Reset Synchronous PWM Mode Operation (OLS0 = OLS1 = 0) In reset synchronous PWM mode, TRDCNT_0 and TRDCNT_1 perform increment and independent operations, respectively. However, GRA_1 and GRB_1 are separated from TRDCNT_1.
Section 14 Timer RD 14.4.7 Complementary PWM Mode Three PWM waveforms for non-overlapped normal and counter phases are output by combining channels 0 and 1. In complementary PWM mode, the FTIOB0 to FTIOD0 and FTIOA1 to FTIOD1 pins become PWM-output pins automatically. TRDCNT_0 and TRDCNT_1 perform an increment or decrement operation. Tables 14.7 and 14.8 show the output pins and register settings in complementary PWM mode, respectively. Figure 14.
Section 14 Timer RD [1] Complementary PWM mode Stop counter operation [1] [2] Select counter clock [2] Set complementary PWM mode [3] Set TCNT [4] Set GR [5] [3] [4] Enable waveform output [6] Start counter operation [7] [5] [6] [7] Note: Clear bits STR0 and STR1 in TRDSTR to 0, and stop the counter operation of TRDCNT_0. Stop TRDCNT_0 and TRDCNT_1 and set complementary PWM mode.
Section 14 Timer RD (2) Examples of Complementary PWM Mode Operation Figure 14.34 shows an example of complementary PWM mode operation. In complementary PWM mode, TRDCNT_0 and TRDCNT_1 perform an increment or decrement operation. When TRDCNT_0 and GRA_0 are compared and their contents match, the counter is decremented, and when TRDCNT_1 underflows, the counter is incremented.
Section 14 Timer RD Figure 14.35 shows an example of PWM waveform output with 0% duty and 100% duty in complementary PWM mode (for one phase). In this figure, GRB_0 is set to a value equal to or greater than GRA_0 and H'0000. The waveform with a duty cycle of 0% and 100% can be output. When buffer operation is used together, the duty cycles can easily be changed, including the above settings, during operation. For details on buffer operation, refer to section 14.4.9, Buffer Operation.
Section 14 Timer RD In complementary PWM mode, when the counter switches from up-counter to down-counter or vice versa, TRDCNT_0 and TRDCNT_1 overshoots or undershoots, respectively. In this case, the conditions to set the IMFA flag in channel 0 and the UDF flag in channel 1 differ from usual settings. Also, the transfer conditions in buffer operation differ from usual settings. Such timings are shown in figures 14.36 and 14.37.
Section 14 Timer RD When the counter is incremented or decremented, the IMFA flag of channel 0 is set to 1, and when the register is underflowed, the UDF flag of channel 0 is set to 1. After buffer operation has been designated for GR, the value in the buffer registers is transferred to GR when the counter is incremented by compare match A0 or when TRDCNT_1 is underflowed.
Section 14 Timer RD 14.4.8 PWM3 Mode Operation In PWM3 mode, single-phase PWM waveforms can be output using TRDCNT_0. The waveform does not overlap its counter-phase waveform. When the PWM3 mode is selected, the FTIOA0 and FTIOB0 pins are automatically set to output pins for the PWM function using TRDCNT_0 regardless of the TRDPMR value. The waveform is output on a GRA_0, GRA_1, GRB_0, or GRB_1 compare match according to bits TOA0 and TOB0 in TRDOCR.
Section 14 Timer RD Table 14.
Section 14 Timer RD PWM mode 3 Select counter clock [1] Select counter clearing source [2] Set PWM mode 3 [3] [1] Select the counter clock with bits TPSC2 to TPSC0 in TRDCR. When an external clock is selected, select the external clock edge with bits CKEG1 and CKEG0 in TRDCR. [2] Use bits CCLR2 to CCLR0 in TRDCR to select counter clearing source GRA_0. [3] Select PWM mode 3 with bit PWM3 in TRDFCR. Set output level [4] [4] Set output levels with bits TOB0 and TOA0 in TRDOCR.
Section 14 Timer RD Figure 14.40 is an example when non-overlapped pulses are output on pins FTIOA0 and FTIOB0. In this example, TRDCNT_0 functions as a periodic counter which is cleared on compare match A0 (bits CCLR2 to CCLR0 in TRDCR_0 are set to B'001), and PWM3 mode is selected (bit PWM3 in TRDFCR is cleared to 0). The cycle of the pulse is arbitrary. TRDCNT value Counter cleared on GRA_0 compare match H'FFFF GRA_0 GRA_1 GRB_0 GRB_1 H'0000 Time FTIOA0 FTIOB0 Figure 14.
Section 14 Timer RD 14.4.9 Buffer Operation Buffer operation differs depending on whether GR has been designated for an input capture register or an output compare register, or in reset synchronous PWM mode or complementary PWM mode. Table 14.10 shows the register combinations used in buffer operation. Table 14.
Section 14 Timer RD (2) When GR is an Input Capture Register When an input capture occurs, the value in TRDCNT is transferred to GR and the value previously stored in the general register is transferred to the buffer register. This operation is illustrated in figure 14.42. Input capture signal General register Buffer register TRDCNT Figure 14.42 Input Capture Buffer Operation (3) PWM3 Mode When compare match A0 occurs, the value of the buffer register is transferred to GR.
Section 14 Timer RD (6) Example of Buffer Operation Setting Procedure Figure 14.43 shows an example of the buffer operation setting procedure. Buffer operation [1] Designate GR as an input capture register or output compare register by means of TRDIOR. Select GR function [1] [2] Designate GR for buffer operation with bits BFD1, BFC1, BFD0, or BFC0 in TRDMDR. Set buffer operation [2] [3] Set the STR bit in TRDSTR to 1 to start the count operation of TRDCNT.
Section 14 Timer RD (7) Examples of Buffer Operation Figure 14.44 shows an operation example in which GRA has been designated as an output compare register, and buffer operation has been designated for GRA and GRC. This is an example of TRDCNT operating as a periodic counter cleared by compare match B. Pins FTIOA and FTIOB are set for toggle output by compare match A and B.
Section 14 Timer RD φ TRDCNT n n+1 Compare match signal Buffer transfer signal GRC GRA N n N Figure 14.45 Example of Compare Match Timing for Buffer Operation Figure 14.46 shows an operation example in which GRA has been designated as an input capture register, and buffer operation has been designated for GRA and GRC. Counter clearing by input capture B has been set for TRDCNT, and falling edges have been selected as the FIOCB pin input capture input edge.
Section 14 Timer RD TRDCNT value Counter is cleared by the input capture B H'0180 H'0160 H'0005 H'0000 Time FTIOB FTIOA GRA H'0005 H'0160 GRC H'0005 GRB H'0160 H'0180 Input capture A Figure 14.46 Example of Buffer Operation (2) (Buffer Operation for Input Capture Register) φ FTIO pin Input capture signal TRDCNT n GRA M n n N GRC m M M n n+1 N N+1 Figure 14.47 Input Capture Timing of Buffer Operation Rev. 1.50 Sep.
Section 14 Timer RD Figures 14.48 and 14.49 show the operation examples when buffer operation has been designated for GRB_0 and GRD_0 in complementary PWM mode. These are examples when a PWM waveform of 0% duty is created by using the buffer operation and performing GRD_0 ≥ GRA_0. Data is transferred from GRD_0 to GRB_0 according to the settings of CMD0 and CMD1 when TRDCNT_0 and GRA_0 are compared and their contents match or when TRDCNT_1 underflows.
Section 14 Timer RD TRDCNT values GRB_0 (When restored, data will be transferred to the saved location regardless of the CMD1 and CMD0 values) TRDCNT_0 GRA_0 TRDCNT_1 H'0999 H'0000 Time GRB_0 GRD_0 H'0999 GRB_0 H'0999 H'0000 H'0999 H'0000 H'0999 FTIOC0 FTIOD0 Figure 14.49 Buffer Operation (4) (Buffer Operation in Complementary PWM Mode CMD1 =1, CMD0 = 0) Rev. 1.50 Sep.
Section 14 Timer RD 14.4.10 Timer RD Output Timing The outputs of channels 0 and 1 can be disabled or inverted by the settings of TRDOER1 and TRDOCR and the external level. (1) Output Disable/Enable Timing of Timer RD by TRDOER1 Setting the master enable bit in TRDOER1 to 1 disables the output of timer RD. By setting the PCR and PDR of the corresponding I/O port beforehand, any value can be output. Figure 14.50 shows the timing to enable or disable the output of timer RD by TRDOER1.
Section 14 Timer RD (3) Output Inverse Timing by TRDFCR The output level can be inverted by inverting the OLS1 and OLS0 bits in TRDFCR in reset synchronous PWM mode or complementary PWM mode. Figure 14.52 shows the timing. T1 T2 T3 T4 φ Address bus TRDOER1 address TRDFCR Timer RD output pin Inverted Figure 14.
Section 14 Timer RD 14.4.11 Digital Filtering Function for Input Capture Inputs Input signals on the FTIOA to FTIOD pins can be input via the digital filters. The digital filter includes three latches connected in series and a matching detecting circuit. The latches operate on the sampling clock specified by bits DFCK1 and DFCK0 in TRDDF and stores an input signal on the FTIOA to FTIOD pins. When outputs of the three latches match, the matching detecting circuit outputs the signal level of the input.
Section 14 Timer RD 14.4.12 Function of Changing Output Pins for GR With the settings of bits IOC3 and IOD3 in TRDIORC, pins for outputs of compare match signals for GRC and GRD can be changed from the FTIOC and FTIOD pins to the FTIOA and FTIOB pins. This means that the compare match A signal ORed with the compare match C signal can be output on the FTIOA pin. The compare match B ORed with the compare match D signal can be output on the FTIOB pin. Figure 14.55 is a block diagram of this function.
Section 14 Timer RD Figure 14.56 is an example when non-overlapped pulses are output on pins FTIOA0 and FTIOB0.
Section 14 Timer RD 14.5 Interrupt Sources There are three kinds of timer RD interrupt sources; input capture/compare match, overflow, and underflow. An interrupt is requested when the corresponding interrupt request flag is set to 1 while the corresponding interrupt enable bit is set to 1. 14.5.1 (1) Status Flag Set Timing IMF Flag Set Timing The IMF flag is set to 1 by the compare match signal that is generated when the GR matches with the TRDCNT.
Section 14 Timer RD (2) IMF Flag Set Timing at Input Capture When an input capture signal is generated, the IMF flag is set to 1 and the value of TRDCNT is simultaneously transferred to corresponding GR. Figure 14.59 shows the timing. φ Input capture signal IMF TRDCNT N GR N ITMRD Figure 14.59 IMF Flag Set Timing at Input Capture (3) Overflow Flag (OVF) Set Timing The overflow flag is set to 1 when the TRDCNT overflows. Figure 14.60 shows the timing.
Section 14 Timer RD 14.5.2 Status Flag Clearing Timing The status flag can be cleared by writing 0 after reading 1 from the CPU. Figure 14.61 shows the timing in this case. φ TRDSR address Address WTRDSR (internal write signal) IMF, OVF ITMRD Figure 14.61 Status Flag Clearing Timing 14.
Section 14 Timer RD (2) Conflict between TRDCNT Write and Clear Operations If a counter clear signal is generated in the T4 state of a TRDCNT write cycle, TRDCNT clearing has priority and the TRDCNT write is not performed. Figure 14.62 shows the timing in this case. T1 TRDCNT write cycle T3 T2 T4 φ Address bus TRDCNT address WTRDCNT (internal write signal) Counter clear signal H'0000 N TRDCNT Clearing has priority. Figure 14.
Section 14 Timer RD (4) Conflict between GR Write and Compare Match If a compare match occurs in the T4 state of a GR write cycle, GR write has priority and the compare match signal is disabled. Figure 14.64 shows the timing in this case. T1 GR write cycle T3 T2 T4 φ Address bus GR address WTRDCNT (internal write signal) TRDCNT N GR N N+1 M GR write data Disabled Compare match signal Figure 14.64 Conflict between GR Write and Compare Match Rev. 1.50 Sep.
Section 14 Timer RD (5) Conflict between TRDCNT Write and Overflow/Underflow If overflow/underflow occurs in the T4 state of a TRDCNT write cycle, TRDCNT write has priority without an increment operation. At this time, the OVF flag is set to 1. Figure 14.65 shows the timing in this case. T1 TRDCNT write cycle T3 T2 T4 φ Address bus TRDCNT address WTRDCNT (internal write signal) TRDCNT input clock Overflow signal H'FFFF TRDCNT M TRDCNT write data OVF Figure 14.
Section 14 Timer RD (6) Conflict between GR Read and Input Capture If an input capture signal is generated in the T4 state of a GR read cycle, the data that is read will be transferred before input capture transfer. Figure 14.66 shows the timing in this case. T1 GR read cycle T2 T3 T4 φ Address bus GR address Internal read signal Input capture signal GR M X Internal data bus X Figure 14.
Section 14 Timer RD (8) Conflict between GR Write and Input Capture If an input capture signal is generated in the T4 state of a GR write cycle, the input capture operation has priority and the write to GR is not performed. Figure 14.68 shows the timing in this case. T1 GR write cycle T2 T3 T4 φ GR address Address bus WGR (internal write signal) Input capture signal TRDCNT N GR M GR write data Figure 14.
Section 14 Timer RD (10) Note on Writing to the TOA0 to TOD0 Bits and the TOA1 to TOD1 Bits in TRDOCR The TOA0 to TOD0 bits and the TOA1 to TOD1 bits in TRDOCR decide the value of the FTIO pin, which is output until the first compare match occurs. Once a compare match occurs and this compare match changes the values of FTIOA0 to FTIOD0 and FTIOA1 to FTIOD1 output, the values of the FTIOA0 to FTIOD0 and FTIOA1 to FTIOD1 pin output and the values read from the TOA0 to TOD0 and TOA1 to TOD1 bits may differ.
Section 14 Timer RD TRDOCR has been set to H'06. Compare match B0 and compare match C0 are used. The FTIOB0 pin is in the 1 output state, and is set to the toggle output or the 0 output by compare match B0. When BCLR#2, @TRDOCR is executed to clear the TOC0 bit (the FTIOC0 signal is low) and compare match B0 occurs at the same timing as shown below, the H'02 writing to TRDOCR has priority and compare match B0 does not drive the FTIOB0 signal low; the FTIOB0 signal remains high.
Section 15 Watchdog Timer Section 15 Watchdog Timer The watchdog timer is an 8-bit timer that can generate an internal reset signal for this LSI if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. WDT dedicated internal oscillator φ CLK TCSRWD PSS TCWD Internal data bus The block diagram of the watchdog timer is shown in figure 15.1.
Section 15 Watchdog Timer 15.2 Register Descriptions The watchdog timer has the following registers. • Timer control/status register WD (TCSRWD) • Timer counter WD (TCWD) • Timer mode register WD (TMWD) 15.2.1 Timer Control/Status Register WD (TCSRWD) TCSRWD performs the TCSRWD and TCWD write control. TCSRWD also controls the watchdog timer operation and indicates the operating state. TCSRWD must be rewritten by using the MOV instruction.
Section 15 Watchdog Timer Bit Bit Name Initial Value R/W Description 2 WDON 1 R/W Watchdog Timer On TCWD starts counting up when the WDON bit is set to 1 and halts when the WDON bit is cleared to 0. The watchdog timer is enabled in the initial state. When the watchdog timer is not used, clear the WDON bit to 0.
Section 15 Watchdog Timer 15.2.2 Timer Counter WD (TCWD) TCWD is an 8-bit readable/writable up-counter. When TCWD overflows from H'FF to H'00, the internal reset signal is generated and the WRST bit in TCSRWD is set to 1. TCWD is initialized to H'00. 15.2.3 Timer Mode Register WD (TMWD) TMWD selects the input clock. Bit Bit Name Initial Value R/W Description 7 to 4 All 1 Reserved These bits are always read as 1.
Section 15 Watchdog Timer 15.3 Operation The watchdog timer is provided with an 8-bit counter. After the reset state is released, TCWD starts counting up. When the TCWD count value overflows H'FF, an internal reset signal is generated. The internal reset signal is output for a period of 256 φRC clock cycles. As TCWD is a writable counter, it starts counting from the value set in TCWD. An overflow period in the range of 1 to 256 input clock cycles can therefore be set, according to the TCWD set value.
Section 15 Watchdog Timer Rev. 1.50 Sep.
Section 16 14-Bit PWM Section 16 14-Bit PWM The 14-bit PWM is a pulse division type PWM that can be used for electronic tuner control, etc. Figure 16.1 shows a block diagram of the 14-bit PWM. 16.
Section 16 14-Bit PWM 16.3 Register Descriptions The 14-bit PWM has the following registers. • PWM control register (PWCR) • PWM data register U (PWDRU) • PWM data register L (PWDRL) 16.3.1 PWM Control Register (PWCR) PWCR selects the conversion period. Bit Bit Name Initial Value R/W Description 7 1 Reserved 6 1 5 1 These bits are always read as 1, and cannot be modified.
Section 16 14-Bit PWM 16.3.2 PWM Data Registers U, L (PWDRU, PWDRL) PWDRU and PWDRL indicate high level width in one PWM waveform cycle. PWDRU and PWDRL are 14-bit write-only registers, with the upper 6 bits assigned to PWDRU and the lower 8 bits to PWDRL. When read, all bits are always read as 1. Both PWDRU and PWDRL are accessible only in bytes. Note that the operation is not guaranteed if word access is performed.
Section 16 14-Bit PWM Conversion period t f1 t H1 t f2 t H2 t f63 t H3 t H63 t f64 t H64 T H = t H1 + t H2 + t H3 + ... + t H64 t f1 = t f2 = t f3 = ... = t f64 Figure 16.2 Waveform Output by 14-Bit PWM Rev. 1.50 Sep.
Section 17 Serial Communication Interface 3 (SCI3) Section 17 Serial Communication Interface 3 (SCI3) This LSI includes a serial communication interface 3 (SCI3), which has independent three channels. The SCI3 can handle both asynchronous and clock synchronous serial communication.
Section 17 Serial Communication Interface 3 (SCI3) Clock synchronous mode: • Data length: 8 bits • Receive error detection: Overrun errors Table 17.
Section 17 Serial Communication Interface 3 (SCI3) Note: 1. In addition to basic functions common in SCI3 and SCI3_2, SCI3_3 has the serial mode control register (SMCR). SMCR controls noise canceling on the RXD_3 input signal, PH2/TXD_3 pin function, and SCI3_3 module standby function. 2. The channel 1 of the SCI3 is used in on-board programming mode by boot mode.
Section 17 Serial Communication Interface 3 (SCI3) SCK3 External clock Internal clock (φ/64, φ/16, φ/4, φ) Baud rate generator BRR BRC SMR Transmit/receive control circuit SCR3 SSR Internal data bus Clock TXD RXD TSR TDR RSR RDR Interrupt request (TEI, TXI, RXI, ERI) [Legend] RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register SCR3: Serial control register 3 SSR: Serial status register BRR: Bit rate registe
Section 17 Serial Communication Interface 3 (SCI3) 17.3 Register Descriptions The SCI3 has the following registers for each channel. • • • • • • • • • Receive shift register (RSR) Receive data register (RDR) Transmit shift register (TSR) Transmit data register (TDR) Serial mode register (SMR) Serial control register 3 (SCR3) Serial status register (SSR) Bit rate register (BRR) Serial mode control register 3 (SMCR3) 17.3.
Section 17 Serial Communication Interface 3 (SCI3) 17.3.4 Transmit Data Register (TDR) TDR is an 8-bit register that stores data for transmission. When the SCI3 detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission. The doublebuffered structure of TDR and TSR enables continuous serial transmission.
Section 17 Serial Communication Interface 3 (SCI3) Bit Bit Name Initial Value R/W Description 2 MP 0 R/W Multiprocessor Mode When this bit is set to 1, the multiprocessor communication function is enabled. The PE bit and PM bit settings are invalid in multiprocessor mode. In clock synchronous mode, clear this bit to 0. 1 CKS1 0 R/W Clock Select 0 and 1 0 CKS0 0 R/W These bits select the clock source for the baud rate generator.
Section 17 Serial Communication Interface 3 (SCI3) Bit Bit Name Initial Value R/W Description 3 MPIE 0 R/W Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and OER status flags in SSR is disabled. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed.
Section 17 Serial Communication Interface 3 (SCI3) 17.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI3 and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, OER, PER, and FER; they can only be cleared. Bit Bit Name Initial Value R/W Description 7 TDRE 1 R/W Transmit Data Register Empty Indicates whether TDR contains transmit data.
Section 17 Serial Communication Interface 3 (SCI3) Bit Bit Name Initial Value R/W Description 4 FER 0 R/W Framing Error [Setting condition] • When a framing error occurs in reception [Clearing condition] • 3 PER 0 R/W When 0 is written to FER after reading FER = 1 Parity Error [Setting condition] • When a parity error is detected during reception [Clearing condition] • 2 TEND 1 R When 0 is written to PER after reading PER = 1 Transmit End [Setting conditions] • When the TE bit in SC
Section 17 Serial Communication Interface 3 (SCI3) 17.3.8 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. The initial value of BRR is H'FF. Table 17.3 shows the relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0 of SMR in asynchronous mode. Table 17.4 shows the maximum bit rate for each frequency in asynchronous mode. The values shown in both tables 17.3 and 17.4 are values in active (highspeed) mode. Table 17.
Section 17 Serial Communication Interface 3 (SCI3) Table 17.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) Operating Frequency φ (MHz) 4 Bit Rate (bit/s) n 110 150 4.9152 N Error (%) n 2 70 0.03 1 207 0.16 300 1 103 600 0 1200 0 2400 5 N Error (%) n 2 86 0.31 1 255 0.00 0.16 1 127 207 0.16 0 103 0.16 0 0 51 0.16 4800 0 25 9600 0 12 19200 0 6 –6.99 0 31250 0 3 0.00 0 38400 0 2 8.
Section 17 Serial Communication Interface 3 (SCI3) Table 17.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) Operating Frequency φ (MHz) 10 12 12.888 Bit Rate (bit/s) n N Error (%) 110 2 177 –0.25 2 212 0.03 2 217 0.08 2 248 –0.17 150 2 129 0.16 2 155 0.16 2 159 0.00 2 181 0.16 300 2 64 0.16 2 77 0.16 2 79 0.00 2 90 0.16 600 1 129 0.16 1 155 0.16 1 159 0.00 1 181 0.16 1200 1 64 0.16 1 77 0.16 1 79 0.00 1 90 0.
Section 17 Serial Communication Interface 3 (SCI3) Table 17.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) φ (MHz) Maximum Bit Rate (bit/s) n N φ (MHz) Maximum Bit Rate (bit/s) n N 4 125000 0 0 12 375000 0 0 4.9152 153600 0 0 12.288 384000 0 0 5 156250 0 0 14 437500 0 0 6 187500 0 0 14.7456 460800 0 0 6.144 192000 0 0 16 500000 0 0 8 250000 0 0 17.2032 537600 0 0 9.
Section 17 Serial Communication Interface 3 (SCI3) 17.4 Operation in Asynchronous Mode Figure 17.2 shows the general format for asynchronous serial communication. One character (or frame) consists of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and finally stop bits (high level). Inside the SCI3, the transmitter and receiver are independent units, enabling full-duplex.
Section 17 Serial Communication Interface 3 (SCI3) 17.4.2 SCI3 Initialization Before transmitting and receiving data, you should first clear the TE and RE bits in SCR3 to 0, then initialize the SCI3 as described below. When the operating mode, or transfer format, is changed for example, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1.
Section 17 Serial Communication Interface 3 (SCI3) 17.4.3 Data Transmission Figure 17.5 shows an example of operation for transmission in asynchronous mode. In transmission, the SCI3 operates as described below. 1. The SCI3 monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI3 recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI3 sets the TDRE flag to 1 and starts transmission.
Section 17 Serial Communication Interface 3 (SCI3) Start transmission [1] [1] Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automaticaly cleared to 0. [2] To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR. When data is written to TDR, the TDRE flag is automaticaly cleared to 0.
Section 17 Serial Communication Interface 3 (SCI3) 17.4.4 Serial Data Reception Figure 17.7 shows an example of operation for reception in asynchronous mode. In serial reception, the SCI3 operates as described below. 1. The SCI3 monitors the communication line. If a start bit is detected, the SCI3 performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit. 2.
Section 17 Serial Communication Interface 3 (SCI3) Table 17.6 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 17.8 shows a sample flow chart for serial data reception. Table 17.
Section 17 Serial Communication Interface 3 (SCI3) Start reception Read OER, PER, and FER flags in SSR OER+PER+FER = 1 No [1] Yes [4] [1] Read the OER, PER, and FER flags in SSR to identify the error. If a receive error occurs, performs the appropriate error processing. [2] Read SSR and check that RDRF = 1, then read the receive data in RDR. The RDRF flag is cleared automatically.
Section 17 Serial Communication Interface 3 (SCI3) [4] Error processing No OER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No Framing error processing No PER = 1 Yes Parity error processing (A) Clear OER, PER, and FER flags in SSR to 0 Figure 17.8 Sample Serial Reception Data Flowchart (Asynchronous Mode) (2) Rev. 1.50 Sep.
Section 17 Serial Communication Interface 3 (SCI3) 17.5 Operation in Clock Synchronous Mode Figure 17.9 shows the general format for clock synchronous communication. In clock synchronous mode, data is transmitted or received synchronous with clock pulses. A single character in the transmit data consists of the 8-bit data starting from the LSB. In clock synchronous serial communication, data on the transmission line is output from one falling edge of the synchronization clock to the next.
Section 17 Serial Communication Interface 3 (SCI3) 17.5.3 Serial Data Transmission Figure 17.10 shows an example of SCI3 operation for transmission in clock synchronous mode. In serial transmission, the SCI3 operates as described below. 1. The SCI3 monitors the TDRE flag in SSR, and if the flag is 0, the SCI3 recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. The SCI3 sets the TDRE flag to 1 and starts transmission.
Section 17 Serial Communication Interface 3 (SCI3) Start transmission [1] [1] Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0 and clocks are output to start the data transmission. [2] To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0.
Section 17 Serial Communication Interface 3 (SCI3) 17.5.4 Serial Data Reception (Clock Synchronous Mode) Figure 17.12 shows an example of SCI3 operation for reception in clock synchronous mode. In serial reception, the SCI3 operates as described below. 1. The SCI3 performs internal initialization synchronous with a synchronization clock input or output, starts receiving data. 2. The SCI3 stores the receive data in RSR. 3.
Section 17 Serial Communication Interface 3 (SCI3) Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 17.13 shows a sample flow chart for serial data reception. Start reception [1] Read the OER flag in SSR to determine if there is an error. If an overrun error has occurred, execute overrun error processing. [2] Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR.
Section 17 Serial Communication Interface 3 (SCI3) 17.5.5 Simultaneous Serial Data Transmission and Reception Figure 17.14 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations. To switch from transmit mode to simultaneous transmit and receive mode, after checking that the SCI3 has finished transmission and the TDRE and TEND flags are set to 1, clear TE to 0.
Section 17 Serial Communication Interface 3 (SCI3) 17.6 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer between a number of processors sharing communication lines by asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is performed, each receiving station is addressed by a unique ID code.
Section 17 Serial Communication Interface 3 (SCI3) Transmitting station Serial transmission line Receiving station A Receiving station B Receiving station C Receiving station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial data H'01 H'AA (MPB = 1) ID transmission cycle = receiving station specification (MPB = 0) Data transmission cycle = Data transmission to receiving station specified by ID [Legend] MPB: Multiprocessor bit Figure 17.
Section 17 Serial Communication Interface 3 (SCI3) 17.6.1 Multiprocessor Serial Data Transmission Figure 17.16 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI3 operations are the same as those in asynchronous mode.
Section 17 Serial Communication Interface 3 (SCI3) 17.6.2 Multiprocessor Serial Data Reception Figure 17.17 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR3 is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI3 operations are the same as those in asynchronous mode. Figure 17.
Section 17 Serial Communication Interface 3 (SCI3) [5] Error processing No OER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No [A] Framing error processing Clear OER, and FER flags in SSR to 0 Figure 17.17 Sample Multiprocessor Serial Reception Flowchart (2) Rev. 1.50 Sep.
Section 17 Serial Communication Interface 3 (SCI3) Start bit Serial data 1 0 Receive data (ID1) D0 D1 D7 MPB 1 Stop Start bit bit 1 0 Receive data (Data1) D0 1 frame D1 D7 MPB Stop bit Mark state (idle state) 0 1 1 1 frame MPIE RDRF RDR value ID1 LSI operation User processing RXI interrupt request is not generated, and RDR retains its state RDRF flag cleared to 0 RXI interrupt request MPIE cleared to 0 RDR data read When data is not this station's ID, MPIE is set to 1 again (a)
Section 17 Serial Communication Interface 3 (SCI3) 17.7 Interrupt Requests SCI3 creates the following six interrupt requests: transmission end, transmit data empty, receive data full, and receive errors (overrun error, framing error, and parity error). Table 17.7 shows the interrupt sources. Table 17.
Section 17 Serial Communication Interface 3 (SCI3) 17.8 Usage Notes 17.8.1 Break Detection and Processing When framing error detection is performed, a break can be detected by reading the RXD pin value directly. In a break, the input from the RXD pin becomes all 0s, setting the FER flag, and possibly the PER flag. Note that as the SCI3 continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. 17.8.
Section 17 Serial Communication Interface 3 (SCI3) 17.8.4 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI3 operates on a basic clock with a frequency of 16 times the transfer rate. In reception, the SCI3 samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the basic clock as shown in figure 17.19.
Section 17 Serial Communication Interface 3 (SCI3) Rev. 1.50 Sep.
2 Section 18 I C Bus Interface 2 (IIC2) Section 18 I2C Bus Interface 2 (IIC2) The I2C bus interface 2 conforms to and provides a subset of the Philips I2C bus (inter-IC bus) interface functions. The register configuration that controls the I2C bus differs partly from the Philips configuration, however. Figure 18.1 shows a block diagram of the I2C bus interface 2. Figure 18.2 shows an example of I/O pin connections to external circuits. 18.
2 Section 18 I C Bus Interface 2 (IIC2) Transfer clock generation circuit Transmission/ reception control circuit Output control SCL ICCR1 ICCR2 ICMR Internal data bus Noise canceler ICDRT Output control SDA ICDRS SAR Address comparator Noise canceler ICDRR Bus state decision circuit Arbitration decision circuit ICSR ICIER [Legend] ICCR1: I2C bus control register 1 ICCR2: I2C bus control register 2 ICMR: I2C bus mode register ICSR: I2C bus status register ICIER: I2C bus interrupt enable reg
2 Section 18 I C Bus Interface 2 (IIC2) Vcc SCL in Vcc SCL SCL SDA SDA SDA in SCL SDA SDA out SCL in (Master) SCL out SCL SDA SCL out SCL in SCL out SDA in SDA in SDA out SDA out (Slave 1) (Slave 2) Figure 18.2 External Circuit Connections of I/O Pins 18.2 Input/Output Pins Table 18.1 summarizes the input/output pins used by the I2C bus interface 2. Table 18.
2 Section 18 I C Bus Interface 2 (IIC2) 18.3 Register Descriptions The I2C bus interface 2 has the following registers. • • • • • • • • • I2C bus control register 1 (ICCR1) I2C bus control register 2 (ICCR2) I2C bus mode register (ICMR) I2C bus interrupt enable register (ICIER) I2C bus status register (ICSR) I2C bus slave address register (SAR) I2C bus transmit data register (ICDRT) I2C bus receive data register (ICDRR) I2C bus shift register (ICDRS) 18.3.
2 Section 18 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 5 MST 0 R/W Master/Slave Select 4 TRS 0 R/W Transmit/Receive Select 2 In master mode with the I C bus format, when arbitration is lost, MST and TRS are both reset by hardware, causing a transition to slave receive mode. Modification of the TRS bit should be made between transfer frames.
2 Section 18 I C Bus Interface 2 (IIC2) Table 18.2 Transfer Rate Bit 3 Bit 2 Bit 1 Bit 0 CKS3 CKS2 CKS1 CKS0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Transfer Rate Clock φ=5 MHz φ=8 MHz 0 φ/28 179 kHz 286 kHz 357 kHz 571 kHz 714 kHz 1 φ/40 125 kHz 200 kHz 250 kHz 400 kHz 500 kHz 0 φ/48 104 kHz 167 kHz 208 kHz 333 kHz 417 kHz 1 φ/64 78.1 kHz 125 kHz 156 kHz 250 kHz 313 kHz 0 φ/80 62.5 kHz 100 kHz 125 kHz 200 kHz 250 kHz 1 φ/100 50.0 kHz 80.
2 Section 18 I C Bus Interface 2 (IIC2) 18.3.2 I2C Bus Control Register 2 (ICCR2) ICCR2 issues start/stop conditions, manipulates the SDA pin, monitors the SCL pin, and controls reset in the control part of the I2C bus interface 2. Bit Bit Name Initial Value R/W Description 7 BBSY 0 R/W Bus Busy 2 This bit enables to confirm whether the I C bus is occupied or released and to issue start/stop conditions in master mode. With the clocked synchronous serial 2 format, this bit has no meaning.
2 Section 18 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 4 SDAOP 1 R/W SDAO Write Protect This bit controls change of output level of the SDA pin by modifying the SDAO bit. To change the output level, clear SDAO and SDAOP to 0 or set SDAO to 1 and clear SDAOP to 0 by the MOV instruction. This bit is always read as 1. 3 SCLO 1 R This bit monitors SCL output level. When SCLO is 1, SCL pin outputs high. When SCLO is 0, SCL pin outputs low.
2 Section 18 I C Bus Interface 2 (IIC2) 18.3.3 I2C Bus Mode Register (ICMR) ICMR selects whether the MSB or LSB is transferred first, performs master mode wait control, and selects the transfer bit count. Bit Bit Name Initial Value R/W 7 MLS 0 R/W Description MSB-First/LSB-First Select 0: MSB-first 1: LSB-first Set this bit to 0 when the I2C bus format is used.
2 Section 18 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 2 BC2 0 R/W Bit Counter 2 to 0 1 BC1 0 R/W 0 BC0 0 R/W These bits specify the number of bits to be transferred next. When read, the remaining number of transfer bits 2 is indicated. With the I C bus format, the data is transferred with one addition acknowledge bit. Bit BC2 to BC0 settings should be made during an interval between transfer frames.
2 Section 18 I C Bus Interface 2 (IIC2) 18.3.4 I2C Bus Interrupt Enable Register (ICIER) ICIER enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be transferred, and confirms acknowledge bits to be received. Bit Bit Name Initial Value R/W Description 7 TIE 0 R/W Transmit Interrupt Enable When the TDRE bit in ICSR is set to 1, this bit enables or disables the transmit data empty interrupt (TXI). 0: Transmit data empty interrupt request (TXI) is disabled.
2 Section 18 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 4 NAKIE 0 R/W NACK Receive Interrupt Enable This bit enables or disables the NACK receive interrupt request (NAKI) and the overrun error (setting of the OVE bit in ICSR) interrupt request (ERI) with the clocked synchronous format, when the NACKF and AL bits in ICSR are set to 1. NAKI can be canceled by clearing the NACKF, OVE, or NAKIE bit to 0. 0: NACK receive interrupt request (NAKI) is disabled.
2 Section 18 I C Bus Interface 2 (IIC2) 18.3.5 I2C Bus Status Register (ICSR) ICSR performs confirmation of interrupt request flags and status.
2 Section 18 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 4 NACKF 0 R/W No Acknowledge Detection Flag [Setting condition] • When no acknowledge is detected from the receive device in transmission while the ACKE bit in ICIER is 1 [Clearing condition] • 3 STOP 0 R/W When 0 is written in NACKF after reading NACKF = 1 Stop Condition Detection Flag [Setting condition] • When a stop condition is detected after frame transfer [Clearing condition] • 2 AL/OVE 0 R/W Wh
2 Section 18 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 1 AAS 0 R/W Slave Address Recognition Flag In slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR. [Setting conditions] • When the slave address is detected in slave receive mode • When the general call address is detected in slave receive mode.
2 Section 18 I C Bus Interface 2 (IIC2) 18.3.7 I2C Bus Transmit Data Register (ICDRT) ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT to ICDRS and starts transferring data. If the next transfer data is written to ICDRT during transferring data of ICDRS, continuous transfer is possible.
2 Section 18 I C Bus Interface 2 (IIC2) 18.4 Operation The I2C bus interface can communicate either in I2C bus mode or clocked synchronous serial mode by setting FS in SAR. 18.4.1 I2C Bus Format Figure 18.3 shows the I2C bus formats. Figure 18.4 shows the I2C bus timing. The first frame following a start condition always consists of 8 bits.
2 Section 18 I C Bus Interface 2 (IIC2) 18.4.2 Master Transmit Operation In master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. For master transmit mode operation timing, see figures 18.5 and 18.6. The transmission procedure and operations in master transmit mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) 2.
2 Section 18 I C Bus Interface 2 (IIC2) SCL (Master output) 1 2 3 4 5 6 SDA (Master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 7 8 Bit 1 9 1 Bit 0 Slave address Bit 7 2 Bit 6 R/W SDA (Slave output) A TDRE TEND Address + R/W ICDRT ICDRS Data 1 Address + R/W User [2] Instruction of start processing condition issuance Data 2 Data 1 [4] Write data to ICDRT (second byte) [5] Write data to ICDRT (third byte) [3] Write data to ICDRT (first byte) Figure 18.
2 Section 18 I C Bus Interface 2 (IIC2) 18.4.3 Master Receive Operation In master receive mode, the master device outputs the receive clock, receives data from the slave device, and returns an acknowledge signal. For master receive mode operation timing, see figures 18.7 and 18.8. The reception procedure and operations in master receive mode are shown below. 1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCR1 to 0 to switch from master transmit mode to master receive mode.
2 Section 18 I C Bus Interface 2 (IIC2) Master transmit mode SCL (Master output) Master receive mode 9 1 2 3 4 5 6 7 8 9 SDA (Master output) 1 A SDA (Slave output) Bit 7 A Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 TDRE TEND TRS RDRF ICDRS Data 1 ICDRR User processing Data 1 [3] Read ICDRR [1] Clear TDRE after clearing TEND and TRS [2] Read ICDRR (dummy read) Figure 18.
2 Section 18 I C Bus Interface 2 (IIC2) 18.4.4 Slave Transmit Operation In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. For slave transmit mode operation timing, see figures 18.9 and 18.10. The transmission procedure and operations in slave transmit mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0 bits in ICCR1 to 1.
2 Section 18 I C Bus Interface 2 (IIC2) Slave receive mode SCL (Master output) Slave transmit mode 9 1 2 3 4 5 6 7 8 SDA (Master output) 9 1 A SCL (Slave output) SDA (Slave output) A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 TDRE TEND TRS ICDRT ICDRS Data 1 Data 2 Data 1 Data 3 Data 2 ICDRR User processing [2] Write data to ICDRT (data 1) [2] Write data to ICDRT (data 2) [2] Write data to ICDRT (data 3) Figure 18.
2 Section 18 I C Bus Interface 2 (IIC2) Slave transmit mode SCL (Master output) 9 SDA (Master output) A 1 2 3 4 5 6 7 8 Slave receive mode 9 A SCL (Slave output) SDA (Slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TDRE TEND TRS ICDRT ICDRS Data n ICDRR User processing [3] Clear TEND [4] Read ICDRR (dummy read) after clearing TRS Figure 18.10 Slave Transmit Mode Operation Timing (2) Rev. 1.50 Sep.
2 Section 18 I C Bus Interface 2 (IIC2) 18.4.5 Slave Receive Operation In slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. For slave receive mode operation timing, see figures 18.11 and 18.12. The reception procedure and operations in slave receive mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0 bits in ICCR1 to 1.
2 Section 18 I C Bus Interface 2 (IIC2) SCL (Master output) 9 SDA (Master output) 1 2 3 4 5 6 7 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 SCL (Slave output) SDA (Slave output) A A RDRF ICDRS Data 2 Data 1 ICDRR Data 1 User processing [3] Set ACKBT [3] Read ICDRR [4] Read ICDRR Figure 18.12 Slave Receive Mode Operation Timing (2) 18.4.
2 Section 18 I C Bus Interface 2 (IIC2) (2) Transmit Operation In transmit mode, transmit data is output from SDA, in synchronization with the fall of the transfer clock. The transfer clock is output when MST in ICCR1 is 1, and is input when MST is 0. For transmit mode operation timing, see figure 18.14. The transmission procedure and operations in transmit mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) 2.
2 Section 18 I C Bus Interface 2 (IIC2) (3) Receive Operation In receive mode, data is latched at the rise of the transfer clock. The transfer clock is output when MST in ICCR1 is 1, and is input when MST is 0. For receive mode operation timing, see figure 18.15. The reception procedure and operations in receive mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) 2.
2 Section 18 I C Bus Interface 2 (IIC2) 18.4.7 Noise Canceller The logic levels at the SCL and SDA pins are routed through noise cancellers before being latched internally. Figure 18.16 shows a block diagram of the noise canceller circuit. The noise canceller consists of two cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree.
2 Section 18 I C Bus Interface 2 (IIC2) Start [1] Test the status of the SCL and SDA lines. Initialize Read BBSY in ICCR2 No [2] Set master transmit mode. [1] BBSY=0 ? [3] Issue the start candition. Yes Set MST and TRS in ICCR1 to 1. [2] [4] Set the first byte (slave address + R/W) of transmit data. [3] [5] Wait for 1 byte to be transmitted. Write 1 to BBSY and 0 to SCP. [4] [6] Test the acknowledge transferred from the specified slave device.
2 Section 18 I C Bus Interface 2 (IIC2) Mater receive mode [1] Clear TEND, select master receive mode, and then clear TDRE.* Clear TEND in ICSR Clear TRS in ICCR1 to 0 [1] [3] Dummy-read ICDDR.* Clear TDRE in ICSR Clear ACKBT in ICIER to 0 Dummy-read ICDRR Read RDRF in ICSR No RDRF=1 ? [2] [4] Wait for 1 byte to be received [3] [5] Check whether it is the (last receive - 1). [6] Read the receive data last. [4] [7] Set acknowledge of the final byte. Disable continuous reception (RCVD = 1).
2 Section 18 I C Bus Interface 2 (IIC2) [1] Clear the AAS flag. Slave transmit mode Clear AAS in ICSR [1] Write transmit data in ICDRT [2] [3] Wait for ICDRT empty. [4] Set the last byte of transmit data. [5] Wait for the last byte to be transmitted. Read TDRE in ICSR [3] No [2] Set transmit data for ICDRT (except for the last data). [6] Clear the TEND flag . TDRE=1 ? [7] Set slave receive mode. Yes [8] Dummy-read ICDRR to release the SCL line.
2 Section 18 I C Bus Interface 2 (IIC2) Slave receive mode [1] Clear the AAS flag. Clear AAS in ICSR [1] Clear ACKBT in ICIER to 0 [2] Dummy-read ICDRR [3] [2] Set acknowledge to the transmit device. [3] Dummy-read ICDRR. [4] Wait for 1 byte to be received. [5] Check whether it is the (last receive - 1). Read RDRF in ICSR No [4] RDRF=1 ? [6] Read the receive data. [7] Set acknowledge of the last byte. Yes Last receive - 1? No Read ICDRR Yes [8] Read the (last byte - 1) of receive data.
2 Section 18 I C Bus Interface 2 (IIC2) 18.5 Interrupts There are six interrupt requests in this module; transmit data empty, transmit end, receive data full, NACK receive, STOP recognition, and arbitration lost/overrun error. Table 18.3 shows the contents of each interrupt request. Table 18.
2 Section 18 I C Bus Interface 2 (IIC2) 18.6 Bit Synchronous Circuit In master mode, this module has a possibility that high level period may be short in the two states described below. • When SCL is driven to low by the slave device • When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pullup resistance) Therefore, it monitors SCL and communicates by bit with synchronization. Figure 18.21 shows the timing of the bit synchronous circuit and table 18.
2 Section 18 I C Bus Interface 2 (IIC2) Rev. 1.50 Sep.
Section 19 A/D Converter Section 19 A/D Converter This LSI includes a 10-bit successive approximation A/D converter that allows up to 16 analog input channels to be selected. The block diagram of the A/D converter is shown in figure 19.1. 19.1 • • • • • • • • Features 10-bit resolution 16 input channels Conversion time: 3.
Section 19 A/D Converter Module data bus 10-bit D/A Bus interface A D D R A A D D R B A D D R C A D D R D A D C S R A D C R + φ/4 Control circuit Analog multiplexer AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 Successive approximations register AVCC Internal data bus Comparator Sample-andhold circuit ADTRG [Legend] ADCR: ADCSR: ADDRA: ADDRB: ADDRC: ADDRD: A/D control register A/D control/status register A/D data register A A/D data register B A/D data register C A
Section 19 A/D Converter 19.2 Input/Output Pins Table 19.1 summarizes the input pins used by the A/D converter. The 16 analog input pins are divided into four groups, each of which has four channels. Group 0 comprises analog input pins 0 to 3 (AN0 to AN3), group 1 comprises analog input pins 4 to 7 (AN4 to AN7), group 2 comprises analog input pins 8 to 11 (AN8 to AN11), and group 3 comprises analog input pins 12 to 15 (AN12 to AN15).
Section 19 A/D Converter 19.3 Register Descriptions The A/D converter has the following registers. • • • • • • A/D data register A (ADDRA) A/D data register B (ADDRB) A/D data register C (ADDRC) A/D data register D (ADDRD) A/D control/status register (ADCSR) A/D control register (ADCR) 19.3.1 A/D Data Registers A to D (ADDRA to ADDRD) There are four 16-bit read-only ADDR registers; ADDRA to ADDRD, used to store the results of A/D conversion.
Section 19 A/D Converter 19.3.2 A/D Control/Status Register (ADCSR) ADCSR consists of the control bits and conversion end status bits of the A/D converter.
Section 19 A/D Converter Bit Bit Name Initial Value R/W Description 2 CH2 0 R/W Channel Select 2 to 0 1 CH1 0 R/W 0 CH0 0 R/W Select analog input channels according to a combination of the CH3 bit in ADCR. Rev. 1.50 Sep.
Section 19 A/D Converter 19.3.3 A/D Control Register (ADCR) ADCR enables A/D conversion started by an external trigger signal. Bit Bit Name Initial Value R/W Description 7 TRGE 0 R/W Trigger Enable A/D conversion is started by an assertion of the external trigger signal from timer RD or the falling or rising edge of the external ADTRG signal when this bit is set to 1. The trigger source is selected by bits PMRG3 and PMRG2 in port mode register G (PMRG).
Section 19 A/D Converter 19.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes; single mode and scan mode. When changing the operating mode or analog input channel, in order to prevent incorrect operation, first clear the bit ADST in ADCSR to 0. The ADST bit can be set at the same time as the operating mode or analog input channel is changed. 19.4.
Section 19 A/D Converter 19.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (tD) has passed after the ADST bit is set to 1, then starts conversion. Figure 19.2 shows the A/D conversion timing. Table 19.3 shows the A/D conversion time. As indicated in figure 19.2, the A/D conversion time includes tD and the input sampling time.
Section 19 A/D Converter Table 19.3 A/D Conversion Time (Single Mode) CKS = 0 Item Symbol Min. A/D conversion start delay time tD Input sampling time tSPL A/D conversion time tCONV CKS = 1 Typ. Max. Min. Typ. Max. 6 — 9 — 31 — 4 — 5 — 15 — 131 — 134 69 — 70 Note: All values represent the number of states. 19.4.4 External Trigger Input Timing A/D conversion can also be started by an external trigger input.
Section 19 A/D Converter 19.5 A/D Conversion Accuracy Definitions This LSI's A/D conversion accuracy definitions are given below. • Resolution The number of A/D converter digital output codes • Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 19.4). • Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value 0000000000 to 0000000001 (see figure 19.5).
Section 19 A/D Converter Digital output Ideal A/D conversion characteristic 111 110 101 100 011 Quantization error 010 001 000 1 8 2 8 3 8 4 8 5 8 6 8 7 8 FS Analog input voltage Figure 19.4 A/D Conversion Accuracy Definitions (1) Rev. 1.50 Sep.
Section 19 A/D Converter Digital output Full-scale error Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Offset error Analog input voltage Figure 19.4 A/D Conversion Accuracy Definitions (2) Rev. 1.50 Sep.
Section 19 A/D Converter 19.6 Usage Notes 19.6.1 Permissible Signal Source Impedance This LSI's analog input is designed such that conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 kΩ or less.
Section 19 A/D Converter 19.6.3 Notes on Analog Pins The AN8 to AN15 pins also function as port G pins. Therefore, switching input/output of port G or changing the output value during A/D conversion may affect the conversion accuracy. Evaluate the accuracy of A/D conversion sufficiently, when port G is used as a general I/O port. Rev. 1.50 Sep.
Section 19 A/D Converter Rev. 1.50 Sep.
Section 20 Band-Gap Regulator, Power-On Reset (Optional), and Low-Voltage Detection Circuits (Optional) Section 20 Band-Gap Regulator, Power-On Reset (Optional), and Low-Voltage Detection Circuits (Optional) This LSI includes a band-gap regulator (BGR), and can include a power-on reset circuit and lowvoltage detection circuit as optional circuits. The BGR supplies a reference voltage to the on-chip oscillator and low-voltage detection circuit. Figure 20.1 is a block diagram showing the position of the BGR.
Section 20 Band-Gap Regulator, Power-On Reset (Optional), and Low-Voltage Detection Circuits (Optional) 20.1 Features • BGR circuit Supplies stable reference voltage covering the entire operating voltage range and the operating temperature range. • Power-on reset circuit Uses an external capacitor to generate an internal reset signal when power is first supplied.
Section 20 Band-Gap Regulator, Power-On Reset (Optional), and Low-Voltage Detection Circuits (Optional) φ CK R OVF PSS R RES Internal reset signal Q Noise canceler S CRES Power-on reset circuit Noise canceler Vcc Ladder resistor Internal data bus LVDCR Vreset + − Vint LVDRES + − LVDINT Interrupt control circuit LVDSR Reference voltage generator Interrupt request Low-voltage detection circuit [Legend] PSS: LVDCR: LVDSR: LVDRES: LVDINT: Vreset: Vint: Prescaler S Low-voltage-detection
Section 20 Band-Gap Regulator, Power-On Reset (Optional), and Low-Voltage Detection Circuits (Optional) 20.2 Register Descriptions The low-voltage detection circuit has the following registers. • Low-voltage-detection control register (LVDCR) • Low-voltage-detection status register (LVDSR) 20.2.
Section 20 Band-Gap Regulator, Power-On Reset (Optional), and Low-Voltage Detection Circuits (Optional) Bit Bit Name Initial Value R/W Description 0 LVDUE 0 R/W Voltage-Rise-Interrupt Enable 0: Interrupt on the power-supply voltage rising above the selected detection level disabled 1: Interrupt on the power-supply voltage rising above the selected detection level enabled Table 20.
Section 20 Band-Gap Regulator, Power-On Reset (Optional), and Low-Voltage Detection Circuits (Optional) 20.2.2 Low-Voltage-Detection Status Register (LVDSR) LVDSR indicates whether the power-supply voltage falls below or rises above the respective specified values. Bit Bit Name Initial Value R/W Description 7 to 2 All 1 Reserved These bits are always read as 1, and cannot be modified.
Section 20 Band-Gap Regulator, Power-On Reset (Optional), and Low-Voltage Detection Circuits (Optional) 20.3 20.3.1 Operation Power-On Reset Circuit Figure 20.3 shows the timing of the operation of the power-on reset circuit. As the power-supply voltage rises, the capacitor which is externally connected to the RES pin is gradually charged via the on-chip pull-up resistor (typ. 150 kΩ).
Section 20 Band-Gap Regulator, Power-On Reset (Optional), and Low-Voltage Detection Circuits (Optional) 20.3.2 (1) Low-Voltage Detection Circuit LVDR (Reset by Low Voltage Detect) Circuit Figure 20.4 shows the timing of the LVDR function. The LVDR is enabled after a power-on reset signal is negated. When the power-supply voltage falls below the Vreset voltage (typ. = 2.3 V or 3.6 V), the LVDR clears the LVDRES signal to 0, and resets prescaler S.
Section 20 Band-Gap Regulator, Power-On Reset (Optional), and Low-Voltage Detection Circuits (Optional) (2) LVDI (Interrupt by Low Voltage Detection) Circuit Figure 20.5 shows the timing of LVDI functions. To start the LVDI, set the LVDDE and LVDUE bits in LVDCR to 1. When the power-supply voltage falls below Vint (D) (typ. = 3.7 V) voltage, the LVDI clears the LVDINT signal to 0 and the LVDDF bit in LVDSR is set to 1.
Section 20 Band-Gap Regulator, Power-On Reset (Optional), and Low-Voltage Detection Circuits (Optional) Rev. 1.50 Sep.
Section 21 Power Supply Circuit Section 21 Power Supply Circuit This LSI incorporates an internal power supply step-down circuit. Use of this circuit enables the internal power supply to be fixed at a constant level of approximately 3.0 V, independently of the voltage of the power supply connected to the external VCC pin. As a result, the current consumed when an external power supply is used at 3.0 V or above can be held down to virtually the same low level as when used at approximately 3.0 V.
Section 21 Power Supply Circuit 21.2 When Not Using Internal Power Supply Step-Down Circuit When the internal power supply step-down circuit is not used, connect the external power supply to the VCL pin and VCC pin, as shown in figure 21.2. The external power supply is then input directly to the internal power supply. The permissible range for the power supply voltage is 3.0 V to 3.6 V. Operation cannot be guaranteed if a voltage outside this range (less than 3.0 V or more than 3.6 V) is input.
Section 22 List of Registers Section 22 List of Registers The register list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. • • • • Register addresses (address order) Registers are listed from the lower allocation addresses. Registers are classified by functional modules. The data bus width is indicated. The number of access states is indicated. 2.
Section 22 List of Registers 22.1 Register Addresses (Address Order) The data-bus width column indicates the number of bits. The access-state column shows the number of states of the specified basic clock that is required for access to the register. Note: Access to undefined or reserved addresses is prohibited. Correct operation of the access itself or later operations is not guaranteed when such a register is accessed.
Section 22 List of Registers Module Name Data Bus Access Width State H'FFF148 Timer RD (Channel 2) 16* 1 4 16 H'FFF14A Timer RD (Channel 3) 16* 1 4 GRA_3 16 H'FFF14C Timer RD (Channel 3) 16* 1 4 General register B_3 GRB_3 16 H'FFF14E Timer RD (Channel 3) 16* 1 4 General register C_3 GRC_3 16 H'FFF150 Timer RD (Channel 3) 16* 1 4 General register D_3 GRD_3 16 H'FFF152 Timer RD (Channel 3) 16* 1 4 Timer RC counter TRCCNT 16 H'FFF180 Timer RC 16* 1 4 16* 1
Section 22 List of Registers Register Name Abbreviation Bit No.
Section 22 List of Registers Data Bus Access Width State Register Name Abbreviation Bit No.
Section 22 List of Registers Data Bus Access Width State Register Name Abbreviation Bit No.
Section 22 List of Registers Register Name Abbreviation Bit No.
Section 22 List of Registers Register Name Abbreviation Bit No.
Section 22 List of Registers Register Name Abbreviation Bit No.
Section 22 List of Registers Register Name Abbreviation Bit No.
Section 22 List of Registers 22.2 Register Bits The addresses and bit names of the registers in the on-chip peripheral modules are listed below. The 16-bit register is indicated in two rows, 8 bits for each row.
Section 22 List of Registers Register Module Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name GRC_2 GRC2H7 GRC2H6 GRC2H5 GRC2H4 GRC2H3 GRC2H2 GRC2H1 GRC2H0 Timer RD GRC2L7 GRC2L6 GRC2L5 GRC2L4 GRC2L3 GRC2L2 GRC2L1 GRC2L0 GRD2H7 GRD2H6 GRD2H5 GRD2H4 GRD2H3 GRD2H2 GRD2H1 GRD2H0 GRD2L7 GRD2L6 GRD2L5 GRD2L4 GRD2L3 GRD2L2 GRD2L1 GRD2L0 GRD_2 TRDCNT_3 GRA_3 GRB_3 GRC_3 GRD_3 TRCCNT GRA GRB GRC TCNT3H7 TCNT3H6 TCNT3H5 TCNT3H4 TCNT3H3 TCNT3H2 TCNT3H1
Section 22 List of Registers Register Module Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name ADDRA AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 A/D AD1 AD0 — — — — — — AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 — — — — — — ADDRB ADDRC converter AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 — — — — — — AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 — — — — — — ADCSR ADF ADIE ADST SCAN CKS CH2 CH1 CH0 ADCR TRGE — — — — — — CH3 PD
Section 22 List of Registers Register Module Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name TRDCR_1 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Timer RD TRDIORA_1 — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0 TRDIORC_1 IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 TRDSR_1 — — UDF OVF IMFD IMFC IMFB IMFA TRDIER_1 — — — OVIE IMIED IMIEC IMIEB IMIEA POCR_1 — — — — — POLD POLC POLB TRDDF_1 DFCK1 DFCK0 — — DFD DFC DFB DFA TRDSTR_01 — —
Section 22 List of Registers Register Module Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name TRDFCR_23 PWM3 STCLK ADEG ADTRG OLS1 OLS0 CMD1 CMD0 Timer RD TRDOER1_23 ED1 EC1 EB1 EA1 ED0 EC0 EB0 EA0 TRDOER2_23 PTO — — — — — — — TRDOCR_23 TOD1 TOC1 TOB1 TOA1 TOD0 TOC0 TOB0 TOA0 TRCMR CTS — BUFEB BUFEA PWM2 PWMD PWMC PWMB TRCCR1 CCLR CKS2 CKS1 CKS0 TOD TOC TOB TOA TRCIER OVIE — — — IMIED IMIEC IMIEB IMIEA TRCSR OVF — — — IM
Section 22 List of Registers Register Module Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name SMR_2 COM CHR PE PM STOP MP CKS1 CKS0 SCI3_2 BRR_2 BRR7 BRR6 BRR5 BRR4 BRR3 BRR2 BRR1 BRR0 SCR3_2 TIE RIE TE RE MPIE TEIE CKE1 CKE0 TDR_2 TDR7 TRD6 TDR5 TDR4 TRD3 TRD2 TRD1 TRD0 SSR_2 TDRE RDRF OER FER PER TEND MPBR MPBT RDR_2 RDR7 RDR6 RDR5 RDR4 RDR3 RDR2 RDR1 RDR0 ICCR1 ICE RCVD MST TRS CKS3 CKS2 CKS1 CKS0 ICCR2 BBSY SCP SDAO
Section 22 List of Registers Register Module Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name TDR TDR7 TRD6 TDR5 TDR4 TRD3 TRD2 TRD1 TRD0 SCI3 SSR TDRE RDRF OER FER PER TEND MPBR MPBT RDR RDR7 RDR6 RDR5 RDR4 RDR3 RDR2 RDR1 RDR0 PWDRL PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0 PWDRU — — PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDRU1 PWDRU0 PWCR — — — — — — — PWCR0 TCSRWD B6WI TCWE B4WI TCSRWE B2WI WDON BOWI WRST TCWD TCWD7
Section 22 List of Registers Register Module Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name PCR5 PCR57 PCR56 PCR55 PCR54 PCR53 PCR52 PCR51 PCR50 I/O port PCR7 PCR77 PCR76 PCR75 PCR74 — PCR72 PCR71 PCR70 PCR8 PCR87 PCR86 PCR85 — — — — — PCRC — — — — PCRC3 PCRC2 PCRC1 PCRC0 SYSCR3 STS3 — — — — — — — SYSCR1 SSBY STS2 STS1 STS0 NESEL — — — SYSCR2 SMSEL LSON DTON MA2 MA1 MA0 SA1 SA0 IEGR1 NMIEG — — — IEG3 IEG2 IEG1 IE
Section 22 List of Registers 22.
Section 22 List of Registers Register Name Reset Active Sleep Subactive Subsleep Standby Module SMR_3 Initialized — — Initialized Initialized Initialized SCI3_3 BRR_3 Initialized — — Initialized Initialized Initialized SCR3_3 Initialized — — Initialized Initialized Initialized TDR_3 Initialized — — Initialized Initialized Initialized SSR_3 Initialized — — Initialized Initialized Initialized RDR_3 Initialized — — Initialized Initialized Initialized SMCR_3 In
Section 22 List of Registers Register Name Reset Active Sleep Subactive Subsleep Standby Module TRDCR_0 Initialized — — — — — Timer RD TRDIORA_0 Initialized — — — — — (Channel 0) TRDIORC_0 Initialized — — — — — TRDSR_0 Initialized — — — — — TRDIER_0 Initialized — — — — — POCR_0 Initialized — — — — — TRDDF_0 Initialized — — — — — TRDCR1 Initialized — — — — — Timer RD TRDIORA_1 Initialized — — — — — (Channel 1) TRDIORC_1 Initialized —
Section 22 List of Registers Register Name Reset Active Sleep Subactive Subsleep Standby Module TRDCR_3 Initialized — — — — — Timer RD TRDIORA_3 Initialized — — — — — (Channel 3) TRDIORC_3 Initialized — — — — — TRDSR_3 Initialized — — — — — TRDIER_3 Initialized — — — — — POCR_3 Initialized — — — — — TRDDF_3 Initialized — — — — — TRDSTR_23 Initialized — — — — — TRDMDR_23 Initialized — — — — — TRDPMR_23 Initialized — — — — — TRDFCR
Section 22 List of Registers Register Name Reset Active Sleep Subactive Subsleep Standby Module LVDCR Initialized — — — — — LVD (optional) LVDSR Initialized — — — — — CKCSR Initialized — — — — — Clock pulse generator RCCR Initialized — — — — — RCTRMDPR Initialized — — — — — On-chip oscillator RCTRMDR Initialized — — — — — ICRA Initialized — — — — — ICRB Initialized — — — — — ICRC Initialized — — — — — ICRD Initialized — — — — —
Section 22 List of Registers Register Name Reset Active Sleep Subactive Subsleep Standby Module FLMCR1 Initialized — — Initialized Initialized Initialized ROM FLMCR2 Initialized — — — — — FLPWCR Initialized — — — — — EBR1 Initialized — — Initialized Initialized Initialized FENR Initialized — — — — — TCRV0 Initialized — — Initialized Initialized Initialized TCSRV Initialized — — Initialized Initialized Initialized TCORA Initialized — — Initialized
Section 22 List of Registers Register Name Reset Active Sleep Subactive Subsleep Standby Module PUCR1 Initialized — — — — — I/O port PUCR5 Initialized — — — — — PDR1 Initialized — — — — — PDR2 Initialized — — — — — PDR3 Initialized — — — — — PDR5 Initialized — — — — — PDR7 Initialized — — — — — PDR8 Initialized — — — — — PDRC Initialized — — — — — PMR1 Initialized — — — — — PMR5 Initialized — — — — — PMR3 Initialized — —
Section 22 List of Registers Register Name Reset Active Sleep Subactive Subsleep Standby Module MSTCR1 Initialized — — — — — MSTCR2 Initialized — — — — — Power-down modes Notes: is not initialized * WDT: Watchdog timer Rev. 1.50 Sep.
Section 23 Electrical Characteristics Section 23 Electrical Characteristics 23.1 Absolute Maximum Ratings Table 23.1 Absolute Maximum Ratings Item Symbol Value Unit Notes Power supply voltage VCC –0.3 to +7.0 V Analog power supply voltage AVCC –0.3 to +7.0 V Input voltage VIN –0.3 to VCC +0.3 V Ports F, G –0.3 to AVCC +0.3 V X1 –0.3 to 4.
Section 23 Electrical Characteristics 23.2 Electrical Characteristics 23.2.1 Power Supply Voltage and Operating Ranges (1) Power Supply Voltage and External Oscillation Frequency Range φ OSC (MHz) φ W (kHz) 20.0 32.768 10.0 4.0 3.0 4.0 5.5 • AVCC = 3.0 to 5.5 V • Active mode • Sleep mode Rev. 1.50 Sep. 18, 2007 Page 498 of 584 REJ09B0240-0150 VCC (V) 3.0 4.0 5.5 • AVCC = 3.0 to 5.
Section 23 Electrical Characteristics (2) Power Supply Voltage and Operating Frequency Range φ (MHz) φSUB (kHz) 20.0 16.384 10.0 8.192 4.096 4.0 3.0 4.0 5.5 3.0 VCC (V) • AVCC = 3.0 to 5.5 V • Active mode • Sleep mode (When MA2 in SYSCR2 = 0 ) 4.0 5.5 VCC (V) • AVCC = 3.0 to 5.5 V • Subactive mode • Subsleep mode φ (kHz) 2500 1250 78.125 3.0 4.0 5.5 V (V) CC • AVCC = 3.0 to 5.
Section 23 Electrical Characteristics (4) Range of Power Supply Voltage and Oscillation Frequency when Low-Voltage Detection Circuit is Used φosc (MHz) 20.0 16.0 4.0 3.0 4.5 5.5 VCC(V) Operation guarantee range Operation guarantee range except A/D conversion accuracy 23.2.2 DC Characteristics Table 23.2 DC Characteristics (1) VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C/–40 to +85°C, unless otherwise indicated. Values Item Symbol Applicable Pins Test Condition Min. Typ. Max.
Section 23 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition Min. Typ. Max. Unit Input high VIH RXD, RXD_2, VCC = 4.0 to 5.5 V VCC × 0.7 VCC + 0.3 V VCC × 0.8 VCC + 0.3 V voltage Notes RXD_3, SCL, SDA, P10 to P12, P14 to P17, P20 to P27, P30 to P37, P50 to P57, P70 to P72, P74 to P77, P85 to P87, PC0 to PC3, PD0 to PD7, PE0 to PE7, PH0 to PH7, PJ0, PJ1 PF0 to PF7, AVCC = PG0 to PG7 4.0 to 5.5 V AVCC = AVCC × 0.7 AVCC + 0.3 V AVCC × 0.
Section 23 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition Min. Typ. Max. Unit Input low VIL RES, NMI, VCC = 4.0 to 5.5 V –0.3 VCC × 0.2 V –0.3 VCC × 0.1 V –0.3 VCC × 0.3 V –0.3 VCC × 0.2 V AVCC = 4.0 to 5.5 V –0.3 AVCC × 0.3 V AVCC = 3.0 to 5.5 V –0.3 AVCC × 0.2 V VCC = 4.0 to 5.5 V –0.3 0.5 V –0.3 0.
Section 23 Electrical Characteristics Values Item Symbol Output high VOH voltage Output low voltage VOL Applicable Pins Test Condition Min. Typ. Max. Unit P10 to P12, P14 to P17, P20 to P27, P30 to P37, P50 to P55, P70 to P72, P74 to P77, P85 to P87, PC0 to PC3, PD0 to PD7, PE0 to PE7, PH0 to PH7, PJ0, PJ1 VCC = 4.0 to 5.5 V –IOH = 5.0 mA VCC – 1.0 V –IOH = 0.1 mA VCC – 0.5 V PG0 to PG7 –IOH = 0.1 mA AVCC – 0.5 V P56, P57 4.0 V ≤ VCC ≤ 5.5 V –IOH = 0.1 mA VCC – 2.
Section 23 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition Input/ output leakage current | IIL | OSC1, RES, NMI, WKP0 to WKP5, IRQ0 to IRQ3, ADTRG, TRGV, TMRIV, TMCIV, FTIOA0 to FTIOD0, FTIOA1 to FTIOD1, FTIOA2 to FTIOD2, FTIOA3 to FTIOD3, FTIOA to FTIOD, RXD, SCK3, RXD_2, SCK3_2, RXD_3, SCK3_3, SCL, SDA, TMIB1, FTCI, TRGC, TRCOI, TRDOI_0, TRDOI_1 P10 to P12, P14 to P17, P20 to P27, P30 to P37, P50 to P57, P70 to P72, P74 to P77, P85 to P87, PC0 to PC3, PD0 to PD7, PE0 to
Section 23 Electrical Characteristics Values Item Symbol Active mode IOPE1 Applicable Pins Test Condition Min. Typ. Max. Unit Notes VCC Active mode 1 VCC = 5.0 V, fOSC = 20 MHz 33.0 40.0 mA * Active mode 1 VCC = 3.0 V, fOSC = 10 MHz 15.0 Active mode 2 VCC = 5.0 V, fOSC = 20 MHz 6.0 7.5 Active mode 2 VCC = 3.0 V, fOSC = 10 MHz 4.5 Sleep mode 1 VCC = 5.0 V, fOSC = 20 MHz 22.0 30.0 Sleep mode 1 VCC = 3.0 V, fOSC = 10 MHz 12.0 Sleep mode 2 VCC = 5.
Section 23 Electrical Characteristics Values Item Symbol Applicable Pins Standby ISTBY VCC mode supply Test Condition Min. Typ. Max. Unit Notes 32-kHz crystal 135 µA * Optional 5.0 2.0 resonator not used current RAM data VRAM VCC * V retaining voltage Note: * Pin states during supply current measurement are given below (excluding current in the pull-up MOS transistors and output buffers).
Section 23 Electrical Characteristics Table 23.2 DC Characteristics (2) VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C/–40 to +85°C, unless otherwise indicated. Values Item Symbol Applicable Pins Allowable output low current (per pin) IOL Allowable output low current (total) Allowable output high current (per pin) ∑IOL –IOH Test Condition Min. Typ. Max. Unit Output pins except ports VCC = 4.0 to 5.5 V D, E, G, PH4 to PH7, SCL, and SDA 2.0 mA Ports D, E, PH4 to PH7 20.
Section 23 Electrical Characteristics 23.2.3 AC Characteristics Table 23.3 AC Characteristics VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C/–40 to +85°C, unless otherwise indicated. Item Symbol System clock oscillation fOSC frequency System clock (φ)cycle time tcyc Subclock oscillation frequency fW Watch clock (φW) cycle time tW Subclock (φSUB) cycle time tsubcyc Values Applicable Pins Test Condition OSC1, OSC2 VCC = 4.0 to 5.5 V Min. Typ. Max. Unit MHz 4.0 20.0 4.0 10.
Section 23 Electrical Characteristics Values Min. Typ. Max. Unit Reference Figure NMI 2tcyc + 1500 ns 2tsubcyc + 1500 ns ns Figure 23.
Section 23 Electrical Characteristics Values Item Symbol Applicable Pins On-chip oscillator fRC oscillation frequency Test Condition Min. Typ. Max. Unit Vcc = 4.0 to 5.5V 39.40 40.00 40.60 MHz 39.20 40.00 40.80 MHz 38.80 40.00 41.20 MHz 38.40 40.00 41.60 MHz 38.40 40.00 41.60 MHz 38.00 40.00 42.00 MHz 31.52 32.00 32.48 MHz 31.36 32.00 32.64 MHz 31.04 32.00 32.96 MHz 30.72 32.00 33.28 MHz 30.72 32.00 33.
Section 23 Electrical Characteristics Values Item Symbol Applicable Pins On-chip oscillator fRC oscillation frequency Test Condition Min. Typ. Max. Unit Ta = -40°C to +85°C 30.40 32.00 33.60 MHz Reference Figure FSEL = 0 VCLSEL = 0 Note: * Determined by the MA2, MA1, MA0, SA1, and SA0 bits in the system control register 2 (SYSCR2). Table 23.4 I2C Bus Interface Timing VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C/–40 to +85°C, unless otherwise indicated.
Section 23 Electrical Characteristics Table 23.5 Serial Communication Interface (SCI) Timing VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C/–40 to +85°C, unless otherwise indicated.
Section 23 Electrical Characteristics 23.2.4 A/D Converter Characteristics Table 23.6 A/D Converter Characteristics VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C/–40 to +85°C, unless otherwise indicated. Item Symbol Applicable Pins Test Condition Values Min. Typ. Max. Unit Notes Analog power supply AVCC voltage AVCC 3.0 VCC 5.5 V * Analog input voltage AN0 to AN15 VSS – 0.3 AVIN Analog power supply AIOPE current AISTOP1 1 AVCC + 0.3 V AVCC AVCC = 5.
Section 23 Electrical Characteristics Item Symbol Conversion time (single mode) Values Applicable Pins Test Condition AN0 to AN7 AVCC = 4.0 to 134 5.5 V Min. Typ. Max. Unit tcyc Nonlinearity error ±3.5 LSB Offset error ±3.5 LSB Full-scale error ±3.5 LSB Quantization error ±0.5 LSB Absolute accuracy ±4.0 LSB tcyc Conversion time (single mode) AN8 to AN15 AVCC = 4.0 to 134 5.5 V Nonlinearity error ±5.
Section 23 Electrical Characteristics 23.2.6 Flash Memory Characteristics Table 23.8 Flash Memory Characteristics VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C/–40 to +85°C, unless otherwise indicated. Test Condition Values Min. Typ. Max.
Section 23 Electrical Characteristics Item Erasing Symbol Test Condition Values Min. Typ. Max.
Section 23 Electrical Characteristics 23.2.7 Power-Supply-Voltage Detection Circuit Characteristics (Optional) Table 23.9 Power-Supply-Voltage Detection Circuit Characteristics VSS = 0.0 V, Ta = –20 to +75°C/–40 to +85°C, unless otherwise indicated. Item Symbol Test Condition Power-supply falling detection voltage Vint (D) Power-supply rising detection voltage Values Min. Typ. Max. Unit LVDSEL = 0 3.5 3.7 V Vint (U) LVDSEL = 0 4.1 4.
Section 23 Electrical Characteristics 23.2.8 Power-On Reset Circuit Characteristics (Optional) Table 23.10 Power-On Reset Circuit Characteristics VSS = 0.0 V, Ta = –20 to +75°C/–40 to +85°C, unless otherwise indicated. Item Symbol Pull-up resistance of RES pin RRES Power-on reset start voltage* Vpor Note: 23.3 * Test Condition Values Min. Typ. Max.
Section 23 Electrical Characteristics NMI, IRQ0 to IRQ3, WKP0 to WKP5, VIH ADTRG, FTIOA to FTIOD, VIL FTIOA0 to FTIOD0, FTIOA1 to FTIOD1, FTIOA2 to FTIOD2, FTIOA3 to FTIOD3, TMCIV, TMRIV, TRGV, FTCI, TMIB1, TRGC, TRCOI, TRDOI_0, TRDOI_1 t IL t IH Figure 23.3 Input Timing VIH SDA VIL tBUF tSTAH tSCLH tSTAS tSP tSTOS SCL P* S* tSf Sr* tSCLL P* tSDAS tSCL tSDAH Note: * S, P, and Sr represent the following: S: Start condition P: Stop condition Sr: Retransmission start condition Figure 23.
Section 23 Electrical Characteristics t Scyc SCK3 VIH or VOH * VIL or VOL * t TXD TXD (transmit data) VOH * VOL * t RXS t RXH RXD (receive data) Note: * Output timing reference levels Output high: VOH = 2.0 V VOL = 0.8 V Output low: Load conditions are shown in figure 23.7. Figure 23.6 SCI Input/Output Timing in Clocked Synchronous Mode 23.4 Output Load Condition VCC 2.4 kΩ LSI output pin 30 pF 12 k Ω Figure 23.7 Output Load Circuit Rev. 1.50 Sep.
Appendix Appendix A. Instruction Set A.
Symbol Description ∧ Logical AND of the operands on both sides ∨ Logical OR of the operands on both sides ⊕ Logical exclusive OR of the operands on both sides ¬ NOT (logical complement) ( ), < > Contents of operand ↔ Appendix Changed according to execution result * Undetermined (no guaranteed value) 0 Cleared to 0 1 Set to 1 — Not affected by execution of the instruction ∆ Varies depending on conditions, described in notes Note: General registers include 8-bit registers (R0H to R7H
Appendix Table A.1 Instruction Set 1. Data Transfer Instructions Advanced Normal — — 0 — 2 @ERs → Rd8 — — 0 — 4 4 @(d:16, ERs) → Rd8 — — 0 — 6 8 @(d:24, ERs) → Rd8 — — 0 — 10 @ERs → Rd8 — — 0 — 6 — 4 0 — 6 0 — 8 0 — 4 0 — 6 0 — 10 0 — 6 — 4 0 — 6 0 — 8 0 — 4 0 — 2 0 — 4 0 — 6 0 — 10 0 — 6 — 6 0 — 8 0 — 4 0 — 6 0 — 10 2 2 ↔ ↔ ↔ ↔ ↔ ↔ 2 Rs8 → Rd8 ↔ ↔ ↔ ↔ ↔ ↔ B C — 0 ↔ ↔ ↔ ↔ ↔ ↔ ↔ MOV.
Appendix Condition Code Advanced 2 0 — 8 0 — 10 0 — 14 0 — 10 — 10 0 — 12 0 — 8 0 — 10 0 — 14 0 — 10 — 10 0 — 12 0 — 6 — 10 — 6 — 10 ↔ — ↔ 6 0 ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ — ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ 8 0 ↔ ↔ ↔ ↔ ↔ ↔ 6 — ↔ ↔ ↔ ↔ ↔ ↔ — 0 0 0 0 — — ↔ ↔ ↔ 6 ↔ ↔ ↔ C — 0 — — ↔ V ↔ Z 0 — — ↔ N ↔ H — — 0 — — ↔ I ERd32–2 → ERd32 2 Normal — @@aa @(d, PC) Operation @aa @–ERn/@ERn+ @(d, ERn) @ERn Rn W #xx MOV.W Rs, @–ERd No.
Appendix 2. Arithmetic Instructions — (2) ↔ ↔ ↔ ↔ ↔ — (2) ↔ (3) ↔ ↔ Rd16+Rs16 → Rd16 — (1) ERd32+#xx:32 → ↔ ↔ ↔ ↔ ↔ — (1) ↔ ↔ ↔ ↔ ↔ Rd16+#xx:16 → Rd16 2 ↔ — 2 Rd8+#xx:8 +C → Rd8 — 2 B 2 Rd8+Rs8 +C → Rd8 — ↔ ↔ Rd8+Rs8 → Rd8 ↔ — Advanced C ↔ ↔ I Rd8+#xx:8 → Rd8 Normal V ↔ ↔ ↔ ↔ ↔ L Z ↔ ADD.L #xx:32, ERd N ↔ ↔ W H ↔ ↔ ADD.W Rs, Rd — W @@aa ADD.W #xx:16, Rd Condition Code @(d, PC) B No. of States*1 Operation @aa ADD.
Appendix Advanced I Normal H N Z V C DEC.L #1, ERd L 2 ERd32–1 → ERd32 — — — 2 DEC.L #2, ERd L 2 ERd32–2 → ERd32 — — ↔ ↔ — @@aa @(d, PC) @aa @–ERn/@ERn+ @(d, ERn) @ERn Rn Condition Code Operation — 2 DAS.Rd B 2 Rd8 decimal adjust — ↔ ↔ ↔ DAS No. of States*1 ↔ ↔ ↔ DEC #xx Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) * — 2 — — — — — — 14 — — — — — — 22 * → Rd8 MULXU MULXU.
Appendix NEG.W Rd W 2 0–Rd16 → Rd16 — NEG.L ERd L 2 0–ERd32 → ERd32 — EXTU.W Rd W 2 0 → ( — — 0 — — 0 — — — — Advanced C Normal V ↔ ↔ ↔ — ↔ ↔ ↔ Z ↔ ↔ ↔ 0–Rd8 → Rd8 ↔ ↔ ↔ ↔ 2 2 0 — 2 ↔ H B 0 — 2 ↔ I NEG.B Rd 0 — 2 ↔ N ↔ ↔ ↔ — @@aa @(d, PC) @aa @–ERn/@ERn+ @(d, ERn) @ERn Rn Condition Code Operation ↔ EXTU No. of States*1 ↔ NEG #xx Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) 0 — 2 2 2 of Rd16) EXTU.
Appendix 3. Logic Instructions NOT AND.L ERs, ERd L OR.B #xx:8, Rd B OR.B Rs, Rd B OR.W #xx:16, Rd W OR.W Rs, Rd W OR.L #xx:32, ERd L OR.L ERs, ERd L XOR.B #xx:8, Rd B XOR.B Rs, Rd B XOR.W #xx:16, Rd W XOR.W Rs, Rd W XOR.L #xx:32, ERd L XOR.L ERs, ERd L NOT.
Appendix 4. Shift Instructions W 2 SHAL.L ERd L 2 SHAR SHAR.B Rd B 2 SHAR.W Rd W 2 SHAR.L ERd L 2 SHLL.B Rd B 2 SHLL.W Rd W 2 SHLL.L ERd L 2 SHLR SHLR.B Rd B 2 SHLR.W Rd W 2 SHLR.L ERd L 2 ROTXL ROTXL.B Rd B 2 ROTXL.W Rd W 2 ROTXL.L ERd L 2 ROTXR ROTXR.B Rd B 2 ROTXR.W Rd W 2 ROTXR.L ERd L 2 ROTL ROTL.B Rd B 2 ROTL.W Rd W 2 ROTL.L ERd L 2 ROTR ROTR.B Rd B 2 ROTR.W Rd W 2 ROTR.
Appendix 5. Bit-Manipulation Instructions BSET BSET Rn, @aa:8 B BCLR BCLR #xx:3, Rd B BCLR #xx:3, @ERd B BCLR #xx:3, @aa:8 B BCLR Rn, Rd B BCLR Rn, @ERd B BCLR Rn, @aa:8 B BNOT BNOT #xx:3, Rd B 2 4 4 2 4 4 2 4 4 2 H N Z V C Advanced B 4 I Normal BSET Rn, @ERd 4 — B 2 @@aa BSET Rn, Rd Condition Code @(d, PC) B No.
Appendix BST BIST B BLD #xx:3, @aa:8 B BILD #xx:3, Rd B BILD #xx:3, @ERd B BILD #xx:3, @aa:8 B BST #xx:3, Rd B BST #xx:3, @ERd B BST #xx:3, @aa:8 B BIST #xx:3, Rd B BIST #xx:3, @ERd B BIST #xx:3, @aa:8 B BAND BAND #xx:3, Rd BAND #xx:3, @ERd B BAND #xx:3, @aa:8 B BIAND BIAND #xx:3, Rd BOR BIOR B B BIAND #xx:3, @ERd B BIAND #xx:3, @aa:8 B BOR #xx:3, Rd B BOR #xx:3, @ERd B BOR #xx:3, @aa:8 B BIOR #xx:3, Rd B BIOR #xx:3, @ERd B BIOR #xx:3, @aa:8 B BXOR BXOR #xx:3
Appendix 6. Branching Instructions Bcc No.
Appendix JMP BSR JMP @ERn — JMP @aa:24 — JMP @@aa:8 — BSR d:8 — No.
Appendix 7. System Control Instructions Condition Code Advanced @@aa I Normal — @(d, PC) Operation @aa @–ERn/@ERn+ @(d, ERn) @ERn Rn No.
Appendix 8. Block Transfer Instructions EEPMOV EEPMOV. B — No. of States*1 Condition Code repeat H N Z V C — — — — — — @R5 → @R6 Advanced I 4 if R4L ≠ 0 then Normal — @@aa @(d, PC) Operation @aa @–ERn/@ERn+ @(d, ERn) @ERn Rn #xx Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) 8+ 4n*2 R5+1 → R5 R6+1 → R6 R4L–1 → R4L until R4L=0 else next EEPMOV.
REJ09B0240-0150 Rev. 1.50 Sep. 18, 2007 Page 536 of 584 SUBX OR XOR AND MOV C D E F BILD BIST BLD BST TRAPA BEQ B BIAND BAND AND RTE BNE MOV.B Table A.2 (2) CMP BIXOR BXOR XOR BSR BCS AND.B LDC 7 A BIOR BOR OR RTS BCC XOR.B ANDC 6 ADDX BTST DIVXU BLS OR.B XORC 5 9 BCLR MULXU BHI Table A.2 (2) ORC 4 ADD BNOT DIVXU BRN Table A.2 (2) LDC 3 MOV BVS 9 Table A.2 (2) SUB ADD Table A.2 (2) BVC 8 BMI MOV Table A.2 (2) Table A.
MOV 7A BRA 58 MOV DAS 1F 79 SUBS 1B 1 ADD ADD BRN NOT 17 DEC ROTXR 13 1A ROTXL 12 DAA 0F SHLR ADDS 0B 11 INC 0A SHLL MOV 01 10 0 CMP CMP BHI 2 1st byte AH AL SUB SUB BLS NOT ROTXR ROTXL SHLR SHLL 3 4 OR OR BCC LDC/STC 2nd byte BH BL XOR XOR BCS DEC EXTU INC 5 AND AND BNE 6 BEQ DEC EXTU INC 7 BVC SUB NEG 9 BVS ROTR ROTL SHAR SHAL ADDS SLEEP 8 BPL A MOV BMI NEG CMP SUB ROTR ROTL SHAR C D BGE BLT DEC EXTS INC Tabl
REJ09B0240-0150 Rev. 1.50 Sep. 18, 2007 Page 538 of 584 DIVXS 3 BSET 1 7Dr07* BSET 2 7Faa7* BNOT BNOT BNOT BCLR BCLR BCLR Notes: 1. r is the register designation field. 2. aa is the absolute address field.
Appendix A.3 Number of Execution States The status of execution for each instruction of the H8/300H CPU and the method of calculating the number of states required for instruction execution are shown below. Table A.4 shows the number of cycles of each type occurring in each instruction, such as instruction fetch and data read/write. Table A.3 shows the number of states required for each cycle.
Appendix Table A.3 Number of Cycles in Each Instruction Access Location Execution Status (Instruction Cycle) On-Chip Memory On-Chip Peripheral Module 2 — Instruction fetch SI Branch address read SJ Stack operation SK Byte data access SL 2 or 3* Word data access SM 2 or 3* Internal operation SN Note: * 1 Depends on which on-chip peripheral module is accessed. For details, see section 22.1, Register Addresses (Address Order). Rev. 1.50 Sep.
Appendix Table A.4 Number of Cycles in Each Instruction Instruction Mnemonic Instruction Fetch I ADD ADD.B #xx:8, Rd 1 ADD.B Rs, Rd 1 ADD.W #xx:16, Rd 2 ADD.W Rs, Rd 1 ADD.L #xx:32, ERd 3 ADD.L ERs, ERd 1 ADDS ADDS #1/2/4, ERd 1 ADDX ADDX #xx:8, Rd 1 ADDX Rs, Rd 1 AND AND.B #xx:8, Rd 1 AND.B Rs, Rd 1 AND.W #xx:16, Rd 2 AND.W Rs, Rd 1 AND.L #xx:32, ERd 3 AND.L ERs, ERd 2 Branch Stack Addr.
Appendix Instruction Branch Instruction Mnemonic Bcc BCLR BIAND BILD Byte Data Word Data Internal Fetch Addr.
Appendix Instruction Mnemonic Instruction Fetch I BIOR BIOR #xx:8, Rd 1 BIOR #xx:8, @ERd 2 1 BIOR #xx:8, @aa:8 2 1 BIST #xx:3, Rd 1 BIST #xx:3, @ERd 2 2 BIST #xx:3, @aa:8 2 2 BIXOR #xx:3, Rd 1 BIXOR #xx:3, @ERd 2 1 BIXOR #xx:3, @aa:8 2 1 BLD #xx:3, Rd 1 BLD #xx:3, @ERd 2 1 BLD #xx:3, @aa:8 2 1 BNOT #xx:3, Rd 1 BNOT #xx:3, @ERd 2 2 BNOT #xx:3, @aa:8 2 2 BNOT Rn, Rd 1 BNOT Rn, @ERd 2 2 BNOT Rn, @aa:8 2 2 BOR #xx:3, Rd 1 BOR #xx:3, @ERd 2 1 BOR #xx:3, @a
Appendix Instruction Branch Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic I J L M N BTST BTST #xx:3, Rd 1 BTST #xx:3, @ERd 2 1 BTST #xx:3, @aa:8 2 1 BTST Rn, Rd 1 BTST Rn, @ERd 2 1 1 BXOR CMP Stack K BTST Rn, @aa:8 2 BXOR #xx:3, Rd 1 BXOR #xx:3, @ERd 2 1 BXOR #xx:3, @aa:8 2 1 CMP.B #xx:8, Rd 1 CMP.B Rs, Rd 1 CMP.W #xx:16, Rd 2 CMP.W Rs, Rd 1 CMP.L #xx:32, ERd 3 CMP.
Appendix Instruction Branch Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic I J L M N INC INC.B Rd 1 INC.W #1/2, Rd 1 INC.L #1/2, ERd 1 JMP @ERn 2 JMP @aa:24 2 JMP @@aa:8 2 JSR @ERn 2 1 JSR @aa:24 2 1 JSR @@aa:8 2 LDC #xx:8, CCR 1 LDC Rs, CCR 1 LDC@ERs, CCR 2 1 LDC@(d:16, ERs), CCR 3 1 LDC@(d:24,ERs), CCR 5 1 LDC@ERs+, CCR 2 1 LDC@aa:16, CCR 3 1 LDC@aa:24, CCR 4 1 MOV.B #xx:8, Rd 1 MOV.
Appendix Instruction Mnemonic Instruction Fetch I MOV MOV.B Rs, @aa:16 2 1 MOV.B Rs, @aa:24 3 1 MOV.W #xx:16, Rd 2 MOV.W Rs, Rd 1 MOV.W @ERs, Rd 1 1 MOV.W @(d:16,ERs), Rd 2 1 MOV.W @(d:24,ERs), Rd 4 1 MOV.W @ERs+, Rd 1 1 MOV.W @aa:16, Rd 2 1 MOV.W @aa:24, Rd 3 1 MOV.W Rs, @ERd 1 1 MOV.W Rs, @(d:16,ERd) 2 1 MOV.W Rs, @(d:24,ERd) 4 1 MOV.W Rs, @-ERd 1 1 MOV.W Rs, @aa:16 2 1 MOV.W Rs, @aa:24 3 1 MOV.L #xx:32, ERd 3 MOV.L ERs, ERd 1 MOV.
Appendix Instruction Branch Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic I J L M N MULXS MULXS.B Rs, Rd 2 12 MULXS.W Rs, ERd 2 20 MULXU MULXU.B Rs, Rd 1 12 MULXU.W Rs, ERd 1 20 NEG.B Rd 1 NEG.W Rd 1 NEG NEG.L ERd 1 NOP NOP 1 NOT NOT.B Rd 1 NOT.W Rd 1 NOT.L ERd 1 OR Stack K OR.B #xx:8, Rd 1 OR.B Rs, Rd 1 OR.W #xx:16, Rd 2 OR.W Rs, Rd 1 OR.L #xx:32, ERd 3 OR.
Appendix Instruction Branch Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic I J L M N ROTXR ROTXR.B Rd 1 ROTXR.W Rd 1 ROTXR.L ERd 1 RTE RTE 2 2 2 RTS RTS 2 1 2 SHAL SHAL.B Rd 1 SHAL.W Rd 1 SHAL.L ERd 1 SHAR.B Rd 1 SHAR.W Rd 1 SHAR.L ERd 1 SHAR SHLL SHLR SHLL.B Rd 1 SHLL.W Rd 1 SHLL.L ERd 1 SHLR.B Rd 1 SHLR.W Rd 1 Stack K SHLR.
Appendix Instruction Branch Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic I J K L M N SUBX SUBX #xx:8, Rd 1 1 2 SUBX. Rs, Rd 1 TRAPA TRAPA #xx:2 2 XOR XOR.B #xx:8, Rd 1 XOR.B Rs, Rd 1 XOR.W #xx:16, Rd 2 XOR.W Rs, Rd 1 XOR.L #xx:32, ERd 3 XOR.L ERs, ERd 2 XORC #xx:8, CCR 1 XORC Stack 4 Notes: 1. n: Specified value in R4L and R4. The source and destination operands are accessed n+1 times respectively. 2.
Appendix A.4 Combinations of Instructions and Addressing Modes Table A.5 Combinations of Instructions and Addressing Modes @@aa:8 — — — — — — — — — WL MOVFPE, — — — — — — — — — — — — — B BWL BWL @ERn Rn #xx — @(d:16.PC) — — @aa:24 — — BWL BWL BWL BWL BWL BWL @aa:16 — — MOV @aa:8 @(d:8.PC) @ERn+/@ERn @(d:24.ERn) — POP, PUSH Instructions Functions Data transfer instructions @(d:16.
Appendix B. I/O Port Block Diagrams B.1 I/O Port Block Diagrams RES goes low in a reset, and SBY goes low at a reset and in standby mode. Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR IRQ TRGV [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.1 Port 1 Block Diagram (P17) Rev. 1.50 Sep.
Appendix RES Internal data bus SBY PUCR Pull-up MOS PMR PDR PCR IRQ [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.2 Port 1 Block Diagram (P16, P14) Internal data bus RES SBY PUCR PMR PDR PCR IRQ TMIB1 [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.3 Port 1 Block Diagram (P15) Rev. 1.50 Sep.
Appendix Internal data bus RES SBY PUCR Pull-up MOS PDR PCR [Legend] PUCR: Port pull-up control register PDR: Port data register PCR: Port control register Figure B.4 Port 1 Block Diagram (P12) Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR 14-bit PWM PWM [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.5 Port 1 Block Diagram (P11) Rev. 1.50 Sep.
Appendix Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR RTC TMOW [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.6 Port 1 Block Diagram (P10) Internal data bus SBY PMR PDR PCR [Legend] PUCR: Port pull-up control register PDR: Port data register PCR: Port control register Figure B.7 Port 2 Block Diagram (P27, P26, P25, P24, P23) Rev. 1.50 Sep.
Appendix Internal data bus SBY PMR PDR PCR SCI3 TxD [Legend] PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.8 Port 2 Block Diagram (P22) SBY Internal data bus PDR PCR SCI3 RE RxD [Legend] PDR: Port data register PCR: Port control register Figure B.9 Port 2 Block Diagram (P21) Rev. 1.50 Sep.
Appendix SBY SCI3 SCKIE SCKOE Internal data bus PDR PCR SCKO SCKI [Legend] PDR: Port data register PCR: Port control register Figure B.10 Port 2 Block Diagram (P20) Internal data bus SBY PDR PCR [Legend] PDR: Port data register PCR: Port control register Figure B.11 Port 3 Block Diagram (P37, P36, P35, P34, P33, P32, P31, P30) Rev. 1.50 Sep.
Appendix Internal data bus SBY PMR PDR PCR IIC2 ICE SDAO/SCLO SDAI/SCLI [Legend] PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.12 Port5 Block Diagram (P57, P56) Internal data bus RES PUCR SBY Pull-up MOS PMR PDR PCR WKP [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.13 Port 5 Block Diagram (P55, P54, P53, P52, P51, P50) Rev. 1.50 Sep.
Appendix Internal data bus SBY PDR PCR [Legend] PDR: Port data register PCR: Port control register Figure B.14 Port 7 Block Diagram (P77) Internal data bus SBY Timer V OS3 OS2 OS1 OS0 PDR PCR TMOV [Legend] PDR: Port data register PCR: Port control register Figure B.15 Port 7 Block Diagram (P76) Rev. 1.50 Sep.
Appendix Internal data bus SBY PDR PCR Timer V TMCIV [Legend] PDR: Port data register PCR: Port control register Figure B.16 Port 7 Block Diagram (P75) Internal data bus SBY PDR PCR Timer V TMRIV [Legend] PDR: Port data register PCR: Port control register Figure B.17 Port 7 Block Diagram (P74) Rev. 1.50 Sep.
Appendix Internal data bus SBY PMR PDR PCR SCI3_2 TxD [Legend] PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.18 Port 7 Block Diagram (P72) SBY Internal data bus PDR PCR SCI3_2 RE RxD [Legend] PDR: Port data register PCR: Port control register Figure B.19 Port 7 Block Diagram (P71) Rev. 1.50 Sep.
Appendix SBY SCI3_2 SCKIE SCKOE Internal data bus PDR PCR SCKO SCKI [Legend] PDR: Port data register PCR: Port control register Figure B.20 Port 7 Block Diagram (P70) Internal data bus SBY PDR PCR [Legend] PDR: Port data register PCR: Port control register Figure B.21 Port 8 Block Diagram (P87, P86, P85) Rev. 1.50 Sep.
Appendix Internal data bus SBY PDR PCR [Legend] PDR: Port data register PCR: Port control register Figure B.22 Port C Block Diagram (PC3, PC2, PC1, PC0) Internal data bus SBY Timer RD_0 Output control signals A to D PDR PCR FTIOA to FTIOD [Legend] PDR: Port data register PCR: Port control register Figure B.23 Port D Block Diagram (PD7, PD6, PD5, PD4, PD3, PD2, PD1, PD0) Rev. 1.50 Sep.
Appendix Internal data bus SBY Timer RD_1 Output control signals A to D PDR PCR FTIOA to FTIOD [Legend] PDR: Port data register PCR: Port control register Figure B.24 Port E Block Diagram (PE7, PE6, PE5, PE4, PE3, PE2, PE1, PE0) Internal data bus A/D converter DEC CH3 to CH0 SCAN VIN Figure B.25 Port F Block Diagram (PF7, PF6, PF5, PF4, PF3, PF2, PF1, PF0) Rev. 1.50 Sep.
Appendix SBY Internal data bus PMR PDR PCR A/D converter SCAN CH3 to CH0 DEC VIN Timer RC, Timer RD TRCOI, TRDOI [Legend] PDR: Port data register PCR: Port control register PMR: Port mode register Figure B.26 Port G Block Diagram (PG7, PG6, PG5) Internal data bus SBY PDR PCR A/D converter SCAN CH3 to CH0 DEC VIN [Legend] PDR: Port data register PCR: Port control register Figure B.27 Port G Block Diagram (PG4, PG3, PG2, PG1, PG0) Rev. 1.50 Sep.
Appendix Internal data bus SBY Timer RC Output contorl signal A to D PDR PCR FTIOA to FTIOD TRGC [Legend] PDR: Port data register PCR: Port control register Figure B.28 Port H Block Diagram (PH7, PH6, PH5, PH4) Internal data bus SBY PDR PCR Timer RC FTCI [Legend] PDR: Port data register PCR: Port control register Figure B.29 Port H Block Diagram (PH3) Rev. 1.50 Sep.
Appendix Internal data bus SBY SMCR3 PDR PCR SCI3_3 TxD [Legend] SMCR3: Serial module control register 3 PDR: Port data register PCR: Port control register Figure B.30 Port H Block Diagram (PH2) SBY Internal data bus PDR PCR SCI3_3 RE RxD [Legend] PDR: Port data register PCR: Port control register Figure B.31 Port H Block Diagram (PH1) Rev. 1.50 Sep.
Appendix SBY SCI3_3 SCKIE SCKOE Internal data bus PMRG PDR PCR SCKO SCKI ADTRG [Legend] PMRG: Port mode register G PDR: Port data register PCR: Port control register Figure B.32 Port H Block Diagram (PH0) Internal data bus SBY CPG PDR φ PCR PMRJ1 PMRJ0 XTALI [Legend] PDR: Port data register PCR: Port control register Figure B.33 Port J Block Diagram (PJ1) Rev. 1.50 Sep.
Appendix SBY Internal data bus PDR PCR CPG PMRJ0 EXTALI [Legend] PDR: Port data register PCR: Port control register Figure B.34 Port J Block Diagram (PJ0) Rev. 1.50 Sep.
Appendix B.
Appendix C. Product Code Lineup Product Classification Product Code Model Marking Package (Code) H8/36109 Flash memory Standard version product HD64F36109F HD64F36109F QFP-100 (FP-100A) HD64F36109H HD64F36109H LQFP-100 (FP-100U) HD64F36109GF HD64F36109GF QFP-100 (FP-100A) HD64F36109GH HD64F36109GH LQFP-100 (FP-100U) Product with POR & LVDC D. Package Dimensions The package dimensions that are shown in the Renesas Semiconductor Packages Data Book have priority. Rev. 1.50 Sep.
100 e 1 ZD D y *3 bp 30 51 x 31 50 ZE M F E *2 81 80 *1 MASS[Typ.] 1.7g Detail F L1 L Terminal cross section b1 bp θ HE 0.30 L1 2.4 1.2 0.83 ZE L 0.58 ZD 1.4 0.15 10° 0.22 0.13 0.65 0.15 0.17 y 1.0 0° 0.12 x e θ c1 c b1 0.30 0.40 0.24 bp 0.32 3.10 0.00 A1 19.2 25.2 Max A 0.20 24.8 18.8 24.4 18.4 HD 14 2.70 E A2 20 Nom Dimension in Millimeters Min D Reference Symbol NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2.
Figure D.2 FP-100U Package Dimensions *1 100 76 ZD 1 75 e Index mark D y HD *3 bp 25 51 Previous Code x 26 50 100P6Q-A / FP-100U / FP-100UV F E *2 RENESAS Code HE PLQP0100KB-A 0.6g b1 bp c1 Detail F Terminal cross section MASS[Typ.] A JEITA Package Code A2 REJ09B0240-0150 ZE Rev. 1.50 Sep. 18, 2007 Page 572 of 584 A1 P-LQFP100-14x14-0.50 c L1 L 14.0 13.9 0.5 L 1.0 1.0 ZE L1 1.0 ZD 0.65 0.08 8° 0.08 0.5 0.20 0.25 0.15 1.7 16.2 16.2 14.1 y 0.
Main Revisions and Additions in this Edition Item Page Revisions (See Manual for Details) Section 5 Clock Pulse Generators 76 5.2.4 Clock Control/Status Register (CKCSR) Amended Bit Bit Name Description 7 PMRJ1 OSC Pin Function Select 1 and 0 6 PMRJ0 PMRJ1 PMRJ0 OSC2 OSC1 0 I/O 0 I/O 1 0 CLKOUT I/O 0 1 Hi-Z OSC1 (external clock input) 1 Section 14 Timer RD 346 1 OSC2 OSC1 Amended Figure 14.
Item Page Revisions (See Manual for Details) 2 Section 18 I C Bus Interface 2 (IIC2) 434 Figure 18.15 Receive Mode Operation Timing Section 19 A/D Converter 457 Amended SCL 7 8 1 2 SDA (Input) Bit 6 Bit 7 Bit 0 Bit 1 Added 19.6.3 Notes on Analog Pins Section 23 Electrical Characteristics 497 to Amended 520 The wide temperature range of Ta = –40 to +85°C is added to the conditions. Rev. 1.50 Sep.
Item Page Revisions (See Manual for Details) Table 23.2 DC Characteristics (1) 503, 505, 506 Added Values Item Test Condition Min. Output high voltage 3.0 V ≤ VCC < 4.0 V –IOH = 0.1 mA VCC – 2.2 Active mode Active mode 1 supply current VCC = 5.0 V, fOSC = 20 MHz 33.0 40.0 mA * Active mode 1 VCC = 3.0 V, fOSC = 10 MHz 15.0 * Reference value Active mode 2 VCC = 5.0 V, fOSC = 20 MHz 6.0 7.5 Active mode 2 VCC = 3.0 V, fOSC = 10 MHz 4.
Item Page Revisions (See Manual for Details) Table 23.2 DC Characteristics (2) 507 Amended Values Item Applicable Pins Min. Typ. Max. Unit Allowable output low Port G 0.4 mA Port G 3.2 mA Port G 0.2 mA Port G 1.6 mA current (per pin) Allowable output low current (total) Allowable output high current (per pin) Allowable output high current (total) Rev. 1.50 Sep.
Item Page Revisions (See Manual for Details) Table 23.3 AC Characteristics 510, 511 Amended Values Item Test Condition Min. Typ. Max. Unit On-chip oscillator oscillation frequency Vcc = 4.0 to 5.5V 39.40 40.00 40.60 MHz 39.20 40.00 40.80 MHz 38.80 40.00 41.20 MHz 38.40 40.00 41.60 MHz 38.40 40.00 41.60 MHz 38.00 40.00 42.00 MHz 31.52 32.00 32.48 MHz 31.36 32.00 32.64 MHz 31.04 32.00 32.96 MHz 30.72 32.00 33.28 MHz 30.72 32.00 33.28 MHz 30.40 32.
Item Page Revisions (See Manual for Details) Table 23.9 Power-Supply-Voltage 517 Detection Circuit Characteristics Amended Values Item Symbol Test Condition Min. Typ. Max. Unit Power-supply Vint (D) LVDSEL = 0 3.5 3.7 V Power-supply rising Vint (U) LVDSEL = 0 4.1 4.3 V Vreset1 LVDSEL = 0 2.3 2.6 V Vreset2 LVDSEL = 1 3.3 3.6 3.9 V 1.
Index Numerics CPU........................................................... 11 14-bit PWM ............................................ 365 D A A/D converter ......................................... 443 Absolute address....................................... 32 Acknowledge .......................................... 423 Address break ........................................... 65 Addressing modes..................................... 31 Arithmetic operations instructions............
I2C Bus format ........................................ 423 I2C bus interface 2 (IIC2) ....................... 407 Immediate ................................................. 33 Initial setting procedure .......................... 195 Input capture function............................. 312 Instruction list......................................... 521 Instruction set ........................................... 20 Internal interrupts .....................................
Register states in each operating mode... 489 Registers ABRKCR...................... 66, 479, 487, 494 ABRKSR ...................... 68, 479, 487, 494 ADCR ......................... 449, 473, 483, 490 ADCSR....................... 447, 473, 483, 490 ADDR......................... 446, 473, 483, 490 BARE ........................... 68, 479, 487, 494 BARH ........................... 68, 479, 487, 494 BARL ........................... 68, 479, 487, 494 BDRH ........................... 68, 479, 487, 494 BDRL .....
RCCR ............................73, 477, 485, 493 RCTRMDPR .................74, 477, 485, 493 RCTRMDR....................75, 477, 485, 493 RDR.............................373, 479, 487, 494 RHRDR .......................190, 477, 485, 492 RMINDR .....................189, 477, 485, 492 RSECDR......................188, 477, 485, 492 RSR .................................................... 373 RTCCR1 ......................192, 477, 485, 492 RTCCR2 ......................193, 477, 485, 492 RTCCSR................
Synchronous operation ........................... 315 System control instructions....................... 28 Trap instruction......................................... 45 Trimming .................................................. 82 T W Timer B1................................................. 199 Timer RC ................................................ 217 Timer RD................................................ 265 Timer V .................................................. 203 Transfer rate...........
Rev. 1.50 Sep.
Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8/36109 Group Publication Date: Rev.1.00, Jan. 25, 2006 Rev.1.50, Sep. 18, 2007 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. 2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES http://www.renesas.com Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
H8/36109 Group Hardware Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0240-0150
