Datasheet

Section 5 Clock Pulse Generators
Rev. 1.50 Sep. 18, 2007 Page 71 of 584
REJ09B0240-0150
Section 5 Clock Pulse Generators
The clock pulse generator consists of a system clock generating circuitry, a subclock generating
circuitry, and two prescalers. The system clock generating circuitry includes a system clock
oscillator, a duty correction circuit, an on-chip oscillator, an on-chip oscillator divider, a clock
select circuit, and a system clock divider. The subclock generating circuitry includes a subclock
oscillator and a subclock divider.
Figure 5.1 shows a block diagram of the clock pulse generator.
System
clock
oscillator
Subclock
oscillator
Subclock
divider
Duty
correction
circuit
System
clock
divider
Prescaler S
(13 bits)
Prescaler W
(5 bits)
OSC1
OSC2
X1
X2
System clock generating circuitry
φ
OSC
φ
OSC
φ
W
(φ
W
)
φ
W
/2
φ
W
/4
φ
SUB
φ/2
to
φ/8192
φ
W
/8
φ
φ/8
φ
φ/16
φ/32
φ/64
φ
W
/8
to
φ
W
/128
Subclock pulse generating circuitry
Clock
sekect
circuit
On-chip
oscillator
On-chip
oscillator
divider
R
OSC
R
OSC
/2
R
OSC
/4
φ
RC
R
OSC
/8
To timer RC and
timer RD
φ
40M
Figure 5.1 Block Diagram of Clock Pulse Generators
The system clock (φ) and subclock (φ
SUB
) are basic clocks on which the CPU and on-chip
peripheral modules operate. The system clock is divided by a value from 2 to 8192 in prescaler S,
and the subclock is divided by a value from 8 to 128 in prescaler W. These divided clocks are
supplied to respective on-chip peripheral modules. The on-chip oscillator can generate system
clock φ
RC
, which is produced by dividing R
OSC
by 2, 4, or 8, and the φ
40M
clock supplied to timer RC
and timer RD.