Datasheet

Section 5 Clock Pulse Generators
Rev. 1.50 Sep. 18, 2007 Page 80 of 584
REJ09B0240-0150
5.3.3 Clock Change Timing
The timing for changing clocks are shown in figures 5.5 and 5.6.
[Legend]
φ
OSC
: External clock
φ
RC
: Internal RC clock
φ: System clock
OSCSEL: Bit 4 in CKCSR
PHISTOP: System clock stop control signal
CKSTA: Bit 0 in CKCSR
Wait for external
oscillation settling
φ halt*
External clock operation
Note: * The φ halt duration is the duration from the timing when the φ clock stops to the first
rising edge of the φ
OSC
clock after seven clock cycles of the φ
RC
clock have elapsed.
φ
OSC
N wait
φ
RC
PHISTOP
(Internal signal)
φ
OSCSEL
CKSTA
Internal RC clock operation
Figure 5.5 Timing Chart of Switching from On-Chip Oscillator Clock to External Clock