Datasheet

Section 5 Clock Pulse Generators
Rev. 1.50 Sep. 18, 2007 Page 81 of 584
REJ09B0240-0150
[Legend]
φ
OSC
: External clock
φ
RC
: Internal RC clock
φ: System clock
OSCSEL: Bit 4 in CKCSR
PHISTOP: System clock stop control signal
CKSTA: Bit 0 in CKCSR
CKSWIF: Bit 2 in CKCSR
φ halt*
External clock
operation
Note: * The φ halt duration is the duration from the timing when the φ clock stops to the
seventh rising edge of the φ
RC
clock.
φ
OSC
φ
RC
PHISTOP
(Internal signal)
φ
OSCSEL
CKSTA
External RC clock operation
CKSWIF
Figure 5.6 Timing Chart to Switch from External Clock to On-Chip Oscillator Clock