Datasheet

Rev. 1.50 Sep. 18, 2007 Page x of xxxiv
3.2.4 Interrupt Enable Register 2 (IENR2) ...................................................................... 51
3.2.5 Interrupt Flag Register 1 (IRR1)............................................................................. 51
3.2.6 Interrupt Flag Register 2 (IRR2)............................................................................. 53
3.2.7 Wakeup Interrupt Flag Register (IWPR) ................................................................ 53
3.2.8 Interrupt Control Registers A to D (ICRA to ICRD).............................................. 55
3.3 Reset Exception Handling.................................................................................................... 56
3.4 Interrupt Exception Handling .............................................................................................. 56
3.4.1 External Interrupts .................................................................................................. 56
3.4.2 Internal Interrupts ................................................................................................... 58
3.4.3 Interrupt Handling Sequence .................................................................................. 58
3.4.4 Interrupt Response Time......................................................................................... 62
3.5 Usage Notes ......................................................................................................................... 63
3.5.1 Interrupts after Reset............................................................................................... 63
3.5.2 Notes on Stack Area Use ........................................................................................ 63
3.5.3 Notes on Rewriting Port Mode Registers ............................................................... 63
Section 4 Address Break .....................................................................................65
4.1 Register Descriptions...........................................................................................................66
4.1.1 Address Break Control Register (ABRKCR) ......................................................... 66
4.1.2 Address Break Status Register (ABRKSR) ............................................................ 68
4.1.3 Break Address Registers E, H, L (BARE, BARH, BARL) .................................... 68
4.1.4 Break Data Registers H, L (BDRH, BDRL)........................................................... 68
4.2 Operation ............................................................................................................................. 69
Section 5 Clock Pulse Generators ....................................................................... 71
5.1 Features................................................................................................................................ 72
5.2 Register Descriptions...........................................................................................................72
5.2.1 RC Control Register (RCCR) ................................................................................. 73
5.2.2 RC Trimming Data Protect Register (RCTRMDPR).............................................. 74
5.2.3 RC Trimming Data Register (RCTRMDR)............................................................ 75
5.2.4 Clock Control/Status Register (CKCSR)................................................................ 76
5.3 System Clock Oscillator ...................................................................................................... 77
5.3.1 State Transition of System Clock ........................................................................... 77
5.3.2 Clock Control Operation......................................................................................... 78
5.3.3 Clock Change Timing............................................................................................. 80
5.4 Trimming of On-Chip Oscillator Frequency........................................................................ 82
5.5 External Oscillator ............................................................................................................... 84
5.5.1 Connecting Crystal Resonator ................................................................................ 84
5.5.2 Connecting Ceramic Resonator .............................................................................. 85
5.5.3 External Clock Input Method ................................................................................. 85