Datasheet

Section 6 Power-Down Modes
Rev. 1.50 Sep. 18, 2007 Page 91 of 584
REJ09B0240-0150
Bit Bit Name
Initial
Value R/W Description
6
5
4
STS2
STS1
STS0
0
0
0
R/W
R/W
R/W
Standby Timer Select 2 to 0
These bits specify the waiting time in number of cycles
until clocks are supplied after the system clock
oscillator starts oscillation when making a transition
from the standby, subactive, or subsleep mode to the
active or sleep mode. The number of cycles for the
waiting time should be specified so that the waiting
time is 6.5 ms or more when the external oscillator is
used as the system clock source after the transition.
The waiting time should be 100 µs or more when the
on-chip oscillator is used as the system clock source
after the transition. The relationship between the
setting and the number of cycles is shown in table 6.1.
A clock used for counting the number of cycles is not
divided regardless of the setting in bits MA2 to MA0 in
SYSCR2. When the system clock source after a
transition is the external oscillator or on-chip oscillator,
the φ
OSC
or φRC clock is used for counting, respectively.
These bits also specify the waiting time until the
external oscillator settles when system clock sources
are switched from the on-chip oscillator to the external
clock by user software. The relationship of waiting
times between the above transition and clock switching
is shown below. The number of cycles for external
oscillator settling should be specified so that the Nstby
value multiplied by the external oscillator frequency is
6.5 ms or more. In this case, a clock used for counting
the number of cycles is the φ
RC
clock divided by the
setting in bits MA2 to MA0 in SYSCR2.
Nstby ≤ Nwait ≤ 2 × Nstby
Nwait: The number of waiting cycles for external
oscillator settling
Nstby: The number of waiting cycles when returning
from a standby mode