Datasheet

Section 6 Power-Down Modes
Rev. 1.50 Sep. 18, 2007 Page 92 of 584
REJ09B0240-0150
Bit Bit Name
Initial
Value R/W Description
3 NESEL 0 R/W Noise Elimination Sampling Frequency Select
This bit selects the clock frequency to sample the
watch clock signal (φ
W
) generated by the subclock
oscillator. The oscillator clock (φ
OSC
) generated by the
system clock oscillator or the φ
RC
clock generated by
the on-chip oscillator can be used as the sampling
clock source. When φ
OSC
or φ
RC
= 4 to 20 MHz, set this
bit to 0.
0: Sampling rate is φ
OSC
/16 or φ
RC
/16
1: Sampling rate is φ
OSC
/4 or φ
RC
/4
2 to 0  All 0  Reserved
These bits are always read as 0.
Table 6.1 Operating Frequency and Waiting Time
Bit Name Operating Frequency
STS3 STS2 STS1 STS0
Cycle Count
for Waiting
Time
20 MHz 16 MHz 10 MHz 8 MHz 4 MHz 2 MHz 1 MHz 0.5 MHz
x 0 0 0 8,192 cycles 0.4 0.5 0.8 1.0 2.0 4.1 8.1 16.4
x 0 0 1 16,384 cycles 0.8 1.0 1.6 2.0 4.1 8.2 16.4 32.8
x 0 1 0 32,768 cycles 1.6 2.0 3.3 4.1 8.2 16.4 32.8 65.5
x 0 1 1 65,536 cycles 3.3 4.1 6.6 8.2 16.4 32.8 65.5 131.1
x 1 0 0 131,072 cycles 6.6 8.2 13.1 16.4 32.8 65.5 131.1 262.1
1 1 0 1 1,024 cycles 0.05 0.06 0.10 0.13 0.26 0.51 1.02 2.05
1 1 1 0 128 cycles 0.00 0.00 0.01 0.02 0.03 0.06 0.13 0.26
1 1 1 1 16 cycles 0.00 0.00 0.00 0.00 0.00 0.00 0.02 0.03
0 1 0 1 4,096 cycles 0.20 0.25 0.40 0.51 1.02 2.05 4.01 8.19
0 1 1 0 2,048 cycles 0.10 0.13 0.20 0.26 0.51 1.02 2.05 4.01
0 1 1 1 512 cycles 0.02 0.03 0.05 0.06 0.13 0.26 0.51 1.02
[Legend]
x: Don't care
Note: Time unit is ms.