Datasheet

Section 6 Power-Down Modes
Rev. 1.50 Sep. 18, 2007 Page 100 of 584
REJ09B0240-0150
6.2.1 Sleep Mode
In sleep mode, CPU operation is halted but the on-chip peripheral modules function at the clock
frequency set by the MA2, MA1, and MA0 bits in SYSCR2. CPU register contents are retained.
When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts.
Sleep mode is not cleared if the I bit of the condition code register (CCR) is set to 1 or the
requested interrupt is disabled in the interrupt enable register. After sleep mode is cleared, a
transition is made to active mode when the LSON bit in SYSCR2 is 0, and a transition is made to
subactive mode when the bit is 1. When the RES pin goes low, the CPU goes into the reset state
and sleep mode is cleared.
6.2.2 Standby Mode
In standby mode, the system clock oscillator stops, so the CPU and on-chip peripheral modules
stop functioning. However, as long as the rated voltage is supplied, the contents of CPU registers,
on-chip RAM, and some on-chip peripheral module registers are retained. On-chip RAM contents
will be retained as long as the voltage set by the RAM data retention voltage is provided. The I/O
ports go to the high-impedance state.
The standby mode is cleared by an interrupt. When an interrupt is requested, the system clock
oscillator starts. After the time set in bits STS2 to STS0 in SYSCR1 and bit STS3 in SYSCR3 has
elapsed, the standby mode is lifted and the interrupt exception handling starts. The standby mode
is not lifted if the I bit in CCR is set to 1 or the requested interrupt is disabled in the interrupt
enable register.
When the RES signal goes low, the on-chip oscillator starts oscillation. Since clock signals are
supplied to the entire chip as soon as the on-chip oscillator starts oscillation, the RES signal must
be kept low over a given time. After the given time, the CPU starts the reset exception handling
when the RES signal is driven high.