Datasheet

Section 6 Power-Down Modes
Rev. 1.50 Sep. 18, 2007 Page 101 of 584
REJ09B0240-0150
6.2.3 Subsleep Mode
In subsleep mode, operation of the CPU and on-chip peripheral modules other than the RTC is
halted. As long as a required voltage is applied, the contents of CPU registers, the on-chip RAM,
and some registers of the on-chip peripheral modules are retained. I/O ports keep the same states
as before the transition.
The subsleep mode is lifted by an interrupt. When an interrupt is requested, the subsleep mode is
lifted and the interrupt exception handling starts. The subsleep mode is not lifted if the I bit in
CCR is set to 1 or the requested interrupt is disabled in the interrupt enable register. The mode
after the subsleep mode is lifted, a transition is made to the active mode or subactive mode
according to the LSON bit in SYSCR2 is 0. After the time set in bits STS2 to STS0 in SYSCR1
and bit STS3 in SYSCR has elapsed, a transition is made to active mode.
When the RES signal goes low, the on-chip oscillator starts oscillation. Since clock signals are
supplied to the entire chip as soon as the on-chip oscillator starts oscillation, the RES signal must
be kept low over a given time. After the given time, the CPU starts the reset exception handling
when the RES signal is driven high.
6.2.4 Subactive Mode
The operating frequency in subactive mode is selected from φ
W
/2, φ
W
/4, and φ
W
/8 by the SA1 and
SA0 bits in SYSCR2. After the SLEEP instruction is executed, the operating frequency changes to
the frequency which is set before the execution.
When the SLEEP instruction is executed in subactive mode, a transition to sleep mode, subsleep
mode, standby mode, active mode, or subactive mode is made, depending on the combination of
SYSCR1 and SYSCR2.
When the RES signal goes low, the on-chip oscillator starts oscillation. Since clock signals are
supplied to the entire chip as soon as the on-chip oscillator starts oscillation, the RES signal must
be kept low over a given time. After the given time, the CPU starts the reset exception handling
when the RES signal is driven high.
6.3 Operating Frequency in Active Mode
This LSI operates in active mode at the frequency specified by bits MA2, MA1, and MA0 in
SYSCR2. The operating frequency changes to the set frequency after the SLEEP instruction
execution.