Datasheet

Section 6 Power-Down Modes
Rev. 1.50 Sep. 18, 2007 Page 103 of 584
REJ09B0240-0150
6.4.2 Direct Transition from Subactive Mode to Active Mode
The time from the start of the SLEEP instruction execution to the end of the interrupt exception
handling (the direct transition time) is calculated by equation (2).
Direct transition time = {(number of SLEEP instruction execution cycles) + (number of internal
processing cycles)} × (tsubcyc before transition) + {(waiting time set in bits STS2 to STS0) +
(number of interrupt exception handling cycles)} × (t
cyc
after transition) …. (2)
Example 1: Case when the CPU operating clock changes from φ
w
/8 to φ
osc
, and a waiting time of
32768 cycles is set
Direct transition time = (2 + 1) × 8 t
w
+ (32768 + 16) × t
OSC
= 24 t
w
+ 32784 t
OSC
Example 2: Case when the CPU operating clock changes from φ
w
/4 to Rosc/2, and a waiting time
of 4096 cycles is set
Direct transition time = (2 + 1) × 4 t
w
+ (4096 + 16) × t
ROSC
= 12 t
w
+ 8224 t
OSC
[Legend]
t
OSC
: OSC clock cycle time
t
ROSC
: Period of oscillation of the on-chip oscillator
t
W
: Watch clock cycle time
tcyc: System clock (φ) cycle time
tsubcyc: Subclock (φ
SUB
) cycle time
6.5 Module Standby Function
The module-standby function can be set to any peripheral module. In the module standby state, the
clock supply to modules stops to enter the power-down mode. Setting a bit in MSTCR1,
MSTCR2, MSTCR4, or SMCR that corresponds to each module to 1 enables each on-chip
peripheral module to enter the module standby state and the module standby state is canceled by
clearing the bit to 0.