Datasheet

Section 7 ROM
Rev. 1.50 Sep. 18, 2007 Page 116 of 584
REJ09B0240-0150
8. The maximum number of repetitions of the programming/program-verify sequence of the
same bit is 1,000.
Note: * The RTS instruction must not be used during the following 1. and 2. periods.
1. A period between 128-byte data programming to flash memory and the P bit clearing
2. A period between dummy writing of H'FF to a verify address and verify data reading
No
Yes
No
Yes
No
No
Yes
Yes
Yes
No
Yes
No
Yes
*
Write pulse application subroutine
Apply Write Pulse
START
*
End Sub
End of programming
Set PSU bit in FLMCR1
WDT enable
Set SWE bit in FLMCR1
Wait 1 µs
Store 128-byte program data
in program data area and
reprogram data area
n = 1
m = 0
Write 128-byte data in RAM
reprogram data area consecutively
to flash memory
Apply Write pulse
Set PV bit in FLMCR1
Wait 4 µs
Set block start address as
verify address
H'FF dummy write to verify address
Wait 2 µs
Read verify data
Additional-programming
data computation
Reprogram data computation
Clear PV bit in FLMCR1
Wait 2 µs
Successively write 128-byte data
from additional-programming data
area in RAM to flash memory
Clear SWE bit in FLMCR1
Wait 100 µs
Apply Write Pulse
Verify data =
write data?
n ≤ 6 ?
128-byte
data verification
completed?
n ≤ 6?
m= 0 ?
Programming failure
Clear SWE bit in FLMCR1
Wait 100 µs
n ≤ 1000 ?
Disable WDT
Wait 50 µs
Set P bit in FLMCR1
Wait (Wait time = programming time)
Clear P bit in FLMCR1
Wait 5 µs
Clear PSU bit in FLMCR1
Wait 5 µs
m = 1
Increment address
n ← n + 1
Sub-Routine-Call
Figure 7.3 Programming/Program-Verify Flowchart