Datasheet

Section 9 I/O Ports
Rev. 1.50 Sep. 18, 2007 Page 138 of 584
REJ09B0240-0150
• P30 pin
Register PCR3
Bit Name PCR30 Pin Function
Setting Value 0 P30 input pin
1 P30 output pin
9.4 Port 5
Port 5 is a general I/O port also functioning as an I
2
C bus interface I/O pin and a wakeup interrupt
input pin. Each pin of port 5 is shown in figure 9.4. The register setting of the I
2
C bus interface has
priority for functions of the pins P57/SCL and P56/SDA. Since the output buffer for pins P56 and
P57 has the NMOS push-pull structure, it differs from an output buffer with the CMOS structure
in the high-level output characteristics (see section 23, Electrical Characteristics).
P55/WKP
5
P56/SDA
P57/SCL
P50/WKP
0
P54/WKP
4
P53/WKP
3
P52/WKP
2
P51/WKP
1
Port 5
Figure 9.4 Port 5 Pin Configuration
Port 5 has the following registers.
• Port mode register 5 (PMR5)
• Port control register 5 (PCR5)
• Port data register 5 (PDR5)
• Port pull-up control register 5 (PUCR5)