Datasheet

Rev. 1.50 Sep. 18, 2007 Page xvii of xxxiv
Section 16 14-Bit PWM.....................................................................................365
16.1 Features.............................................................................................................................. 365
16.2 Input/Output Pin................................................................................................................. 365
16.3 Register Descriptions......................................................................................................... 366
16.3.1 PWM Control Register (PWCR) .......................................................................... 366
16.3.2 PWM Data Registers U, L (PWDRU, PWDRL) .................................................. 367
16.4 Operation ........................................................................................................................... 367
Section 17 Serial Communication Interface 3 (SCI3) .......................................369
17.1 Features.............................................................................................................................. 369
17.2 Input/Output Pins...............................................................................................................372
17.3 Register Descriptions......................................................................................................... 373
17.3.1 Receive Shift Register (RSR) ............................................................................... 373
17.3.2 Receive Data Register (RDR)............................................................................... 373
17.3.3 Transmit Shift Register (TSR) .............................................................................. 373
17.3.4 Transmit Data Register (TDR).............................................................................. 374
17.3.5 Serial Mode Register (SMR) ................................................................................ 374
17.3.6 Serial Control Register 3 (SCR3).......................................................................... 375
17.3.7 Serial Status Register (SSR) ................................................................................. 377
17.3.8 Bit Rate Register (BRR) ....................................................................................... 379
17.4 Operation in Asynchronous Mode ..................................................................................... 383
17.4.1 Clock..................................................................................................................... 383
17.4.2 SCI3 Initialization................................................................................................. 384
17.4.3 Data Transmission ................................................................................................ 385
17.4.4 Serial Data Reception ........................................................................................... 387
17.5 Operation in Clock Synchronous Mode............................................................................. 391
17.5.1 Clock..................................................................................................................... 391
17.5.2 SCI3 Initialization................................................................................................. 391
17.5.3 Serial Data Transmission ...................................................................................... 392
17.5.4 Serial Data Reception (Clock Synchronous Mode) .............................................. 394
17.5.5 Simultaneous Serial Data Transmission and Reception........................................ 396
17.6 Multiprocessor Communication Function.......................................................................... 397
17.6.1 Multiprocessor Serial Data Transmission ............................................................. 399
17.6.2 Multiprocessor Serial Data Reception .................................................................. 400
17.7 Interrupt Requests ..............................................................................................................403
17.8 Usage Notes ....................................................................................................................... 404
17.8.1 Break Detection and Processing ........................................................................... 404
17.8.2 Mark State and Break Sending.............................................................................. 404