Datasheet

Rev. 1.50 Sep. 18, 2007 Page xviii of xxxiv
17.8.3 Receive Error Flags and Transmit Operations
(Clock Synchronous Mode Only) ......................................................................... 404
17.8.4 Receive Data Sampling Timing and Reception Margin in Asynchronous
Mode..................................................................................................................... 405
Section 18 I
2
C Bus Interface 2 (IIC2)................................................................ 407
18.1 Features.............................................................................................................................. 407
18.2 Input/Output Pins...............................................................................................................409
18.3 Register Descriptions......................................................................................................... 410
18.3.1 I
2
C Bus Control Register 1 (ICCR1)..................................................................... 410
18.3.2 I
2
C Bus Control Register 2 (ICCR2)..................................................................... 413
18.3.3 I
2
C Bus Mode Register (ICMR)............................................................................ 415
18.3.4 I
2
C Bus Interrupt Enable Register (ICIER)........................................................... 417
18.3.5 I
2
C Bus Status Register (ICSR)............................................................................. 419
18.3.6 Slave Address Register (SAR).............................................................................. 421
18.3.7 I
2
C Bus Transmit Data Register (ICDRT) ............................................................ 422
18.3.8 I
2
C Bus Receive Data Register (ICDRR).............................................................. 422
18.3.9 I
2
C Bus Shift Register (ICDRS)............................................................................ 422
18.4 Operation ........................................................................................................................... 423
18.4.1 I
2
C Bus Format...................................................................................................... 423
18.4.2 Master Transmit Operation................................................................................... 424
18.4.3 Master Receive Operation .................................................................................... 426
18.4.4 Slave Transmit Operation ..................................................................................... 428
18.4.5 Slave Receive Operation....................................................................................... 431
18.4.6 Clocked Synchronous Serial Format .................................................................... 432
18.4.7 Noise Canceller..................................................................................................... 435
18.4.8 Example of Use..................................................................................................... 435
18.5 Interrupts............................................................................................................................ 440
18.6 Bit Synchronous Circuit..................................................................................................... 441
Section 19 A/D Converter ................................................................................. 443
19.1 Features.............................................................................................................................. 443
19.2 Input/Output Pins...............................................................................................................445
19.3 Register Descriptions......................................................................................................... 446
19.3.1 A/D Data Registers A to D (ADDRA to ADDRD) .............................................. 446
19.3.2 A/D Control/Status Register (ADCSR) ................................................................ 447
19.3.3 A/D Control Register (ADCR) ............................................................................. 449
19.4 Operation ........................................................................................................................... 450
19.4.1 Single Mode.......................................................................................................... 450
19.4.2 Scan Mode ............................................................................................................ 450