Datasheet

Rev. 1.50 Sep. 18, 2007 Page xxi of xxxiv
Figures
Section 1 Overview
Figure 1.1 Internal Block Diagram .................................................................................................3
Figure 1.2 Pin Assignments (FP-100A)..........................................................................................4
Figure 1.3 Pin Assignments (FP-100U)..........................................................................................5
Section 2 CPU
Figure 2.1 Memory Map...............................................................................................................12
Figure 2.2 CPU Registers ............................................................................................................. 13
Figure 2.3 Usage of General Registers .........................................................................................14
Figure 2.4 Relationship between Stack Pointer and Stack Area................................................... 15
Figure 2.5 General Register Data Formats (1).............................................................................. 17
Figure 2.5 General Register Data Formats (2).............................................................................. 18
Figure 2.6 Memory Data Formats.................................................................................................19
Figure 2.7 Instruction Formats......................................................................................................30
Figure 2.8 Branch Address Specification in Memory Indirect Mode ........................................... 33
Figure 2.9 On-Chip Memory Access Cycle.................................................................................. 36
Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)..................................... 37
Figure 2.11 CPU Operation States................................................................................................ 38
Figure 2.12 State Transitions........................................................................................................39
Figure 2.13 Example of Timer Configuration with Two Registers Allocated to Same
Address......................................................................................................................40
Section 3 Exception Handling
Figure 3.1 Reset Sequence............................................................................................................ 57
Figure 3.2 Interrupt Acceptance Flowchart .................................................................................. 59
Figure 3.3 Stack Status after Exception Handling ........................................................................60
Figure 3.4 Interrupt Sequence....................................................................................................... 61
Figure 3.5 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure .............. 63
Section 4 Address Break
Figure 4.1 Block Diagram of Address Break................................................................................ 65
Figure 4.2 Address Break Interrupt Operation Example (1)......................................................... 69
Figure 4.2 Address Break Interrupt Operation Example (2)......................................................... 70
Section 5 Clock Pulse Generators
Figure 5.1 Block Diagram of Clock Pulse Generators.................................................................. 71
Figure 5.2 State Transition of System Clock ................................................................................77
Figure 5.3 Flowchart of Clock Switching
(From On-Chip Oscillator Clock to External Clock)................................................... 78