Datasheet

Rev. 1.50 Sep. 18, 2007 Page xxiv of xxxiv
Figure 13.17 Example (1) of TRGC Synchronous Operation in PWM2 Mode.......................... 250
Figure 13.18 Example (2) of TRGC Synchronous Operation in PWM2 Mode.......................... 250
Figure 13.19 Example of Stopping Operation of the Counter in PWM2 Mode ......................... 251
Figure 13.20 Example (1) of Output Operation of One-Shot Pulse Waveform in PWM2
Mode ..................................................................................................................... 251
Figure 13.21 Example (2) of Output Operation of One-Shot Pulse Waveform in PWM2
Mode ..................................................................................................................... 252
Figure 13.22 Block Diagram of Digital Filter ............................................................................ 253
Figure 13.23 Count Timing for Internal Clock Source............................................................... 254
Figure 13.24 Count Timing for External Clock Source.............................................................. 254
Figure 13.25 Output Compare Output Timing ........................................................................... 255
Figure 13.26 Input Capture Input Signal Timing........................................................................ 256
Figure 13.27 Timing of Counter Clearing by Compare Match................................................... 256
Figure 13.28 Buffer Operation Timing (Compare Match) ......................................................... 257
Figure 13.29 Buffer Operation Timing (Input Capture) ............................................................. 257
Figure 13.30 Timing of IMFA to IMFD Flag Setting at Compare Match.................................. 258
Figure 13.31 Timing of IMFA to IMFD Flag Setting at Input Capture...................................... 259
Figure 13.32 Timing of Status Flag Clearing by CPU................................................................ 260
Figure 13.33 Contention between TRCCNT Write and Clear.................................................... 261
Figure 13.34 Internal Clock Switching and TRCCNT Operation............................................... 262
Figure 13.35 When Compare Match and Bit Manipulation Instruction to TRCCR1 Occur
at the Same Timing ............................................................................................... 263
Section 14 Timer RD
Figure 14.1 Timer RD Block Diagram ....................................................................................... 269
Figure 14.2 Timer RD (Channel 0) Block Diagram ................................................................... 270
Figure 14.3 Timer RD (Channel 1) Block Diagram ................................................................... 271
Figure 14.4 Example (1) of Stopping Operation of the Counter (in PWM3 Mode) ................... 276
Figure 14.5 Example (2) of Stopping Operation of the Counter (in PWM3 Mode) ................... 276
Figure 14.6 Example of Starting and Stopping Operations of Counters (in PWM3 Mode) ....... 277
Figure 14.7 Example of Outputs in Reset Synchronous PWM Mode and Complementary
PWM Mode ............................................................................................................. 282
Figure 14.8 Accessing Operation of 16-Bit Register
(between CPU and TRDCNT (16 bits)) .................................................................. 299
Figure 14.9 Accessing Operation of 8-Bit Register (between CPU and TRDSTR (8 bits))....... 299
Figure 14.10 Example of Counter Operation Setting Procedure ................................................ 306
Figure 14.11 Free-Running Counter Operation .......................................................................... 307
Figure 14.12 Periodic Counter Operation................................................................................... 308
Figure 14.13 Count Timing at Internal Clock Operation............................................................ 308
Figure 14.14 Count Timing at External Clock Operation (Both Edges Detected)...................... 309
Figure 14.15 Example of Setting Procedure for Waveform Output by Compare Match............ 309