Datasheet

Section 13 Timer RC
Rev. 1.50 Sep. 18, 2007 Page 225 of 584
REJ09B0240-0150
Bit Bit Name
Initial
Value R/W Description
1 TOB 0 R/W Timer Output Level Setting B
Sets the output value of the FTIOB pin until the first
compare match B is generated. In PWM mode, controls
the output polarity of the FTIOB pin.
0: Output value is 0*
1: Output value is 1*
0 TOA 0 R/W Timer Output Level Setting A
Sets the output value of the FTIOA pin until the first
compare match A is generated.
0: Output value is 0*
1: Output value is 1*
[Legend]
X: Don't care.
Note: * The change of the setting is immediately reflected in the output value.
13.3.3 Timer RC Control Register 2 (TRCCR2)
TRCCR2 specifies the edge of the TRGC signal and an input enable.
Bit Bit Name
Initial
Value R/W Description
7
6
TCEG1
TCEG0
0
0
R/W
R/W
TRGC Input Edge Select
These bits select the input edge of the TRGC signal. This
function is only enabled when the PWM2 bit in TRCMR is
set to 0.
00: A trigger input on TRGC is disabled
01: The rising edge is selected
10: The falling edge is selected
11: Both edges are selected
5 CSTP 0 R/W Specifies whether TRCCNT counting up is halted or
continued by the compare match A signal. This function is
only enabled when the PWM2 bit in TRCMR is set to 0.
0: TRCCNT counting up is continued
1: TRCCNT counting up is halted
4 to 0  All 1  Reserved
These bits are always read as 1.