Datasheet

Section 13 Timer RC
Rev. 1.50 Sep. 18, 2007 Page 226 of 584
REJ09B0240-0150
13.3.4 Timer RC Interrupt Enable Register (TRCIER)
TRCIER controls the timer RC interrupt request.
Bit Bit Name
Initial
Value R/W Description
7 OVIE 0 R/W Timer Overflow Interrupt Enable
When this bit is set to 1, an FOVI interrupt requested by
the OVF flag in TRCSR is enabled.
6 to 4  All 1  Reserved
These bits are always read as 1.
3 IMIED 0 R/W Input Capture/Compare Match Interrupt Enable D
When this bit is set to 1, an IMID interrupt requested by
the IMFD flag in TRCSR is enabled.
2 IMIEC 0 R/W Input Capture/Compare Match Interrupt Enable C
When this bit is set to 1, an IMIC interrupt requested by
the IMFC flag in TRCSR is enabled.
1 IMIEB 0 R/W Input Capture/Compare Match Interrupt Enable B
When this bit is set to 1, an IMIB interrupt requested by
the IMFB flag in TRCSR is enabled.
0 IMIEA 0 R/W Input Capture/Compare Match Interrupt Enable A
When this bit is set to 1, an IMIA interrupt requested by
the IMFA flag in TRCSR is enabled.