Datasheet

Section 13 Timer RC
Rev. 1.50 Sep. 18, 2007 Page 227 of 584
REJ09B0240-0150
13.3.5 Timer RC Status Register (TRCSR)
TRCSR shows the status of interrupt requests.
Bit Bit Name
Initial
Value R/W Description
7 OVF 0 R/W Timer Overflow Flag
[Setting condition]
When TRCCNT overflows from H'FFFF to H'0000
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
6 to 4  All 1  Reserved
These bits are always read as 1.
3 IMFD 0 R/W Input Capture/Compare Match Flag D
[Setting conditions]
• TRCCNT = GRD when GRD functions as an output
compare register
• The TRCCNT value is transferred to GRD by an input
capture signal when GRD functions as an input
capture register
• TRCCNT = GRD when the PWMD bit is set to 1 or
the PWM2 bit to 0 in TRCMR
[Clearing condition]
Read IMFD when IMFD = 1, then write 0 in IMFD
2 IMFC 0 R/W Input Capture/Compare Match Flag C
[Setting conditions]
• TRCCNT = GRC when GRC functions as an output
compare register
• The TRCCNT value is transferred to GRC by an input
capture signal when GRC functions as an input
capture register
• TRCCNT = GRC when the PWMC bit is set to 1 or
the PWM2 bit to 0 in TRCMR
[Clearing condition]
Read IMFC when IMFC = 1, then write 0 in IMFC