Datasheet

Section 13 Timer RC
Rev. 1.50 Sep. 18, 2007 Page 230 of 584
REJ09B0240-0150
Bit Bit Name
Initial
Value R/W Description
1
0
IOA1
IOA0
0
0
R/W
R/W
I/O Control A1 and A0
When IOA2 = 0,
00: No output at compare match
01: 0 output to the FTIOA pin at GRA compare match
10: 1 output to the FTIOA pin at GRA compare match
11: Output toggles to the FTIOA pin at GRA compare
match
When IOA2 = 1,
00: Input capture at rising edge of the FTIOA pin
01: Input capture at falling edge of the FTIOA pin
1X: Input capture at rising and falling edges of the FTIOA
pin
[Legend]
X: Don't care.
Note: When a GR register functions as a buffer register for a paired GR register, the settings in
the IOA2 and IOB2 bits in TRCIOR0 and the IOC2 and IOD2 bits in TRCIOR1 of both
registers should be the same.