Datasheet

Section 13 Timer RC
Rev. 1.50 Sep. 18, 2007 Page 234 of 584
REJ09B0240-0150
13.3.9 Timer RC Digital Filtering Function Select Register (TRCDF)
TRCDF enables or disables the digital filter for each of the FTIOA to FTIOD and TRGC pin. The
setting in this register is valid on the corresponding pin when the FTIOA to FTIOA inputs are
enabled by TRCIOR0 and TRCIOR1 and the TRGC input is selected by bits TCEG1 and TCEG0
in TRCCR2.
Bit Bit Name
Initial
Value R/W Description
7
6
DFCK1
DFCK0
0
0
R/W
R/W
These bits select the clock to be used by the digital
filter.
00: φ/32
01: φ/8
10: φ
11: Clock specified by bits CKS2 to CKS0 in TRCCR1
5 — 0 — Reserved
This bit is always read as 0.
4 DFRG 0 R/W Enables or disables the digital filter for the TRGC pin.
0: Disables the digital filter
1: Enables the digital filter
3 DFD 0 R/W Enables or disables the digital filter for the FTIOD pin.
0: Disables the digital filter
1: Enables the digital filter
2 DFC 0 R/W Enables or disables the digital filter for the FTIOC pin.
0: Disables the digital filter
1: Enables the digital filter
1 DFB 0 R/W Enables or disables the digital filter for the FTIOB pin.
0: Disables the digital filter
1: Enables the digital filter
0 DFA 0 R/W Enables or disables the digital filter for the FTIOA pin.
0: Disables the digital filter
1: Enables the digital filter