Datasheet

Section 13 Timer RC
Rev. 1.50 Sep. 18, 2007 Page 243 of 584
REJ09B0240-0150
13.4.2 PWM Mode Operation
In PWM mode, PWM waveforms are generated by using GRA as the cycle register and GRB,
GRC, and GRD as duty cycle registers. PWM waveforms are output from the FTIOB, FTIOC, and
FTIOD pins. Up to three-phase PWM waveforms can be output. In PWM mode, a general register
functions as an output compare register automatically. The output level of each pin depends on the
corresponding timer output level set bit (TOB, TOC, or TOD) in TRCCR1. When the TOB bit is
set to 1, the FTIOB output goes 1 on compare match A and 0 on compare match B. When the
TOB bit is cleared to 0, the FTIOB output goes 0 on compare match A and 1 on compare match B.
When an output pin is set to PWM mode, the settings in TRCIOR0 and TRCIOR1 are ignored. If
the same value is set in the cycle register and duty cycle register, output levels are not changed
when a compare match occurs.
Figure 13.9 shows an example of operation in PWM mode. The output signals go 1 (TOB = TOC
= TOD = 1) and TRCCNT is cleared on compare match A, and the output signals go 0 on compare
match B, C, and D .
TRCCNT
GRA
GRB
GRC
H'0000
FTIOB
FTIOC
FTIOD
Time
GRD
Counter cleared by compare match A
Figure 13.9 PWM Mode Example (1)
Figure 13.10 shows another example of operation in PWM mode. The output signals go 0 (TOB =
TOC = TOD = 0) and TRCCNT is cleared on compare match A, and the output signals go 1 on
compare match B, C, and D .