Datasheet

Rev. 1.50 Sep. 18, 2007 Page xxvi of xxxiv
Figure 14.52 Example of Output Inverse Timing of Timer RD by Writing to TRDFCR........... 345
Figure 14.53 Example of Output Inverse Timing of Timer RD by Writing to POCR................ 345
Figure 14.54 Block Diagram of Digital Filter ............................................................................ 346
Figure 14.55 Block Diagram of Output Pins for GR .................................................................. 347
Figure 14.56 Example of Non-Overlapped Pulses Output on Pins FTIOA0 and FTIOB0
(TRDCNT_0 Used)............................................................................................... 348
Figure 14.57 Example of Non-Overlapped Pulses Output on Pins FTIOA1 and FTIOB1
(TRDCNT_1 Used)............................................................................................... 348
Figure 14.58 IMF Flag Set Timing when Compare Match Occurs ............................................ 349
Figure 14.59 IMF Flag Set Timing at Input Capture .................................................................. 350
Figure 14.60 OVF Flag Set Timing............................................................................................ 350
Figure 14.61 Status Flag Clearing Timing.................................................................................. 351
Figure 14.62 Conflict between TRDCNT Write and Clear Operations...................................... 352
Figure 14.63 Conflict between TRDCNT Write and Increment Operations .............................. 352
Figure 14.64 Conflict between GR Write and Compare Match.................................................. 353
Figure 14.65 Conflict between TRDCNT Write and Overflow.................................................. 354
Figure 14.66 Conflict between GR Read and Input Capture ...................................................... 355
Figure 14.67 Conflict between Count Clearing and Increment Operations by Input Capture.... 355
Figure 14.68 Conflict between GR Write and Input Capture ..................................................... 356
Figure 14.69 When Compare Match and Bit Manipulation Instruction to TRDOCR Occur
at the Same Timing ............................................................................................... 358
Section 15 Watchdog Timer
Figure 15.1 Block Diagram of Watchdog Timer........................................................................ 359
Figure 15.2 Watchdog Timer Operation Example...................................................................... 363
Section 16 14-Bit PWM
Figure 16.1 Block Diagram of 14-Bit PWM .............................................................................. 365
Figure 16.2 Waveform Output by 14-Bit PWM ......................................................................... 368
Section 17 Serial Communication Interface 3 (SCI3)
Figure 17.1 Block Diagram of SCI3........................................................................................... 372
Figure 17.2 Data Format in Asynchronous Communication ...................................................... 383
Figure 17.3 Relationship between Output Clock and Transfer Data Phase
(Asynchronous Mode)(Example with 8-Bit Data, Parity, Two Stop Bits).............. 383
Figure 17.4 Sample SCI3 Initialization Flowchart ..................................................................... 384
Figure 17.5 Example of SCI3 Transmission in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit) ........................................................................... 385
Figure 17.6 Sample Serial Transmission Data Flowchart
(Asynchronous Mode)............................................................................................. 386
Figure 17.7 Example of SCI3 Reception in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit) ........................................................................... 387