Datasheet

Section 13 Timer RC
Rev. 1.50 Sep. 18, 2007 Page 244 of 584
REJ09B0240-0150
TRCCNT
GRA
GRB
GRC
H'0000
FTIOB
FTIOC
FTIOD
Time
GRD
Counter cleared by compare match A
Figure 13.10 PWM Mode Example (2)
Figure 13.11 shows an example of buffer operation when the FTIOB pin is set to PWM mode and
GRD is set as the buffer register for GRB. TRCCNT is cleared on compare match A, and the
FTIOB pin outputs 1 on compare match B and 0 on compare match A.
Due to the buffer operation, the FTIOB output levels are changed and the value of buffer register
GRD is transferred to GRB whenever compare match B occurs. This procedure is repeated every
time compare match B occurs.
TCNT value
GRA
H'0000
GRD
Time
GRB
H'0200 H'0520
FTIOB
H'0200
H'0450
H'0520
H'0450
GRB
H'0450 H'0520
H'0200
Figure 13.11 Buffer Operation Example (Output Compare)