Datasheet

Section 13 Timer RC
Rev. 1.50 Sep. 18, 2007 Page 247 of 584
REJ09B0240-0150
13.4.3 PWM2 Mode Operation
In PWM2 mode, waveforms are output on the FTIOB pin when a compare match occurs on GRB
or GRC. GRD functions as a buffer register for GRB by setting the BUFEB bit in TRCMR to 1.
The output level of the FTIOB signal is specified by the TOB bit in TRCCR1. When TOB = 0, 1
is output on a compare match of GRC and 0 is output on a compare match of GRB. When TOB =
1, 0 is output on a compare match of GRC and 1 is output on a compare match of GRB.
Table 13.3 shows the correspondence between the pin configuration and GR registers and figure
13.14 is a block diagram of PWM2 mode.
Figures 13.15 and 13.16 show the GRD and GRB buffer operating timing in PWM2 mode.
In PWM2 mode, the value of GRD is transferred to GRB on a compare match of GRA and the
counter is cleared. Note, however, that the counter is only cleared when the CCLR bit in TRCCR1
is set to 1. Moreover, when the trigger input is enabled by the TCEG1 and TCEG0 bits in
TRCCR2, the value of GRD is transferred to GRB by the trigger signal and the counter is cleared.
The input/output pins of timers which do not operate in PWM2 mode are only used as general I/O
ports.
Table 13.3 Pin Configuration in PWM2 Mode and GR Registers
Pin Name Input/Output Compare Match Register Buffer Register
FTIOA I/O Port/TRGC Port/TRGC
FTIOB Output GRB GRD
GRC 
FTIOC I/O Port Port
FTIOD I/O Port Port