Datasheet

Section 13 Timer RC
Rev. 1.50 Sep. 18, 2007 Page 251 of 584
REJ09B0240-0150
The value of TRCCNT
H'FFFF
H'0000
GRA
GRB
GRC
CTS
High
FTIOB
FTIOA/TRGC
FTIOB
(Output transformation
when TOB = 0)
(Output transformation
when TOB = 1)
Time
Figure 13.19 Example of Stopping Operation of the Counter in PWM2 Mode
The following is an example of output operation of the one-shot pulse waveform in PWM2 mode.
When the TRGC input is disabled by TRCCR2 (clearing the TCEG1 and TCEG0 bits to 0),
TRCCNT is set to counting-up on compare match A of GRA (setting the CSTP bit in TRCCR2 to
1), TRCCNT is cleared on compare match A (setting the CCLR bit in TRCCR1 to 1), and the
initial value of the output signal is set to 0 by TRCCR1 (clearing the TOB bit to 0), TRCCNT
starts counting when the CTS bit in TRCMR is set to 1. Then, TRCCNT is cleared to H'0000 on a
compare match of GRA and stops counting, and the one-shot pulse waveform is output. Figure
13.20 shows such an example.
The value of TRCCNT
H'FFFF
H'0000
GRA
GRB
GRC
CTS
High
FTIOB
FTIOA/TRGC
Time
Figure 13.20 Example (1) of Output Operation of One-Shot Pulse Waveform
in PWM2 Mode