Datasheet

Section 13 Timer RC
Rev. 1.50 Sep. 18, 2007 Page 253 of 584
REJ09B0240-0150
13.4.4 Digital Filtering Function for Input Capture Inputs
Input signals on the FTIOA to FIOD and TRGC pin can be input via the digital filters. The digital
filter includes three latches connected in series and a matching detecting circuit. The latches
operate on the sampling clock specified by bits DFCK1 and DFCK0 in TRCDF and stores an
input signal on the FTIOA to FTIOD pins or TRGC pin. When outputs of the three latches match,
the matching detecting circuit outputs the signal level of the input. Otherwise, the output remains
unchanged. That is, when a pulse width is equal to or greater than three sampling clock cycles, the
pulse is input as a signal. When a pulse width is less than three sampling clock cycles, the pulse is
considered as a noise to be removed.
φ40M
φ/32
FTCI
φ/8
φ/4
φ/2
φ
φ, φ40M
CKS2 to
CKS0
DFCK1 and
DFCK2
DFTRG and
DFA to DFD
IOA1, IOA0,
IOD1, and IOD0
Sampling clock
φ/32
φ/8
φ
Matching
detecting
circuit
Selecter
Edge
detecting
circuit
Sampling clock
FTIOA to FTIOD
or TRGC
input signal
C
Latch
DQ
C
Latch
DQ
C
Latch
DQ
C
Latch
D
Q
FTIOA to FTIOD
and TRGC
input signals
Digital-filtered signal
Cycle of a clock specified
by CKS2 to CKS0
or DFCK1 and DFCK0
Signal change is not output unless
signal levels match three times.
Signal propagation delay:
5 sampling clocks
C
Latch
DQ
Figure 13.22 Block Diagram of Digital Filter