Datasheet

Rev. 1.50 Sep. 18, 2007 Page xxvii of xxxiv
Figure 17.8 Sample Serial Reception Data Flowchart (Asynchronous Mode) (1)...................... 389
Figure 17.8 Sample Serial Reception Data Flowchart (Asynchronous Mode) (2)...................... 390
Figure 17.9 Data Format in Clock Synchronous Communication.............................................. 391
Figure 17.10 Example of SCI3 Transmission in Clock Synchronous Mode .............................. 392
Figure 17.11 Sample Serial Transmission Flowchart (Clock Synchronous Mode).................... 393
Figure 17.12 Example of SCI3 Reception in Clock Synchronous Mode.................................... 394
Figure 17.13 Sample Serial Reception Flowchart (Clock Synchronous Mode) ......................... 395
Figure 17.14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
(Clock Synchronous Mode)................................................................................... 396
Figure 17.15 Example of Inter-Processor Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A) .......................................... 398
Figure 17.16 Sample Multiprocessor Serial Transmission Flowchart ........................................ 399
Figure 17.17 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 400
Figure 17.17 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 401
Figure 17.18 Example of SCI3 Reception Using Multiprocessor Format
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit).............................. 402
Figure 17.19 Receive Data Sampling Timing in Asynchronous Mode ...................................... 405
Section 18 I
2
C Bus Interface 2 (IIC2)
Figure 18.1 Block Diagram of I
2
C Bus Interface 2..................................................................... 408
Figure 18.2 External Circuit Connections of I/O Pins ................................................................ 409
Figure 18.3 I
2
C Bus Formats ...................................................................................................... 423
Figure 18.4 I
2
C Bus Timing........................................................................................................ 423
Figure 18.5 Master Transmit Mode Operation Timing (1)......................................................... 425
Figure 18.6 Master Transmit Mode Operation Timing (2)......................................................... 425
Figure 18.7 Master Receive Mode Operation Timing (1)........................................................... 427
Figure 18.8 Master Receive Mode Operation Timing (2)........................................................... 427
Figure 18.9 Slave Transmit Mode Operation Timing (1) ........................................................... 429
Figure 18.10 Slave Transmit Mode Operation Timing (2) ......................................................... 430
Figure 18.11 Slave Receive Mode Operation Timing (1)........................................................... 431
Figure 18.12 Slave Receive Mode Operation Timing (2)........................................................... 432
Figure 18.13 Clocked Synchronous Serial Transfer Format....................................................... 432
Figure 18.14 Transmit Mode Operation Timing......................................................................... 433
Figure 18.15 Receive Mode Operation Timing .......................................................................... 434
Figure 18.16 Block Diagram of Noise Canceller........................................................................ 435
Figure 18.17 Sample Flowchart for Master Transmit Mode.......................................................436
Figure 18.18 Sample Flowchart for Master Receive Mode ........................................................437
Figure 18.19 Sample Flowchart for Slave Transmit Mode......................................................... 438
Figure 18.20 Sample Flowchart for Slave Receive Mode .......................................................... 439
Figure 18.21 Timing of Bit Synchronous Circuit ....................................................................... 441